[linux-2.6-block.git] / arch / arm / boot / dts / imx6qp.dtsi

/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "imx6q.dtsi"

/ {
	soc {
		ocram2: sram@940000 {
			compatible = "mmio-sram";
			reg = <0x00940000 0x20000>;
			clocks = <&clks IMX6QDL_CLK_OCRAM>;
		};

		ocram3: sram@960000 {
			compatible = "mmio-sram";
			reg = <0x00960000 0x20000>;
			clocks = <&clks IMX6QDL_CLK_OCRAM>;
		};

		aips-bus@2100000 {
			pre1: pre@21c8000 {
				compatible = "fsl,imx6qp-pre";
				reg = <0x021c8000 0x1000>;
				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clks IMX6QDL_CLK_PRE0>;
				clock-names = "axi";
				fsl,iram = <&ocram2>;
			};

			pre2: pre@21c9000 {
				compatible = "fsl,imx6qp-pre";
				reg = <0x021c9000 0x1000>;
				interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clks IMX6QDL_CLK_PRE1>;
				clock-names = "axi";
				fsl,iram = <&ocram2>;
			};

			pre3: pre@21ca000 {
				compatible = "fsl,imx6qp-pre";
				reg = <0x021ca000 0x1000>;
				interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clks IMX6QDL_CLK_PRE2>;
				clock-names = "axi";
				fsl,iram = <&ocram3>;
			};

			pre4: pre@21cb000 {
				compatible = "fsl,imx6qp-pre";
				reg = <0x021cb000 0x1000>;
				interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clks IMX6QDL_CLK_PRE3>;
				clock-names = "axi";
				fsl,iram = <&ocram3>;
			};

			prg1: prg@21cc000 {
				compatible = "fsl,imx6qp-prg";
				reg = <0x021cc000 0x1000>;
				clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
					 <&clks IMX6QDL_CLK_PRG0_AXI>;
				clock-names = "ipg", "axi";
				fsl,pres = <&pre1>, <&pre2>, <&pre3>;
			};

			prg2: prg@21cd000 {
				compatible = "fsl,imx6qp-prg";
				reg = <0x021cd000 0x1000>;
				clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
					 <&clks IMX6QDL_CLK_PRG1_AXI>;
				clock-names = "ipg", "axi";
				fsl,pres = <&pre4>, <&pre2>, <&pre3>;
			};
		};
	};
};

&fec {
	/delete-property/interrupts-extended;
	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
		     <0 119 IRQ_TYPE_LEVEL_HIGH>;
};

&gpc {
	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
};

&ipu1 {
	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
	fsl,prg = <&prg1>;
};

&ipu2 {
	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
	fsl,prg = <&prg2>;
};

&ldb {
	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
		 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
	clock-names = "di0_pll", "di1_pll",
		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
		      "di0", "di1";
};

&mmdc0 {
	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
};

&pcie {
	compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
};
Commit	Line	Data
5d625375 BP	1	/*
	2	* Copyright 2016 Freescale Semiconductor, Inc.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include "imx6q.dtsi"
	44
	45	/ {
	46	soc {
8dccafaa	47	ocram2: sram@940000 {
5d625375 BP	48	compatible = "mmio-sram";
	49	reg = <0x00940000 0x20000>;
	50	clocks = <&clks IMX6QDL_CLK_OCRAM>;
	51	};
	52
8dccafaa	53	ocram3: sram@960000 {
5d625375 BP	54	compatible = "mmio-sram";
	55	reg = <0x00960000 0x20000>;
	56	clocks = <&clks IMX6QDL_CLK_OCRAM>;
	57	};
3062cf55	58
8dccafaa	59	aips-bus@2100000 {
3062cf55 LS	60	pre1: pre@21c8000 {
	61	compatible = "fsl,imx6qp-pre";
	62	reg = <0x021c8000 0x1000>;
	63	interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
	64	clocks = <&clks IMX6QDL_CLK_PRE0>;
	65	clock-names = "axi";
	66	fsl,iram = <&ocram2>;
	67	};
	68
	69	pre2: pre@21c9000 {
	70	compatible = "fsl,imx6qp-pre";
	71	reg = <0x021c9000 0x1000>;
	72	interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
	73	clocks = <&clks IMX6QDL_CLK_PRE1>;
	74	clock-names = "axi";
	75	fsl,iram = <&ocram2>;
	76	};
	77
	78	pre3: pre@21ca000 {
	79	compatible = "fsl,imx6qp-pre";
	80	reg = <0x021ca000 0x1000>;
	81	interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
	82	clocks = <&clks IMX6QDL_CLK_PRE2>;
	83	clock-names = "axi";
	84	fsl,iram = <&ocram3>;
	85	};
	86
	87	pre4: pre@21cb000 {
	88	compatible = "fsl,imx6qp-pre";
	89	reg = <0x021cb000 0x1000>;
	90	interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
	91	clocks = <&clks IMX6QDL_CLK_PRE3>;
	92	clock-names = "axi";
	93	fsl,iram = <&ocram3>;
	94	};
54458dac LS	95
	96	prg1: prg@21cc000 {
	97	compatible = "fsl,imx6qp-prg";
	98	reg = <0x021cc000 0x1000>;
	99	clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
	100	<&clks IMX6QDL_CLK_PRG0_AXI>;
	101	clock-names = "ipg", "axi";
	102	fsl,pres = <&pre1>, <&pre2>, <&pre3>;
	103	};
	104
	105	prg2: prg@21cd000 {
	106	compatible = "fsl,imx6qp-prg";
	107	reg = <0x021cd000 0x1000>;
	108	clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
	109	<&clks IMX6QDL_CLK_PRG1_AXI>;
	110	clock-names = "ipg", "axi";
	111	fsl,pres = <&pre4>, <&pre2>, <&pre3>;
	112	};
3062cf55	113	};
5d625375 BP	114	};
5d625375 BP	115	};
df38e42f	116
7c3f8363 LS	117	&fec {
	118	/delete-property/interrupts-extended;
	119	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
	120	<0 119 IRQ_TYPE_LEVEL_HIGH>;
	121	};
	122
6447a053 LS	123	&gpc {
	124	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
	125	};
	126
4901f343 LS	127	&ipu1 {
4901f343 LS	128	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
54458dac	129	fsl,prg = <&prg1>;
4901f343 LS	130	};
	131
	132	&ipu2 {
	133	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
54458dac	134	fsl,prg = <&prg2>;
4901f343 LS	135	};
4901f343 LS	136
df38e42f LS	137	&ldb {
	138	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	139	<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
	140	<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
	141	<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
	142	clock-names = "di0_pll", "di1_pll",
	143	"di0_sel", "di1_sel", "di2_sel", "di3_sel",
	144	"di0", "di1";
	145	};
3b3a95c8	146
c871b91e LS	147	&mmdc0 {
	148	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
	149	};
	150
3b3a95c8 LS	151	&pcie {
	152	compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
	153	};