Commit | Line | Data |
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7d740f87 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
8888f651 | 13 | #include <dt-bindings/clock/imx6qdl-clock.h> |
07134a36 LS |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | ||
36dffd8f | 16 | #include "skeleton.dtsi" |
7d740f87 SG |
17 | |
18 | / { | |
19 | aliases { | |
22970070 | 20 | ethernet0 = &fec; |
5f8fbc2c LW |
21 | can0 = &can1; |
22 | can1 = &can2; | |
5230f8fe SG |
23 | gpio0 = &gpio1; |
24 | gpio1 = &gpio2; | |
25 | gpio2 = &gpio3; | |
26 | gpio3 = &gpio4; | |
27 | gpio4 = &gpio5; | |
28 | gpio5 = &gpio6; | |
29 | gpio6 = &gpio7; | |
80fa0584 SH |
30 | i2c0 = &i2c1; |
31 | i2c1 = &i2c2; | |
32 | i2c2 = &i2c3; | |
fb06d65c SH |
33 | mmc0 = &usdhc1; |
34 | mmc1 = &usdhc2; | |
35 | mmc2 = &usdhc3; | |
36 | mmc3 = &usdhc4; | |
80fa0584 SH |
37 | serial0 = &uart1; |
38 | serial1 = &uart2; | |
39 | serial2 = &uart3; | |
40 | serial3 = &uart4; | |
41 | serial4 = &uart5; | |
42 | spi0 = &ecspi1; | |
43 | spi1 = &ecspi2; | |
44 | spi2 = &ecspi3; | |
45 | spi3 = &ecspi4; | |
8189c51f PC |
46 | usbphy0 = &usbphy1; |
47 | usbphy1 = &usbphy2; | |
7d740f87 SG |
48 | }; |
49 | ||
7d740f87 SG |
50 | intc: interrupt-controller@00a01000 { |
51 | compatible = "arm,cortex-a9-gic"; | |
52 | #interrupt-cells = <3>; | |
7d740f87 SG |
53 | interrupt-controller; |
54 | reg = <0x00a01000 0x1000>, | |
55 | <0x00a00100 0x100>; | |
b923ff6a | 56 | interrupt-parent = <&intc>; |
7d740f87 SG |
57 | }; |
58 | ||
59 | clocks { | |
60 | #address-cells = <1>; | |
61 | #size-cells = <0>; | |
62 | ||
63 | ckil { | |
64 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
4b2b4043 | 65 | #clock-cells = <0>; |
7d740f87 SG |
66 | clock-frequency = <32768>; |
67 | }; | |
68 | ||
69 | ckih1 { | |
70 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
4b2b4043 | 71 | #clock-cells = <0>; |
7d740f87 SG |
72 | clock-frequency = <0>; |
73 | }; | |
74 | ||
75 | osc { | |
76 | compatible = "fsl,imx-osc", "fixed-clock"; | |
4b2b4043 | 77 | #clock-cells = <0>; |
7d740f87 SG |
78 | clock-frequency = <24000000>; |
79 | }; | |
80 | }; | |
81 | ||
82 | soc { | |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | compatible = "simple-bus"; | |
b923ff6a | 86 | interrupt-parent = <&gpc>; |
7d740f87 SG |
87 | ranges; |
88 | ||
f30fb03d | 89 | dma_apbh: dma-apbh@00110000 { |
e5d0f9f5 HS |
90 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
91 | reg = <0x00110000 0x2000>; | |
275c08b5 TK |
92 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
93 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
94 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
95 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
f30fb03d SG |
96 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
97 | #dma-cells = <1>; | |
98 | dma-channels = <4>; | |
8888f651 | 99 | clocks = <&clks IMX6QDL_CLK_APBH_DMA>; |
e5d0f9f5 HS |
100 | }; |
101 | ||
be4ccfce | 102 | gpmi: gpmi-nand@00112000 { |
0e87e043 SG |
103 | compatible = "fsl,imx6q-gpmi-nand"; |
104 | #address-cells = <1>; | |
105 | #size-cells = <1>; | |
106 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
107 | reg-names = "gpmi-nand", "bch"; | |
275c08b5 | 108 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
c7aa12a6 | 109 | interrupt-names = "bch"; |
8888f651 SG |
110 | clocks = <&clks IMX6QDL_CLK_GPMI_IO>, |
111 | <&clks IMX6QDL_CLK_GPMI_APB>, | |
112 | <&clks IMX6QDL_CLK_GPMI_BCH>, | |
113 | <&clks IMX6QDL_CLK_GPMI_BCH_APB>, | |
114 | <&clks IMX6QDL_CLK_PER1_BCH>; | |
0e87e043 SG |
115 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
116 | "gpmi_bch_apb", "per1_bch"; | |
f30fb03d SG |
117 | dmas = <&dma_apbh 0>; |
118 | dma-names = "rx-tx"; | |
0e87e043 | 119 | status = "disabled"; |
cf922fa8 HS |
120 | }; |
121 | ||
ac4af82b LS |
122 | hdmi: hdmi@0120000 { |
123 | #address-cells = <1>; | |
124 | #size-cells = <0>; | |
125 | reg = <0x00120000 0x9000>; | |
126 | interrupts = <0 115 0x04>; | |
127 | gpr = <&gpr>; | |
128 | clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, | |
129 | <&clks IMX6QDL_CLK_HDMI_ISFR>; | |
130 | clock-names = "iahb", "isfr"; | |
131 | status = "disabled"; | |
132 | ||
133 | port@0 { | |
134 | reg = <0>; | |
135 | ||
136 | hdmi_mux_0: endpoint { | |
137 | remote-endpoint = <&ipu1_di0_hdmi>; | |
138 | }; | |
139 | }; | |
140 | ||
141 | port@1 { | |
142 | reg = <1>; | |
143 | ||
144 | hdmi_mux_1: endpoint { | |
145 | remote-endpoint = <&ipu1_di1_hdmi>; | |
146 | }; | |
147 | }; | |
148 | }; | |
149 | ||
7d740f87 | 150 | timer@00a00600 { |
58458e03 MZ |
151 | compatible = "arm,cortex-a9-twd-timer"; |
152 | reg = <0x00a00600 0x20>; | |
153 | interrupts = <1 13 0xf01>; | |
b923ff6a | 154 | interrupt-parent = <&intc>; |
8888f651 | 155 | clocks = <&clks IMX6QDL_CLK_TWD>; |
7d740f87 SG |
156 | }; |
157 | ||
158 | L2: l2-cache@00a02000 { | |
159 | compatible = "arm,pl310-cache"; | |
160 | reg = <0x00a02000 0x1000>; | |
275c08b5 | 161 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
162 | cache-unified; |
163 | cache-level = <2>; | |
5a5ca56e DB |
164 | arm,tag-latency = <4 2 3>; |
165 | arm,data-latency = <4 2 3>; | |
7d740f87 SG |
166 | }; |
167 | ||
3a57291f SC |
168 | pcie: pcie@0x01000000 { |
169 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | |
fcd17303 LS |
170 | reg = <0x01ffc000 0x04000>, |
171 | <0x01f00000 0x80000>; | |
172 | reg-names = "dbi", "config"; | |
3a57291f SC |
173 | #address-cells = <3>; |
174 | #size-cells = <2>; | |
175 | device_type = "pci"; | |
176 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ | |
177 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | |
178 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | |
179 | num-lanes = <1>; | |
92a7eb7c LS |
180 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
181 | interrupt-names = "msi"; | |
07134a36 LS |
182 | #interrupt-cells = <1>; |
183 | interrupt-map-mask = <0 0 0 0x7>; | |
1a9fa190 LS |
184 | interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
185 | <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
188 | clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, |
189 | <&clks IMX6QDL_CLK_LVDS1_GATE>, | |
190 | <&clks IMX6QDL_CLK_PCIE_REF_125M>; | |
92a7eb7c | 191 | clock-names = "pcie", "pcie_bus", "pcie_phy"; |
3a57291f SC |
192 | status = "disabled"; |
193 | }; | |
194 | ||
218abe6f DB |
195 | pmu { |
196 | compatible = "arm,cortex-a9-pmu"; | |
275c08b5 | 197 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
218abe6f DB |
198 | }; |
199 | ||
7d740f87 SG |
200 | aips-bus@02000000 { /* AIPS1 */ |
201 | compatible = "fsl,aips-bus", "simple-bus"; | |
202 | #address-cells = <1>; | |
203 | #size-cells = <1>; | |
204 | reg = <0x02000000 0x100000>; | |
205 | ranges; | |
206 | ||
207 | spba-bus@02000000 { | |
208 | compatible = "fsl,spba-bus", "simple-bus"; | |
209 | #address-cells = <1>; | |
210 | #size-cells = <1>; | |
211 | reg = <0x02000000 0x40000>; | |
212 | ranges; | |
213 | ||
7b7d6727 | 214 | spdif: spdif@02004000 { |
c9d96df2 | 215 | compatible = "fsl,imx35-spdif"; |
7d740f87 | 216 | reg = <0x02004000 0x4000>; |
275c08b5 | 217 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
c9d96df2 FE |
218 | dmas = <&sdma 14 18 0>, |
219 | <&sdma 15 18 0>; | |
220 | dma-names = "rx", "tx"; | |
8888f651 SG |
221 | clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>, |
222 | <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, | |
223 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, | |
224 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, | |
225 | <&clks IMX6QDL_CLK_DUMMY>; | |
c9d96df2 FE |
226 | clock-names = "core", "rxtx0", |
227 | "rxtx1", "rxtx2", | |
228 | "rxtx3", "rxtx4", | |
229 | "rxtx5", "rxtx6", | |
230 | "rxtx7"; | |
231 | status = "disabled"; | |
7d740f87 SG |
232 | }; |
233 | ||
7b7d6727 | 234 | ecspi1: ecspi@02008000 { |
7d740f87 SG |
235 | #address-cells = <1>; |
236 | #size-cells = <0>; | |
237 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
238 | reg = <0x02008000 0x4000>; | |
275c08b5 | 239 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
240 | clocks = <&clks IMX6QDL_CLK_ECSPI1>, |
241 | <&clks IMX6QDL_CLK_ECSPI1>; | |
0e87e043 | 242 | clock-names = "ipg", "per"; |
b3810c3d FL |
243 | dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; |
244 | dma-names = "rx", "tx"; | |
7d740f87 SG |
245 | status = "disabled"; |
246 | }; | |
247 | ||
7b7d6727 | 248 | ecspi2: ecspi@0200c000 { |
7d740f87 SG |
249 | #address-cells = <1>; |
250 | #size-cells = <0>; | |
251 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
252 | reg = <0x0200c000 0x4000>; | |
275c08b5 | 253 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
254 | clocks = <&clks IMX6QDL_CLK_ECSPI2>, |
255 | <&clks IMX6QDL_CLK_ECSPI2>; | |
0e87e043 | 256 | clock-names = "ipg", "per"; |
b3810c3d FL |
257 | dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; |
258 | dma-names = "rx", "tx"; | |
7d740f87 SG |
259 | status = "disabled"; |
260 | }; | |
261 | ||
7b7d6727 | 262 | ecspi3: ecspi@02010000 { |
7d740f87 SG |
263 | #address-cells = <1>; |
264 | #size-cells = <0>; | |
265 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
266 | reg = <0x02010000 0x4000>; | |
275c08b5 | 267 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
268 | clocks = <&clks IMX6QDL_CLK_ECSPI3>, |
269 | <&clks IMX6QDL_CLK_ECSPI3>; | |
0e87e043 | 270 | clock-names = "ipg", "per"; |
b3810c3d FL |
271 | dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; |
272 | dma-names = "rx", "tx"; | |
7d740f87 SG |
273 | status = "disabled"; |
274 | }; | |
275 | ||
7b7d6727 | 276 | ecspi4: ecspi@02014000 { |
7d740f87 SG |
277 | #address-cells = <1>; |
278 | #size-cells = <0>; | |
279 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
280 | reg = <0x02014000 0x4000>; | |
275c08b5 | 281 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
282 | clocks = <&clks IMX6QDL_CLK_ECSPI4>, |
283 | <&clks IMX6QDL_CLK_ECSPI4>; | |
0e87e043 | 284 | clock-names = "ipg", "per"; |
b3810c3d FL |
285 | dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; |
286 | dma-names = "rx", "tx"; | |
7d740f87 SG |
287 | status = "disabled"; |
288 | }; | |
289 | ||
0c456cfa | 290 | uart1: serial@02020000 { |
7d740f87 SG |
291 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
292 | reg = <0x02020000 0x4000>; | |
275c08b5 | 293 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
294 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
295 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 296 | clock-names = "ipg", "per"; |
72a5cebf HS |
297 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
298 | dma-names = "rx", "tx"; | |
7d740f87 SG |
299 | status = "disabled"; |
300 | }; | |
301 | ||
7b7d6727 | 302 | esai: esai@02024000 { |
7d740f87 | 303 | reg = <0x02024000 0x4000>; |
275c08b5 | 304 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
305 | }; |
306 | ||
b1a5da8e | 307 | ssi1: ssi@02028000 { |
6ff7f51e | 308 | #sound-dai-cells = <0>; |
98ea6ad2 | 309 | compatible = "fsl,imx6q-ssi", |
4c03527e | 310 | "fsl,imx51-ssi"; |
7d740f87 | 311 | reg = <0x02028000 0x4000>; |
275c08b5 | 312 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
313 | clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, |
314 | <&clks IMX6QDL_CLK_SSI1>; | |
315 | clock-names = "ipg", "baud"; | |
5da826ab SG |
316 | dmas = <&sdma 37 1 0>, |
317 | <&sdma 38 1 0>; | |
318 | dma-names = "rx", "tx"; | |
b1a5da8e | 319 | fsl,fifo-depth = <15>; |
b1a5da8e | 320 | status = "disabled"; |
7d740f87 SG |
321 | }; |
322 | ||
b1a5da8e | 323 | ssi2: ssi@0202c000 { |
6ff7f51e | 324 | #sound-dai-cells = <0>; |
98ea6ad2 | 325 | compatible = "fsl,imx6q-ssi", |
4c03527e | 326 | "fsl,imx51-ssi"; |
7d740f87 | 327 | reg = <0x0202c000 0x4000>; |
275c08b5 | 328 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
329 | clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, |
330 | <&clks IMX6QDL_CLK_SSI2>; | |
331 | clock-names = "ipg", "baud"; | |
5da826ab SG |
332 | dmas = <&sdma 41 1 0>, |
333 | <&sdma 42 1 0>; | |
334 | dma-names = "rx", "tx"; | |
b1a5da8e | 335 | fsl,fifo-depth = <15>; |
b1a5da8e | 336 | status = "disabled"; |
7d740f87 SG |
337 | }; |
338 | ||
b1a5da8e | 339 | ssi3: ssi@02030000 { |
6ff7f51e | 340 | #sound-dai-cells = <0>; |
98ea6ad2 | 341 | compatible = "fsl,imx6q-ssi", |
4c03527e | 342 | "fsl,imx51-ssi"; |
7d740f87 | 343 | reg = <0x02030000 0x4000>; |
275c08b5 | 344 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
345 | clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, |
346 | <&clks IMX6QDL_CLK_SSI3>; | |
347 | clock-names = "ipg", "baud"; | |
5da826ab SG |
348 | dmas = <&sdma 45 1 0>, |
349 | <&sdma 46 1 0>; | |
350 | dma-names = "rx", "tx"; | |
b1a5da8e | 351 | fsl,fifo-depth = <15>; |
b1a5da8e | 352 | status = "disabled"; |
7d740f87 SG |
353 | }; |
354 | ||
7b7d6727 | 355 | asrc: asrc@02034000 { |
7d740f87 | 356 | reg = <0x02034000 0x4000>; |
275c08b5 | 357 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
358 | }; |
359 | ||
360 | spba@0203c000 { | |
361 | reg = <0x0203c000 0x4000>; | |
362 | }; | |
363 | }; | |
364 | ||
7b7d6727 | 365 | vpu: vpu@02040000 { |
a04a0b6f | 366 | compatible = "cnm,coda960"; |
7d740f87 | 367 | reg = <0x02040000 0x3c000>; |
b2faf1a1 PZ |
368 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, |
369 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
a04a0b6f PZ |
370 | interrupt-names = "bit", "jpeg"; |
371 | clocks = <&clks IMX6QDL_CLK_VPU_AXI>, | |
c9997ba2 FE |
372 | <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; |
373 | clock-names = "per", "ahb"; | |
29eea64c | 374 | power-domains = <&gpc 1>; |
a04a0b6f PZ |
375 | resets = <&src 1>; |
376 | iram = <&ocram>; | |
7d740f87 SG |
377 | }; |
378 | ||
379 | aipstz@0207c000 { /* AIPSTZ1 */ | |
380 | reg = <0x0207c000 0x4000>; | |
381 | }; | |
382 | ||
7b7d6727 | 383 | pwm1: pwm@02080000 { |
33b38587 SH |
384 | #pwm-cells = <2>; |
385 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 386 | reg = <0x02080000 0x4000>; |
275c08b5 | 387 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
388 | clocks = <&clks IMX6QDL_CLK_IPG>, |
389 | <&clks IMX6QDL_CLK_PWM1>; | |
33b38587 | 390 | clock-names = "ipg", "per"; |
e2675266 | 391 | status = "disabled"; |
7d740f87 SG |
392 | }; |
393 | ||
7b7d6727 | 394 | pwm2: pwm@02084000 { |
33b38587 SH |
395 | #pwm-cells = <2>; |
396 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 397 | reg = <0x02084000 0x4000>; |
275c08b5 | 398 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
399 | clocks = <&clks IMX6QDL_CLK_IPG>, |
400 | <&clks IMX6QDL_CLK_PWM2>; | |
33b38587 | 401 | clock-names = "ipg", "per"; |
e2675266 | 402 | status = "disabled"; |
7d740f87 SG |
403 | }; |
404 | ||
7b7d6727 | 405 | pwm3: pwm@02088000 { |
33b38587 SH |
406 | #pwm-cells = <2>; |
407 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 408 | reg = <0x02088000 0x4000>; |
275c08b5 | 409 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
410 | clocks = <&clks IMX6QDL_CLK_IPG>, |
411 | <&clks IMX6QDL_CLK_PWM3>; | |
33b38587 | 412 | clock-names = "ipg", "per"; |
e2675266 | 413 | status = "disabled"; |
7d740f87 SG |
414 | }; |
415 | ||
7b7d6727 | 416 | pwm4: pwm@0208c000 { |
33b38587 SH |
417 | #pwm-cells = <2>; |
418 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 419 | reg = <0x0208c000 0x4000>; |
275c08b5 | 420 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
421 | clocks = <&clks IMX6QDL_CLK_IPG>, |
422 | <&clks IMX6QDL_CLK_PWM4>; | |
33b38587 | 423 | clock-names = "ipg", "per"; |
e2675266 | 424 | status = "disabled"; |
7d740f87 SG |
425 | }; |
426 | ||
7b7d6727 | 427 | can1: flexcan@02090000 { |
0f225212 | 428 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 | 429 | reg = <0x02090000 0x4000>; |
275c08b5 | 430 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
431 | clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, |
432 | <&clks IMX6QDL_CLK_CAN1_SERIAL>; | |
0f225212 | 433 | clock-names = "ipg", "per"; |
a1135337 | 434 | status = "disabled"; |
7d740f87 SG |
435 | }; |
436 | ||
7b7d6727 | 437 | can2: flexcan@02094000 { |
0f225212 | 438 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 | 439 | reg = <0x02094000 0x4000>; |
275c08b5 | 440 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
441 | clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, |
442 | <&clks IMX6QDL_CLK_CAN2_SERIAL>; | |
0f225212 | 443 | clock-names = "ipg", "per"; |
a1135337 | 444 | status = "disabled"; |
7d740f87 SG |
445 | }; |
446 | ||
7b7d6727 | 447 | gpt: gpt@02098000 { |
97b108f9 | 448 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
7d740f87 | 449 | reg = <0x02098000 0x4000>; |
275c08b5 | 450 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 451 | clocks = <&clks IMX6QDL_CLK_GPT_IPG>, |
2b2244a3 AH |
452 | <&clks IMX6QDL_CLK_GPT_IPG_PER>, |
453 | <&clks IMX6QDL_CLK_GPT_3M>; | |
454 | clock-names = "ipg", "per", "osc_per"; | |
7d740f87 SG |
455 | }; |
456 | ||
4d191868 | 457 | gpio1: gpio@0209c000 { |
aeb27748 | 458 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 459 | reg = <0x0209c000 0x4000>; |
275c08b5 TK |
460 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
461 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
462 | gpio-controller; |
463 | #gpio-cells = <2>; | |
464 | interrupt-controller; | |
88cde8b7 | 465 | #interrupt-cells = <2>; |
7d740f87 SG |
466 | }; |
467 | ||
4d191868 | 468 | gpio2: gpio@020a0000 { |
aeb27748 | 469 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 470 | reg = <0x020a0000 0x4000>; |
275c08b5 TK |
471 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
472 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
473 | gpio-controller; |
474 | #gpio-cells = <2>; | |
475 | interrupt-controller; | |
88cde8b7 | 476 | #interrupt-cells = <2>; |
7d740f87 SG |
477 | }; |
478 | ||
4d191868 | 479 | gpio3: gpio@020a4000 { |
aeb27748 | 480 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 481 | reg = <0x020a4000 0x4000>; |
275c08b5 TK |
482 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
483 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
484 | gpio-controller; |
485 | #gpio-cells = <2>; | |
486 | interrupt-controller; | |
88cde8b7 | 487 | #interrupt-cells = <2>; |
7d740f87 SG |
488 | }; |
489 | ||
4d191868 | 490 | gpio4: gpio@020a8000 { |
aeb27748 | 491 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 492 | reg = <0x020a8000 0x4000>; |
275c08b5 TK |
493 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
494 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
495 | gpio-controller; |
496 | #gpio-cells = <2>; | |
497 | interrupt-controller; | |
88cde8b7 | 498 | #interrupt-cells = <2>; |
7d740f87 SG |
499 | }; |
500 | ||
4d191868 | 501 | gpio5: gpio@020ac000 { |
aeb27748 | 502 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 503 | reg = <0x020ac000 0x4000>; |
275c08b5 TK |
504 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
505 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
506 | gpio-controller; |
507 | #gpio-cells = <2>; | |
508 | interrupt-controller; | |
88cde8b7 | 509 | #interrupt-cells = <2>; |
7d740f87 SG |
510 | }; |
511 | ||
4d191868 | 512 | gpio6: gpio@020b0000 { |
aeb27748 | 513 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 514 | reg = <0x020b0000 0x4000>; |
275c08b5 TK |
515 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, |
516 | <0 77 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
517 | gpio-controller; |
518 | #gpio-cells = <2>; | |
519 | interrupt-controller; | |
88cde8b7 | 520 | #interrupt-cells = <2>; |
7d740f87 SG |
521 | }; |
522 | ||
4d191868 | 523 | gpio7: gpio@020b4000 { |
aeb27748 | 524 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 525 | reg = <0x020b4000 0x4000>; |
275c08b5 TK |
526 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, |
527 | <0 79 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
528 | gpio-controller; |
529 | #gpio-cells = <2>; | |
530 | interrupt-controller; | |
88cde8b7 | 531 | #interrupt-cells = <2>; |
7d740f87 SG |
532 | }; |
533 | ||
7b7d6727 | 534 | kpp: kpp@020b8000 { |
36d3a8f0 | 535 | compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; |
7d740f87 | 536 | reg = <0x020b8000 0x4000>; |
275c08b5 | 537 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 538 | clocks = <&clks IMX6QDL_CLK_IPG>; |
1b6f2368 | 539 | status = "disabled"; |
7d740f87 SG |
540 | }; |
541 | ||
7b7d6727 | 542 | wdog1: wdog@020bc000 { |
7d740f87 SG |
543 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
544 | reg = <0x020bc000 0x4000>; | |
275c08b5 | 545 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 546 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
7d740f87 SG |
547 | }; |
548 | ||
7b7d6727 | 549 | wdog2: wdog@020c0000 { |
7d740f87 SG |
550 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
551 | reg = <0x020c0000 0x4000>; | |
275c08b5 | 552 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 553 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
7d740f87 SG |
554 | status = "disabled"; |
555 | }; | |
556 | ||
0e87e043 | 557 | clks: ccm@020c4000 { |
7d740f87 SG |
558 | compatible = "fsl,imx6q-ccm"; |
559 | reg = <0x020c4000 0x4000>; | |
275c08b5 TK |
560 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
561 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | |
0e87e043 | 562 | #clock-cells = <1>; |
7d740f87 SG |
563 | }; |
564 | ||
baa64151 DA |
565 | anatop: anatop@020c8000 { |
566 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
7d740f87 | 567 | reg = <0x020c8000 0x1000>; |
275c08b5 TK |
568 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
569 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | |
570 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
a1e327e6 YCLP |
571 | |
572 | regulator-1p1@110 { | |
573 | compatible = "fsl,anatop-regulator"; | |
574 | regulator-name = "vdd1p1"; | |
575 | regulator-min-microvolt = <800000>; | |
576 | regulator-max-microvolt = <1375000>; | |
577 | regulator-always-on; | |
578 | anatop-reg-offset = <0x110>; | |
579 | anatop-vol-bit-shift = <8>; | |
580 | anatop-vol-bit-width = <5>; | |
581 | anatop-min-bit-val = <4>; | |
582 | anatop-min-voltage = <800000>; | |
583 | anatop-max-voltage = <1375000>; | |
584 | }; | |
585 | ||
586 | regulator-3p0@120 { | |
587 | compatible = "fsl,anatop-regulator"; | |
588 | regulator-name = "vdd3p0"; | |
589 | regulator-min-microvolt = <2800000>; | |
590 | regulator-max-microvolt = <3150000>; | |
591 | regulator-always-on; | |
592 | anatop-reg-offset = <0x120>; | |
593 | anatop-vol-bit-shift = <8>; | |
594 | anatop-vol-bit-width = <5>; | |
595 | anatop-min-bit-val = <0>; | |
596 | anatop-min-voltage = <2625000>; | |
597 | anatop-max-voltage = <3400000>; | |
598 | }; | |
599 | ||
600 | regulator-2p5@130 { | |
601 | compatible = "fsl,anatop-regulator"; | |
602 | regulator-name = "vdd2p5"; | |
603 | regulator-min-microvolt = <2000000>; | |
604 | regulator-max-microvolt = <2750000>; | |
605 | regulator-always-on; | |
606 | anatop-reg-offset = <0x130>; | |
607 | anatop-vol-bit-shift = <8>; | |
608 | anatop-vol-bit-width = <5>; | |
609 | anatop-min-bit-val = <0>; | |
610 | anatop-min-voltage = <2000000>; | |
611 | anatop-max-voltage = <2750000>; | |
612 | }; | |
613 | ||
96574a6d | 614 | reg_arm: regulator-vddcore@140 { |
a1e327e6 | 615 | compatible = "fsl,anatop-regulator"; |
118c98a6 | 616 | regulator-name = "vddarm"; |
a1e327e6 YCLP |
617 | regulator-min-microvolt = <725000>; |
618 | regulator-max-microvolt = <1450000>; | |
619 | regulator-always-on; | |
620 | anatop-reg-offset = <0x140>; | |
621 | anatop-vol-bit-shift = <0>; | |
622 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
623 | anatop-delay-reg-offset = <0x170>; |
624 | anatop-delay-bit-shift = <24>; | |
625 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
626 | anatop-min-bit-val = <1>; |
627 | anatop-min-voltage = <725000>; | |
628 | anatop-max-voltage = <1450000>; | |
629 | }; | |
630 | ||
96574a6d | 631 | reg_pu: regulator-vddpu@140 { |
a1e327e6 YCLP |
632 | compatible = "fsl,anatop-regulator"; |
633 | regulator-name = "vddpu"; | |
634 | regulator-min-microvolt = <725000>; | |
635 | regulator-max-microvolt = <1450000>; | |
40130d32 | 636 | regulator-enable-ramp-delay = <150>; |
a1e327e6 YCLP |
637 | anatop-reg-offset = <0x140>; |
638 | anatop-vol-bit-shift = <9>; | |
639 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
640 | anatop-delay-reg-offset = <0x170>; |
641 | anatop-delay-bit-shift = <26>; | |
642 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
643 | anatop-min-bit-val = <1>; |
644 | anatop-min-voltage = <725000>; | |
645 | anatop-max-voltage = <1450000>; | |
646 | }; | |
647 | ||
96574a6d | 648 | reg_soc: regulator-vddsoc@140 { |
a1e327e6 YCLP |
649 | compatible = "fsl,anatop-regulator"; |
650 | regulator-name = "vddsoc"; | |
651 | regulator-min-microvolt = <725000>; | |
652 | regulator-max-microvolt = <1450000>; | |
653 | regulator-always-on; | |
654 | anatop-reg-offset = <0x140>; | |
655 | anatop-vol-bit-shift = <18>; | |
656 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
657 | anatop-delay-reg-offset = <0x170>; |
658 | anatop-delay-bit-shift = <28>; | |
659 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
660 | anatop-min-bit-val = <1>; |
661 | anatop-min-voltage = <725000>; | |
662 | anatop-max-voltage = <1450000>; | |
663 | }; | |
7d740f87 SG |
664 | }; |
665 | ||
3fe6373b SG |
666 | tempmon: tempmon { |
667 | compatible = "fsl,imx6q-tempmon"; | |
275c08b5 | 668 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
3fe6373b SG |
669 | fsl,tempmon = <&anatop>; |
670 | fsl,tempmon-data = <&ocotp>; | |
8888f651 | 671 | clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
3fe6373b SG |
672 | }; |
673 | ||
74bd88f7 RZ |
674 | usbphy1: usbphy@020c9000 { |
675 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 | 676 | reg = <0x020c9000 0x1000>; |
275c08b5 | 677 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 678 | clocks = <&clks IMX6QDL_CLK_USBPHY1>; |
76a38855 | 679 | fsl,anatop = <&anatop>; |
7d740f87 SG |
680 | }; |
681 | ||
74bd88f7 RZ |
682 | usbphy2: usbphy@020ca000 { |
683 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 | 684 | reg = <0x020ca000 0x1000>; |
275c08b5 | 685 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 686 | clocks = <&clks IMX6QDL_CLK_USBPHY2>; |
76a38855 | 687 | fsl,anatop = <&anatop>; |
7d740f87 SG |
688 | }; |
689 | ||
690 | snvs@020cc000 { | |
c9250388 SG |
691 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
692 | #address-cells = <1>; | |
693 | #size-cells = <1>; | |
694 | ranges = <0 0x020cc000 0x4000>; | |
695 | ||
b1df649b | 696 | snvs_rtc: snvs-rtc-lp@34 { |
c9250388 SG |
697 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
698 | reg = <0x34 0x58>; | |
275c08b5 TK |
699 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
700 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
c9250388 | 701 | }; |
422b0676 RG |
702 | |
703 | snvs_poweroff: snvs-poweroff@38 { | |
704 | compatible = "fsl,sec-v4.0-poweroff"; | |
705 | reg = <0x38 0x4>; | |
706 | status = "disabled"; | |
707 | }; | |
7d740f87 SG |
708 | }; |
709 | ||
7b7d6727 | 710 | epit1: epit@020d0000 { /* EPIT1 */ |
7d740f87 | 711 | reg = <0x020d0000 0x4000>; |
275c08b5 | 712 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
713 | }; |
714 | ||
7b7d6727 | 715 | epit2: epit@020d4000 { /* EPIT2 */ |
7d740f87 | 716 | reg = <0x020d4000 0x4000>; |
275c08b5 | 717 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
718 | }; |
719 | ||
7b7d6727 | 720 | src: src@020d8000 { |
bd3d924d | 721 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
7d740f87 | 722 | reg = <0x020d8000 0x4000>; |
275c08b5 TK |
723 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
724 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
09ebf366 | 725 | #reset-cells = <1>; |
7d740f87 SG |
726 | }; |
727 | ||
7b7d6727 | 728 | gpc: gpc@020dc000 { |
7d740f87 SG |
729 | compatible = "fsl,imx6q-gpc"; |
730 | reg = <0x020dc000 0x4000>; | |
b923ff6a MZ |
731 | interrupt-controller; |
732 | #interrupt-cells = <3>; | |
275c08b5 TK |
733 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
734 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | |
b923ff6a | 735 | interrupt-parent = <&intc>; |
729c8881 PZ |
736 | pu-supply = <®_pu>; |
737 | clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, | |
738 | <&clks IMX6QDL_CLK_GPU3D_SHADER>, | |
739 | <&clks IMX6QDL_CLK_GPU2D_CORE>, | |
740 | <&clks IMX6QDL_CLK_GPU2D_AXI>, | |
741 | <&clks IMX6QDL_CLK_OPENVG_AXI>, | |
742 | <&clks IMX6QDL_CLK_VPU_AXI>; | |
743 | #power-domain-cells = <1>; | |
7d740f87 SG |
744 | }; |
745 | ||
df37e0c0 DA |
746 | gpr: iomuxc-gpr@020e0000 { |
747 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
748 | reg = <0x020e0000 0x38>; | |
749 | }; | |
750 | ||
c56009b2 SG |
751 | iomuxc: iomuxc@020e0000 { |
752 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | |
753 | reg = <0x020e0000 0x4000>; | |
c56009b2 SG |
754 | }; |
755 | ||
41c04342 ST |
756 | ldb: ldb@020e0008 { |
757 | #address-cells = <1>; | |
758 | #size-cells = <0>; | |
759 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | |
760 | gpr = <&gpr>; | |
761 | status = "disabled"; | |
762 | ||
763 | lvds-channel@0 { | |
4520e692 PZ |
764 | #address-cells = <1>; |
765 | #size-cells = <0>; | |
41c04342 | 766 | reg = <0>; |
41c04342 | 767 | status = "disabled"; |
4520e692 PZ |
768 | |
769 | port@0 { | |
770 | reg = <0>; | |
771 | ||
772 | lvds0_mux_0: endpoint { | |
773 | remote-endpoint = <&ipu1_di0_lvds0>; | |
774 | }; | |
775 | }; | |
776 | ||
777 | port@1 { | |
778 | reg = <1>; | |
779 | ||
780 | lvds0_mux_1: endpoint { | |
781 | remote-endpoint = <&ipu1_di1_lvds0>; | |
782 | }; | |
783 | }; | |
41c04342 ST |
784 | }; |
785 | ||
786 | lvds-channel@1 { | |
4520e692 PZ |
787 | #address-cells = <1>; |
788 | #size-cells = <0>; | |
41c04342 | 789 | reg = <1>; |
41c04342 | 790 | status = "disabled"; |
4520e692 PZ |
791 | |
792 | port@0 { | |
793 | reg = <0>; | |
794 | ||
795 | lvds1_mux_0: endpoint { | |
796 | remote-endpoint = <&ipu1_di0_lvds1>; | |
797 | }; | |
798 | }; | |
799 | ||
800 | port@1 { | |
801 | reg = <1>; | |
802 | ||
803 | lvds1_mux_1: endpoint { | |
804 | remote-endpoint = <&ipu1_di1_lvds1>; | |
805 | }; | |
806 | }; | |
41c04342 ST |
807 | }; |
808 | }; | |
809 | ||
7b7d6727 | 810 | dcic1: dcic@020e4000 { |
7d740f87 | 811 | reg = <0x020e4000 0x4000>; |
275c08b5 | 812 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
813 | }; |
814 | ||
7b7d6727 | 815 | dcic2: dcic@020e8000 { |
7d740f87 | 816 | reg = <0x020e8000 0x4000>; |
275c08b5 | 817 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
818 | }; |
819 | ||
7b7d6727 | 820 | sdma: sdma@020ec000 { |
7d740f87 SG |
821 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
822 | reg = <0x020ec000 0x4000>; | |
275c08b5 | 823 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
824 | clocks = <&clks IMX6QDL_CLK_SDMA>, |
825 | <&clks IMX6QDL_CLK_SDMA>; | |
0e87e043 | 826 | clock-names = "ipg", "ahb"; |
fb72bb21 | 827 | #dma-cells = <3>; |
d6b9c591 | 828 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
7d740f87 SG |
829 | }; |
830 | }; | |
831 | ||
832 | aips-bus@02100000 { /* AIPS2 */ | |
833 | compatible = "fsl,aips-bus", "simple-bus"; | |
834 | #address-cells = <1>; | |
835 | #size-cells = <1>; | |
836 | reg = <0x02100000 0x100000>; | |
837 | ranges; | |
838 | ||
839 | caam@02100000 { | |
840 | reg = <0x02100000 0x40000>; | |
275c08b5 TK |
841 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, |
842 | <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
843 | }; |
844 | ||
845 | aipstz@0217c000 { /* AIPSTZ2 */ | |
846 | reg = <0x0217c000 0x4000>; | |
847 | }; | |
848 | ||
7b7d6727 | 849 | usbotg: usb@02184000 { |
74bd88f7 RZ |
850 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
851 | reg = <0x02184000 0x200>; | |
275c08b5 | 852 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 853 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
74bd88f7 | 854 | fsl,usbphy = <&usbphy1>; |
28342c61 | 855 | fsl,usbmisc = <&usbmisc 0>; |
74bd88f7 RZ |
856 | status = "disabled"; |
857 | }; | |
858 | ||
7b7d6727 | 859 | usbh1: usb@02184200 { |
74bd88f7 RZ |
860 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
861 | reg = <0x02184200 0x200>; | |
275c08b5 | 862 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 863 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
74bd88f7 | 864 | fsl,usbphy = <&usbphy2>; |
28342c61 | 865 | fsl,usbmisc = <&usbmisc 1>; |
3ec481ed | 866 | dr_mode = "host"; |
74bd88f7 RZ |
867 | status = "disabled"; |
868 | }; | |
869 | ||
7b7d6727 | 870 | usbh2: usb@02184400 { |
74bd88f7 RZ |
871 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
872 | reg = <0x02184400 0x200>; | |
275c08b5 | 873 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 874 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 | 875 | fsl,usbmisc = <&usbmisc 2>; |
3ec481ed | 876 | dr_mode = "host"; |
74bd88f7 RZ |
877 | status = "disabled"; |
878 | }; | |
879 | ||
7b7d6727 | 880 | usbh3: usb@02184600 { |
74bd88f7 RZ |
881 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
882 | reg = <0x02184600 0x200>; | |
275c08b5 | 883 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 884 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 | 885 | fsl,usbmisc = <&usbmisc 3>; |
3ec481ed | 886 | dr_mode = "host"; |
74bd88f7 RZ |
887 | status = "disabled"; |
888 | }; | |
889 | ||
60984bdf | 890 | usbmisc: usbmisc@02184800 { |
28342c61 RZ |
891 | #index-cells = <1>; |
892 | compatible = "fsl,imx6q-usbmisc"; | |
893 | reg = <0x02184800 0x200>; | |
8888f651 | 894 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 RZ |
895 | }; |
896 | ||
7b7d6727 | 897 | fec: ethernet@02188000 { |
7d740f87 SG |
898 | compatible = "fsl,imx6q-fec"; |
899 | reg = <0x02188000 0x4000>; | |
454cf8f5 TK |
900 | interrupts-extended = |
901 | <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, | |
902 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
903 | clocks = <&clks IMX6QDL_CLK_ENET>, |
904 | <&clks IMX6QDL_CLK_ENET>, | |
905 | <&clks IMX6QDL_CLK_ENET_REF>; | |
7629838c | 906 | clock-names = "ipg", "ahb", "ptp"; |
7d740f87 SG |
907 | status = "disabled"; |
908 | }; | |
909 | ||
910 | mlb@0218c000 { | |
911 | reg = <0x0218c000 0x4000>; | |
275c08b5 TK |
912 | interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, |
913 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
914 | <0 126 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
915 | }; |
916 | ||
7b7d6727 | 917 | usdhc1: usdhc@02190000 { |
7d740f87 SG |
918 | compatible = "fsl,imx6q-usdhc"; |
919 | reg = <0x02190000 0x4000>; | |
275c08b5 | 920 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
921 | clocks = <&clks IMX6QDL_CLK_USDHC1>, |
922 | <&clks IMX6QDL_CLK_USDHC1>, | |
923 | <&clks IMX6QDL_CLK_USDHC1>; | |
0e87e043 | 924 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 925 | bus-width = <4>; |
7d740f87 SG |
926 | status = "disabled"; |
927 | }; | |
928 | ||
7b7d6727 | 929 | usdhc2: usdhc@02194000 { |
7d740f87 SG |
930 | compatible = "fsl,imx6q-usdhc"; |
931 | reg = <0x02194000 0x4000>; | |
275c08b5 | 932 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
933 | clocks = <&clks IMX6QDL_CLK_USDHC2>, |
934 | <&clks IMX6QDL_CLK_USDHC2>, | |
935 | <&clks IMX6QDL_CLK_USDHC2>; | |
0e87e043 | 936 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 937 | bus-width = <4>; |
7d740f87 SG |
938 | status = "disabled"; |
939 | }; | |
940 | ||
7b7d6727 | 941 | usdhc3: usdhc@02198000 { |
7d740f87 SG |
942 | compatible = "fsl,imx6q-usdhc"; |
943 | reg = <0x02198000 0x4000>; | |
275c08b5 | 944 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
945 | clocks = <&clks IMX6QDL_CLK_USDHC3>, |
946 | <&clks IMX6QDL_CLK_USDHC3>, | |
947 | <&clks IMX6QDL_CLK_USDHC3>; | |
0e87e043 | 948 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 949 | bus-width = <4>; |
7d740f87 SG |
950 | status = "disabled"; |
951 | }; | |
952 | ||
7b7d6727 | 953 | usdhc4: usdhc@0219c000 { |
7d740f87 SG |
954 | compatible = "fsl,imx6q-usdhc"; |
955 | reg = <0x0219c000 0x4000>; | |
275c08b5 | 956 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
957 | clocks = <&clks IMX6QDL_CLK_USDHC4>, |
958 | <&clks IMX6QDL_CLK_USDHC4>, | |
959 | <&clks IMX6QDL_CLK_USDHC4>; | |
0e87e043 | 960 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 961 | bus-width = <4>; |
7d740f87 SG |
962 | status = "disabled"; |
963 | }; | |
964 | ||
7b7d6727 | 965 | i2c1: i2c@021a0000 { |
7d740f87 SG |
966 | #address-cells = <1>; |
967 | #size-cells = <0>; | |
5bdfba29 | 968 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 969 | reg = <0x021a0000 0x4000>; |
275c08b5 | 970 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 971 | clocks = <&clks IMX6QDL_CLK_I2C1>; |
7d740f87 SG |
972 | status = "disabled"; |
973 | }; | |
974 | ||
7b7d6727 | 975 | i2c2: i2c@021a4000 { |
7d740f87 SG |
976 | #address-cells = <1>; |
977 | #size-cells = <0>; | |
5bdfba29 | 978 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 979 | reg = <0x021a4000 0x4000>; |
275c08b5 | 980 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 981 | clocks = <&clks IMX6QDL_CLK_I2C2>; |
7d740f87 SG |
982 | status = "disabled"; |
983 | }; | |
984 | ||
7b7d6727 | 985 | i2c3: i2c@021a8000 { |
7d740f87 SG |
986 | #address-cells = <1>; |
987 | #size-cells = <0>; | |
5bdfba29 | 988 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 989 | reg = <0x021a8000 0x4000>; |
275c08b5 | 990 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 991 | clocks = <&clks IMX6QDL_CLK_I2C3>; |
7d740f87 SG |
992 | status = "disabled"; |
993 | }; | |
994 | ||
995 | romcp@021ac000 { | |
996 | reg = <0x021ac000 0x4000>; | |
997 | }; | |
998 | ||
7b7d6727 | 999 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
7d740f87 SG |
1000 | compatible = "fsl,imx6q-mmdc"; |
1001 | reg = <0x021b0000 0x4000>; | |
1002 | }; | |
1003 | ||
7b7d6727 | 1004 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
7d740f87 SG |
1005 | reg = <0x021b4000 0x4000>; |
1006 | }; | |
1007 | ||
05e3f8e7 HS |
1008 | weim: weim@021b8000 { |
1009 | compatible = "fsl,imx6q-weim"; | |
7d740f87 | 1010 | reg = <0x021b8000 0x4000>; |
275c08b5 | 1011 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1012 | clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; |
7d740f87 SG |
1013 | }; |
1014 | ||
3fe6373b SG |
1015 | ocotp: ocotp@021bc000 { |
1016 | compatible = "fsl,imx6q-ocotp", "syscon"; | |
7d740f87 SG |
1017 | reg = <0x021bc000 0x4000>; |
1018 | }; | |
1019 | ||
7d740f87 SG |
1020 | tzasc@021d0000 { /* TZASC1 */ |
1021 | reg = <0x021d0000 0x4000>; | |
275c08b5 | 1022 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1023 | }; |
1024 | ||
1025 | tzasc@021d4000 { /* TZASC2 */ | |
1026 | reg = <0x021d4000 0x4000>; | |
275c08b5 | 1027 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1028 | }; |
1029 | ||
7b7d6727 | 1030 | audmux: audmux@021d8000 { |
f965cd55 | 1031 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
7d740f87 | 1032 | reg = <0x021d8000 0x4000>; |
f965cd55 | 1033 | status = "disabled"; |
7d740f87 SG |
1034 | }; |
1035 | ||
5e0c7cd4 | 1036 | mipi_csi: mipi@021dc000 { |
7d740f87 SG |
1037 | reg = <0x021dc000 0x4000>; |
1038 | }; | |
1039 | ||
4520e692 PZ |
1040 | mipi_dsi: mipi@021e0000 { |
1041 | #address-cells = <1>; | |
1042 | #size-cells = <0>; | |
7d740f87 | 1043 | reg = <0x021e0000 0x4000>; |
4520e692 PZ |
1044 | status = "disabled"; |
1045 | ||
70c2652c LY |
1046 | ports { |
1047 | #address-cells = <1>; | |
1048 | #size-cells = <0>; | |
1049 | ||
1050 | port@0 { | |
1051 | reg = <0>; | |
4520e692 | 1052 | |
70c2652c LY |
1053 | mipi_mux_0: endpoint { |
1054 | remote-endpoint = <&ipu1_di0_mipi>; | |
1055 | }; | |
4520e692 | 1056 | }; |
4520e692 | 1057 | |
70c2652c LY |
1058 | port@1 { |
1059 | reg = <1>; | |
4520e692 | 1060 | |
70c2652c LY |
1061 | mipi_mux_1: endpoint { |
1062 | remote-endpoint = <&ipu1_di1_mipi>; | |
1063 | }; | |
4520e692 PZ |
1064 | }; |
1065 | }; | |
7d740f87 SG |
1066 | }; |
1067 | ||
1068 | vdoa@021e4000 { | |
1069 | reg = <0x021e4000 0x4000>; | |
275c08b5 | 1070 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1071 | }; |
1072 | ||
0c456cfa | 1073 | uart2: serial@021e8000 { |
7d740f87 SG |
1074 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1075 | reg = <0x021e8000 0x4000>; | |
275c08b5 | 1076 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1077 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1078 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1079 | clock-names = "ipg", "per"; |
72a5cebf HS |
1080 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
1081 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1082 | status = "disabled"; |
1083 | }; | |
1084 | ||
0c456cfa | 1085 | uart3: serial@021ec000 { |
7d740f87 SG |
1086 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1087 | reg = <0x021ec000 0x4000>; | |
275c08b5 | 1088 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1089 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1090 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1091 | clock-names = "ipg", "per"; |
72a5cebf HS |
1092 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
1093 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1094 | status = "disabled"; |
1095 | }; | |
1096 | ||
0c456cfa | 1097 | uart4: serial@021f0000 { |
7d740f87 SG |
1098 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1099 | reg = <0x021f0000 0x4000>; | |
275c08b5 | 1100 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1101 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1102 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1103 | clock-names = "ipg", "per"; |
72a5cebf HS |
1104 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
1105 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1106 | status = "disabled"; |
1107 | }; | |
1108 | ||
0c456cfa | 1109 | uart5: serial@021f4000 { |
7d740f87 SG |
1110 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1111 | reg = <0x021f4000 0x4000>; | |
275c08b5 | 1112 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1113 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1114 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1115 | clock-names = "ipg", "per"; |
72a5cebf HS |
1116 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
1117 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1118 | status = "disabled"; |
1119 | }; | |
1120 | }; | |
91660d74 SH |
1121 | |
1122 | ipu1: ipu@02400000 { | |
4520e692 PZ |
1123 | #address-cells = <1>; |
1124 | #size-cells = <0>; | |
91660d74 SH |
1125 | compatible = "fsl,imx6q-ipu"; |
1126 | reg = <0x02400000 0x400000>; | |
275c08b5 TK |
1127 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, |
1128 | <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
1129 | clocks = <&clks IMX6QDL_CLK_IPU1>, |
1130 | <&clks IMX6QDL_CLK_IPU1_DI0>, | |
1131 | <&clks IMX6QDL_CLK_IPU1_DI1>; | |
91660d74 | 1132 | clock-names = "bus", "di0", "di1"; |
09ebf366 | 1133 | resets = <&src 2>; |
4520e692 | 1134 | |
c0470c38 PZ |
1135 | ipu1_csi0: port@0 { |
1136 | reg = <0>; | |
1137 | }; | |
1138 | ||
1139 | ipu1_csi1: port@1 { | |
1140 | reg = <1>; | |
1141 | }; | |
1142 | ||
4520e692 PZ |
1143 | ipu1_di0: port@2 { |
1144 | #address-cells = <1>; | |
1145 | #size-cells = <0>; | |
1146 | reg = <2>; | |
1147 | ||
1148 | ipu1_di0_disp0: endpoint@0 { | |
1149 | }; | |
1150 | ||
1151 | ipu1_di0_hdmi: endpoint@1 { | |
1152 | remote-endpoint = <&hdmi_mux_0>; | |
1153 | }; | |
1154 | ||
1155 | ipu1_di0_mipi: endpoint@2 { | |
1156 | remote-endpoint = <&mipi_mux_0>; | |
1157 | }; | |
1158 | ||
1159 | ipu1_di0_lvds0: endpoint@3 { | |
1160 | remote-endpoint = <&lvds0_mux_0>; | |
1161 | }; | |
1162 | ||
1163 | ipu1_di0_lvds1: endpoint@4 { | |
1164 | remote-endpoint = <&lvds1_mux_0>; | |
1165 | }; | |
1166 | }; | |
1167 | ||
1168 | ipu1_di1: port@3 { | |
1169 | #address-cells = <1>; | |
1170 | #size-cells = <0>; | |
1171 | reg = <3>; | |
1172 | ||
1173 | ipu1_di0_disp1: endpoint@0 { | |
1174 | }; | |
1175 | ||
1176 | ipu1_di1_hdmi: endpoint@1 { | |
1177 | remote-endpoint = <&hdmi_mux_1>; | |
1178 | }; | |
1179 | ||
1180 | ipu1_di1_mipi: endpoint@2 { | |
1181 | remote-endpoint = <&mipi_mux_1>; | |
1182 | }; | |
1183 | ||
1184 | ipu1_di1_lvds0: endpoint@3 { | |
1185 | remote-endpoint = <&lvds0_mux_1>; | |
1186 | }; | |
1187 | ||
1188 | ipu1_di1_lvds1: endpoint@4 { | |
1189 | remote-endpoint = <&lvds1_mux_1>; | |
1190 | }; | |
1191 | }; | |
91660d74 | 1192 | }; |
7d740f87 SG |
1193 | }; |
1194 | }; |