[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-wandboard.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_2p5v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
			regulator-always-on;
		};

		reg_3p3v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};

	sound {
		compatible = "fsl,imx6-wandboard-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx6-wandboard-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <3>;
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif>;
		spdif-out;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&hdmi {
	ddc-i2c-bus = <&i2c1>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	codec: sgtl5000@a {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mclk>;
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks IMX6QDL_CLK_CKO>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
		lrclk-strength = <3>;
	};
};

&iomuxc {
	pinctrl-names = "default";

	imx6qdl-wandboard {

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
			>;
		};

		pinctrl_mclk: mclkgrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
			>;
		};

		pinctrl_spdif: spdifgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
			>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
	fsl,err006687-workaround-present;
	status = "okay";
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "okay";
};

&ssi1 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	dr_mode = "peripheral";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
	status = "okay";
};
Commit	Line	Data
5dda6159	1	// SPDX-License-Identifier: GPL-2.0
2688a32f FE	2	/*
	3	* Copyright 2013 Freescale Semiconductor, Inc.
	4	*
	5	* Author: Fabio Estevam <fabio.estevam@freescale.com>
2688a32f FE	6	*/
2688a32f FE	7
89c1a8cf DA	8	#include <dt-bindings/gpio/gpio.h>
89c1a8cf DA	9
2688a32f FE	10	/ {
	11	regulators {
	12	compatible = "simple-bus";
56160e33 SG	13	#address-cells = <1>;
56160e33 SG	14	#size-cells = <0>;
2688a32f	15
56160e33	16	reg_2p5v: regulator@0 {
2688a32f	17	compatible = "regulator-fixed";
56160e33	18	reg = <0>;
2688a32f FE	19	regulator-name = "2P5V";
	20	regulator-min-microvolt = <2500000>;
	21	regulator-max-microvolt = <2500000>;
	22	regulator-always-on;
	23	};
	24
56160e33	25	reg_3p3v: regulator@1 {
2688a32f	26	compatible = "regulator-fixed";
56160e33	27	reg = <1>;
2688a32f FE	28	regulator-name = "3P3V";
	29	regulator-min-microvolt = <3300000>;
	30	regulator-max-microvolt = <3300000>;
	31	regulator-always-on;
	32	};
	33	};
	34
	35	sound {
	36	compatible = "fsl,imx6-wandboard-sgtl5000",
	37	"fsl,imx-audio-sgtl5000";
	38	model = "imx6-wandboard-sgtl5000";
	39	ssi-controller = <&ssi1>;
	40	audio-codec = <&codec>;
	41	audio-routing =
	42	"MIC_IN", "Mic Jack",
	43	"Mic Jack", "Mic Bias",
	44	"Headphone Jack", "HP_OUT";
	45	mux-int-port = <1>;
	46	mux-ext-port = <3>;
	47	};
c9d96df2 FE	48
	49	sound-spdif {
	50	compatible = "fsl,imx-audio-spdif";
	51	model = "imx-spdif";
	52	spdif-controller = <&spdif>;
	53	spdif-out;
	54	};
2688a32f FE	55	};
	56
	57	&audmux {
	58	pinctrl-names = "default";
817c27a1	59	pinctrl-0 = <&pinctrl_audmux>;
2688a32f FE	60	status = "okay";
	61	};
	62
fed687c5 FE	63	&hdmi {
	64	ddc-i2c-bus = <&i2c1>;
	65	status = "okay";
	66	};
	67
	68	&i2c1 {
	69	clock-frequency = <100000>;
	70	pinctrl-names = "default";
	71	pinctrl-0 = <&pinctrl_i2c1>;
	72	status = "okay";
	73	};
	74
2688a32f FE	75	&i2c2 {
	76	clock-frequency = <100000>;
	77	pinctrl-names = "default";
817c27a1	78	pinctrl-0 = <&pinctrl_i2c2>;
2688a32f FE	79	status = "okay";
2688a32f FE	80
8dccafaa	81	codec: sgtl5000@a {
6e1386b2 FE	82	pinctrl-names = "default";
6e1386b2 FE	83	pinctrl-0 = <&pinctrl_mclk>;
2688a32f FE	84	compatible = "fsl,sgtl5000";
2688a32f FE	85	reg = <0x0a>;
b26a68c1	86	clocks = <&clks IMX6QDL_CLK_CKO>;
2688a32f FE	87	VDDA-supply = <&reg_2p5v>;
2688a32f FE	88	VDDIO-supply = <&reg_3p3v>;
79935915	89	lrclk-strength = <3>;
2688a32f FE	90	};
	91	};
	92
	93	&iomuxc {
	94	pinctrl-names = "default";
2688a32f	95
817c27a1	96	imx6qdl-wandboard {
817c27a1 SG	97
	98	pinctrl_audmux: audmuxgrp {
	99	fsl,pins = <
77112dd5 NC	100	MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
	101	MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
	102	MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
	103	MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
817c27a1 SG	104	>;
	105	};
	106
	107	pinctrl_enet: enetgrp {
	108	fsl,pins = <
	109	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	110	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
c007b3a6 UKK	111	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	112	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	113	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	114	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	115	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	116	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
817c27a1	117	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
c007b3a6 UKK	118	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	119	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	120	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	121	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	122	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	123	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
817c27a1	124	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
9fc77821	125	MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
817c27a1 SG	126	>;
	127	};
	128
fed687c5 FE	129	pinctrl_i2c1: i2c1grp {
fed687c5 FE	130	fsl,pins = <
05c183e4 JT	131	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
05c183e4 JT	132	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
fed687c5 FE	133	>;
	134	};
	135
817c27a1 SG	136	pinctrl_i2c2: i2c2grp {
	137	fsl,pins = <
	138	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	139	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	140	>;
	141	};
	142
6e1386b2 FE	143	pinctrl_mclk: mclkgrp {
	144	fsl,pins = <
	145	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
	146	>;
	147	};
	148
817c27a1 SG	149	pinctrl_spdif: spdifgrp {
	150	fsl,pins = <
	151	MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
	152	>;
	153	};
	154
	155	pinctrl_uart1: uart1grp {
	156	fsl,pins = <
	157	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	158	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	159	>;
	160	};
	161
	162	pinctrl_uart3: uart3grp {
	163	fsl,pins = <
	164	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	165	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	166	MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
	167	MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
	168	>;
	169	};
	170
	171	pinctrl_usbotg: usbotggrp {
	172	fsl,pins = <
	173	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
	174	>;
	175	};
	176
	177	pinctrl_usdhc1: usdhc1grp {
	178	fsl,pins = <
	179	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
	180	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
	181	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
	182	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
	183	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
	184	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
	185	>;
	186	};
	187
	188	pinctrl_usdhc2: usdhc2grp {
	189	fsl,pins = <
	190	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
	191	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
	192	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
	193	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
	194	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
	195	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
	196	>;
	197	};
	198
	199	pinctrl_usdhc3: usdhc3grp {
	200	fsl,pins = <
	201	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	202	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	203	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	204	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	205	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	206	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	207	>;
	208	};
2688a32f FE	209	};
	210	};
	211
	212	&fec {
	213	pinctrl-names = "default";
817c27a1	214	pinctrl-0 = <&pinctrl_enet>;
2688a32f	215	phy-mode = "rgmii";
12de44f5	216	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
9fc77821 SS	217	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
9fc77821 SS	218	<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
a28eeb43	219	fsl,err006687-workaround-present;
2688a32f FE	220	status = "okay";
	221	};
	222
c9d96df2 FE	223	&spdif {
c9d96df2 FE	224	pinctrl-names = "default";
817c27a1	225	pinctrl-0 = <&pinctrl_spdif>;
c9d96df2 FE	226	status = "okay";
	227	};
	228
2688a32f	229	&ssi1 {
2688a32f FE	230	status = "okay";
	231	};
	232
	233	&uart1 {
	234	pinctrl-names = "default";
817c27a1	235	pinctrl-0 = <&pinctrl_uart1>;
2688a32f FE	236	status = "okay";
	237	};
	238
	239	&uart3 {
	240	pinctrl-names = "default";
817c27a1	241	pinctrl-0 = <&pinctrl_uart3>;
2e7c416c	242	uart-has-rtscts;
2688a32f FE	243	status = "okay";
	244	};
	245
	246	&usbh1 {
	247	status = "okay";
	248	};
	249
e9ac890a FE	250	&usbotg {
e9ac890a FE	251	pinctrl-names = "default";
817c27a1	252	pinctrl-0 = <&pinctrl_usbotg>;
e9ac890a FE	253	disable-over-current;
	254	dr_mode = "peripheral";
	255	status = "okay";
	256	};
	257
2688a32f FE	258	&usdhc1 {
2688a32f FE	259	pinctrl-names = "default";
817c27a1	260	pinctrl-0 = <&pinctrl_usdhc1>;
89c1a8cf	261	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
2688a32f FE	262	status = "okay";
	263	};
	264
2688a32f FE	265	&usdhc3 {
2688a32f FE	266	pinctrl-names = "default";
817c27a1	267	pinctrl-0 = <&pinctrl_usdhc3>;
89c1a8cf	268	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
2688a32f FE	269	status = "okay";
2688a32f FE	270	};