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ARM: dts: sun5i: Add backlight GPIO for reference design tablet
[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-ts7970.dtsi
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9ff8e9fc
SB		 1/*
2 * Copyright 2015 Technologic Systems
3 * Copyright 2017 Savoir-Faire Linux
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/gpio/gpio.h>
44#include <dt-bindings/interrupt-controller/irq.h>
45
46/ {
47 leds {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_leds1>;
50 compatible = "gpio-leds";
51
52 green-led {
53 label = "green-led";
54 gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
55 default-state = "on";
56 };
57
58 red-led {
59 label = "red-led";
60 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
61 default-state = "off";
62 };
63
64 yel-led {
65 label = "yellow-led";
66 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
67 default-state = "off";
68 };
69
70 blue-led {
71 label = "blue-led";
72 gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
73 default-state = "off";
74 };
75
76 en-usb-5v {
77 label = "en-usb-5v";
78 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
79 default-state = "on";
80 };
81
82 sel_dc_usb {
83 label = "sel_dc_usb";
84 gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
85 default-state = "off";
86 };
87
88 };
89
90 reg_3p3v: regulator-3p3v {
91 compatible = "regulator-fixed";
92 regulator-name = "3p3v";
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 regulator-always-on;
96 };
97
98 reg_can1_3v3: reg_can1_3v3 {
99 compatible = "regulator-fixed";
100 regulator-name = "reg_can1_3v3";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
104 enable-active-high;
105 };
106
107 reg_can2_3v3: en-reg_can2_3v3 {
108 compatible = "regulator-fixed";
109 regulator-name = "reg_can2_3v3";
110 regulator-min-microvolt = <3300000>;
111 regulator-max-microvolt = <3300000>;
112 gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
113 enable-active-high;
114 };
115
116 reg_usb_otg_vbus: regulator-usb-otg-vbus {
117 compatible = "regulator-fixed";
118 regulator-name = "usb_otg_vbus";
119 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>;
121 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
122 enable-active-high;
123 };
124
125 reg_wlan_vmmc: regulator_wlan_vmmc {
126 compatible = "regulator-fixed";
127 regulator-name = "wlan_vmmc";
128 regulator-min-microvolt = <1800000>;
129 regulator-max-microvolt = <1800000>;
130 gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>;
131 startup-delay-us = <70000>;
132 enable-active-high;
133 };
134
135 sound-sgtl5000 {
136 audio-codec = <&sgtl5000>;
137 audio-routing =
138 "MIC_IN", "Mic Jack",
139 "Mic Jack", "Mic Bias",
140 "Headphone Jack", "HP_OUT";
141 compatible = "fsl,imx-audio-sgtl5000";
142 model = "On-board Codec";
143 mux-ext-port = <3>;
144 mux-int-port = <1>;
145 ssi-controller = <&ssi1>;
146 };
147};
148
149&audmux {
150 status = "okay";
151};
152
153&can1 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_flexcan1>;
156 xceiver-supply = <&reg_can1_3v3>;
157 status = "okay";
158};
159
160&can2 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_flexcan2>;
163 xceiver-supply = <&reg_can2_3v3>;
164 status = "okay";
165};
166
167&ecspi1 {
168 cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_ecspi1>;
171 status = "okay";
172
173 n25q064: flash@0 {
174 compatible = "micron,n25q064", "jedec,spi-nor";
175 reg = <0>;
176 spi-max-frequency = <20000000>;
177 };
178};
179
180&ecspi2 {
181 cs-gpios = <
182 &gpio5 31 GPIO_ACTIVE_HIGH
183 &gpio7 12 GPIO_ACTIVE_HIGH
184 &gpio5 18 GPIO_ACTIVE_HIGH
185 >;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_ecspi2>;
188 status = "okay";
189};
190
191&fec {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_enet>;
194 phy-mode = "rgmii";
195 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
196 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
197 fsl,err006687-workaround-present;
198 status = "okay";
199};
200
201&hdmi {
202 status = "okay";
203};
204
205&i2c1 {
206 clock-frequency = <100000>;
207 pinctrl-names = "default", "gpio";
208 pinctrl-0 = <&pinctrl_i2c1>;
209 pinctrl-1 = <&pinctrl_i2c1_gpio>;
210 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
211 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
212 status = "okay";
213
214 m41t00s: rtc@68 {
215 compatible = "m41t00";
216 reg = <0x68>;
217 };
218
219 isl12022: rtc@6f {
220 compatible = "isl,isl12022";
221 reg = <0x6f>;
222 };
223
224 gpio8: gpio@28 {
225 compatible = "technologic,ts7970-gpio";
226 reg = <0x28>;
227 #gpio-cells = <2>;
228 gpio-controller;
229 ngpio = <32>;
230 };
231
232 sgtl5000: codec@a {
233 compatible = "fsl,sgtl5000";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_sgtl5000>;
236 reg = <0x0a>;
237 clocks = <&clks IMX6QDL_CLK_CKO>;
238 VDDA-supply = <&reg_3p3v>;
239 VDDIO-supply = <&reg_3p3v>;
240 };
241};
242
243&i2c2 {
244 clock-frequency = <100000>;
245 pinctrl-names = "default", "gpio";
246 pinctrl-0 = <&pinctrl_i2c2>;
247 pinctrl-1 = <&pinctrl_i2c2_gpio>;
248 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
249 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
250 status = "okay";
251};
252
253&iomuxc {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_hog>;
256
257 pinctrl_ecspi1: ecspi1grp {
258 fsl,pins = <
259 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
260 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
261 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
262 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard Flash CS */
263 >;
264 };
265
266 pinctrl_ecspi2: ecspi2 {
267 fsl,pins = <
268 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
269 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
270 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
271 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x100b1 /* FPGA_SPI_CS0 */
272 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x100b1 /* FPGA_SPI_CS1 */
273 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 /* HD1_SPI_CS */
274 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */
275 MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */
276 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */
277 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */
278 >;
279 };
280
281 pinctrl_enet: enet {
282 fsl,pins = <
283 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
284 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
285 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
286 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
287 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
288 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
289 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
290 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
291 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
292 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
293 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
294 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
295 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
296 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
297 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
298 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088
299 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */
300 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
301 >;
302 };
303
304 pinctrl_flexcan1: flexcan1grp {
305 fsl,pins = <
306 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088
307 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088
308 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */
309 >;
310 };
311
312 pinctrl_flexcan2: flexcan2grp {
313 fsl,pins = <
314 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088
315 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088
316 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */
317 >;
318 };
319
320 pinctrl_hog: hoggrp {
321 fsl,pins = <
322 /* Onboard */
323 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET */
324 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b088 /* SEL_DC_USB */
325 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */
326 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b088 /* JTAG_FPGA_TMS */
327 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b088 /* JTAG_FPGA_TCK */
328 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b088 /* JTAG_FPGA_TDO */
329 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b088 /* JTAG_FPGA_TDI */
330 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b088 /* GYRO_INT */
331 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* MODBUS_FAULT */
332 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */
333 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */
334 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */
335 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */
336 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */
337 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */
338
339 /* Offboard */
340 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */
341 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b088 /* HD1_IRQ */
342 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b088 /* LCD_D10 */
343 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b088 /* LCD_D11 */
344 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* BUS_BHE */
345 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */
346 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b088 /* BUS_CS */
347 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b088 /* DIO_20 */
348 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b088 /* BUS_WAIT */
349 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 /* MUX_AD_00 */
350 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b088 /* MUX_AD_01 */
351 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* MUX_AD_02 */
352 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b088 /* MUX_AD_03 */
353 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* MUX_AD_04 */
354 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* MUX_AD_05 */
355 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b088 /* MUX_AD_06 */
356 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b088 /* MUX_AD_07 */
357 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b088 /* MUX_AD_08 */
358 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* MUX_AD_09 */
359 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* MUX_AD_10 */
360 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* MUX_AD_11 */
361 MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* MUX_AD_12 */
362 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MUX_AD_13 */
363 MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MUX_AD_14 */
364 MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* MUX_AD_15 */
365
366 /* Strapping only */
367 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088
368 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088
369 >;
370 };
371
372 pinctrl_i2c1: i2c1grp {
373 fsl,pins = <
374 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
375 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
376 >;
377 };
378
379 pinctrl_i2c1_gpio: i2c1gpiogrp {
380 fsl,pins = <
381 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
382 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
383 >;
384 };
385
386 pinctrl_i2c2: i2c2grp {
387 fsl,pins = <
388 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
389 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
390 >;
391 };
392
393 pinctrl_i2c2_gpio: i2c2gpiogrp {
394 fsl,pins = <
395 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
396 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
397 >;
398 };
399
400 pinctrl_leds1: leds1grp {
401 fsl,pins = <
402 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */
403 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */
404 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b088 /* YEL_LED */
405 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 /* IMX6_BLUE_LED */
406 >;
407 };
408
409 pinctrl_sgtl5000: sgtl5000grp {
410 fsl,pins = <
411 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
412 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
413 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
414 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
415 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */
416 >;
417 };
418
419 pinctrl_uart1: uart1grp {
420 fsl,pins = <
421 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088
422 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088
423 >;
424 };
425
426 pinctrl_uart2: uart2grp {
427 fsl,pins = <
428 MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088
429 MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088
430 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088
431 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088
432 >;
433 };
434
435 pinctrl_uart3: uart3grp {
436 fsl,pins = <
437 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088
438 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088
439 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088
440 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088
441 >;
442 };
443
444 pinctrl_uart4: uart4grp {
445 fsl,pins = <
446 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088
447 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088
448 >;
449 };
450
451 pinctrl_uart5: uart5grp {
452 fsl,pins = <
453 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088
454 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088
455 >;
456 };
457
458 pinctrl_usbotg: usbotggrp {
459 fsl,pins = <
460 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
461 >;
462 };
463
464 pinctrl_usdhc1: usdhc1grp {
465 fsl,pins = <
466 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
467 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
468 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
469 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
470 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
471 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
472 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */
473 >;
474 };
475
476 pinctrl_usdhc2: usdhc2grp {
477 fsl,pins = <
478 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
479 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
480 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
481 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
482 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
483 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
484 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* EN_SD_POWER */
485 >;
486 };
487
488 pinctrl_usdhc3: usdhc3grp {
489 fsl,pins = <
490 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
491 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
492 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
493 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
494 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
495 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
496 >;
497 };
498};
499
500&pcie {
501 status = "okay";
502};
503
504&snvs_rtc {
505 status = "disabled";
506};
507
508&ssi1 {
509 fsl,mode = "i2s-slave";
510 status = "okay";
511};
512
513&uart1 {
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_uart1>;
516 status = "okay";
517};
518
519&uart2 {
520 pinctrl-names = "default";
521 pinctrl-0 = <&pinctrl_uart2>;
522 uart-has-rtscts;
523 status = "okay";
524};
525
526&uart3 {
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_uart3>;
529 status = "okay";
530};
531
532&uart4 {
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_uart4>;
535 status = "okay";
536};
537
538&uart5 {
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_uart5>;
541 status = "okay";
542};
543
544&usbh1 {
545 status = "okay";
546};
547
548&usbotg {
549 vbus-supply = <&reg_usb_otg_vbus>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_usbotg>;
552 disable-over-current;
553 status = "okay";
554};
555
556/* WIFI */
557&usdhc1 {
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_usdhc1>;
560 vmmc-supply = <&reg_wlan_vmmc>;
561 bus-width = <4>;
562 non-removable;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 status = "okay";
566
567 wlcore: wlcore@2 {
568 compatible = "ti,wl1271";
569 reg = <2>;
570 interrupt-parent = <&gpio1>;
571 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
572 ref-clock-frequency = <38400000>;
573 };
574};
575
576/* SD */
577&usdhc2 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_usdhc2>;
580 vmmc-supply = <&reg_3p3v>;
581 bus-width = <4>;
582 fsl,wp-controller;
583 status = "okay";
584};
585
586/* eMMC */
587&usdhc3 {
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_usdhc3>;
590 vmmc-supply = <&reg_3p3v>;
591 bus-width = <4>;
592 non-removable;
593 status = "okay";
594};
Linux 6.x block layer and io_uring tree(s)