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Merge tag 'amlogic-dt-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman...
[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-sabresd.dtsi
CommitLineData
1f31e253
FE		 1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
082d33d0 5
545fb52e 6#include <dt-bindings/clock/imx6qdl-clock.h>
22724cf1 7#include <dt-bindings/gpio/gpio.h>
8e4422ae
AH		 8#include <dt-bindings/input/input.h>
9
082d33d0 10/ {
48f51963
SH		 11 chosen {
12 stdout-path = &uart1;
13 };
14
ad00e080 15 memory@10000000 {
082d33d0
SG		 16 reg = <0x10000000 0x40000000>;
17 };
18
19 regulators {
20 compatible = "simple-bus";
56160e33
SG		 21 #address-cells = <1>;
22 #size-cells = <0>;
082d33d0 23
56160e33 24 reg_usb_otg_vbus: regulator@0 {
082d33d0 25 compatible = "regulator-fixed";
56160e33 26 reg = <0>;
082d33d0
SG		 27 regulator-name = "usb_otg_vbus";
28 regulator-min-microvolt = <5000000>;
29 regulator-max-microvolt = <5000000>;
30 gpio = <&gpio3 22 0>;
31 enable-active-high;
40f73779 32 vin-supply = <&swbst_reg>;
082d33d0 33 };
fdbfb43b 34
56160e33 35 reg_usb_h1_vbus: regulator@1 {
015fa46d 36 compatible = "regulator-fixed";
56160e33 37 reg = <1>;
015fa46d
PC		 38 regulator-name = "usb_h1_vbus";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 gpio = <&gpio1 29 0>;
42 enable-active-high;
40f73779 43 vin-supply = <&swbst_reg>;
015fa46d
PC		 44 };
45
56160e33 46 reg_audio: regulator@2 {
fdbfb43b 47 compatible = "regulator-fixed";
56160e33 48 reg = <2>;
fdbfb43b
NC		 49 regulator-name = "wm8962-supply";
50 gpio = <&gpio4 10 0>;
51 enable-active-high;
52 };
78827ec0
LS		 53
54 reg_pcie: regulator@3 {
55 compatible = "regulator-fixed";
56 reg = <3>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_pcie_reg>;
59 regulator-name = "MPCIE_3V3";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
62 gpio = <&gpio3 19 0>;
78827ec0
LS		 63 enable-active-high;
64 };
082d33d0
SG		 65 };
66
67 gpio-keys {
68 compatible = "gpio-keys";
8e4422ae
AH		 69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_gpio_keys>;
71
72 power {
73 label = "Power Button";
22724cf1 74 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
26cefdd1 75 wakeup-source;
8e4422ae
AH		 76 linux,code = <KEY_POWER>;
77 };
082d33d0
SG		 78
79 volume-up {
80 label = "Volume Up";
22724cf1 81 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
26cefdd1 82 wakeup-source;
8e4422ae 83 linux,code = <KEY_VOLUMEUP>;
082d33d0
SG		 84 };
85
86 volume-down {
87 label = "Volume Down";
22724cf1 88 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
26cefdd1 89 wakeup-source;
8e4422ae 90 linux,code = <KEY_VOLUMEDOWN>;
082d33d0
SG		 91 };
92 };
77b38fc3
NC		 93
94 sound {
95 compatible = "fsl,imx6q-sabresd-wm8962",
96 "fsl,imx-audio-wm8962";
97 model = "wm8962-audio";
98 ssi-controller = <&ssi2>;
99 audio-codec = <&codec>;
100 audio-routing =
101 "Headphone Jack", "HPOUTL",
102 "Headphone Jack", "HPOUTR",
103 "Ext Spk", "SPKOUTL",
104 "Ext Spk", "SPKOUTR",
76e68684
FE		 105 "AMIC", "MICBIAS",
106 "IN3R", "AMIC";
77b38fc3
NC		 107 mux-int-port = <2>;
108 mux-ext-port = <3>;
109 };
2f35c0c4 110
e0884948 111 backlight_lvds: backlight-lvds {
2f35c0c4
RP		 112 compatible = "pwm-backlight";
113 pwms = <&pwm1 0 5000000>;
114 brightness-levels = <0 4 8 16 32 64 128 255>;
115 default-brightness-level = <7>;
116 status = "okay";
117 };
702bfbef
VS		 118
119 leds {
120 compatible = "gpio-leds";
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_gpio_leds>;
123
124 red {
bf5393c5
JT		 125 gpios = <&gpio1 2 0>;
126 default-state = "on";
702bfbef
VS		 127 };
128 };
e0884948
FE		 129
130 panel {
131 compatible = "hannstar,hsd100pxn1";
132 backlight = <&backlight_lvds>;
133
134 port {
135 panel_in: endpoint {
136 remote-endpoint = <&lvds0_out>;
137 };
138 };
139 };
082d33d0
SG		 140};
141
545fb52e
SL		 142&ipu1_csi0_from_ipu1_csi0_mux {
143 bus-width = <8>;
144 data-shift = <12>; /* Lines 19:12 used */
145 hsync-active = <1>;
146 vsync-active = <1>;
147};
148
149&ipu1_csi0_mux_from_parallel_sensor {
150 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
151};
152
153&ipu1_csi0 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_ipu1_csi0>;
156};
157
158&mipi_csi {
159 status = "okay";
160
161 port@0 {
162 reg = <0>;
163
164 mipi_csi2_in: endpoint {
165 remote-endpoint = <&ov5640_to_mipi_csi2>;
166 clock-lanes = <0>;
167 data-lanes = <1 2>;
168 };
169 };
170};
171
48828700
NC		 172&audmux {
173 pinctrl-names = "default";
817c27a1 174 pinctrl-0 = <&pinctrl_audmux>;
48828700
NC		 175 status = "okay";
176};
177
d28be499
FE		 178&clks {
179 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
180 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
181 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
182 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
183};
184
9110ede4 185&ecspi1 {
9110ede4
HS		 186 cs-gpios = <&gpio4 9 0>;
187 pinctrl-names = "default";
817c27a1 188 pinctrl-0 = <&pinctrl_ecspi1>;
9110ede4
HS		 189 status = "okay";
190
191 flash: m25p80@0 {
192 #address-cells = <1>;
193 #size-cells = <1>;
79826ac6 194 compatible = "st,m25p32", "jedec,spi-nor";
9110ede4
HS		 195 spi-max-frequency = <20000000>;
196 reg = <0>;
197 };
198};
199
082d33d0
SG		 200&fec {
201 pinctrl-names = "default";
817c27a1 202 pinctrl-0 = <&pinctrl_enet>;
082d33d0 203 phy-mode = "rgmii";
12de44f5 204 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
082d33d0
SG		 205 status = "okay";
206};
207
ad704567 208&hdmi {
12ce81e9
FE		 209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_hdmi_cec>;
ad704567
FE		 211 ddc-i2c-bus = <&i2c2>;
212 status = "okay";
213};
214
20426feb
NC		 215&i2c1 {
216 clock-frequency = <100000>;
217 pinctrl-names = "default";
817c27a1 218 pinctrl-0 = <&pinctrl_i2c1>;
20426feb
NC		 219 status = "okay";
220
221 codec: wm8962@1a {
222 compatible = "wlf,wm8962";
223 reg = <0x1a>;
f029ce3b 224 clocks = <&clks IMX6QDL_CLK_CKO>;
20426feb
NC		 225 DCVDD-supply = <&reg_audio>;
226 DBVDD-supply = <&reg_audio>;
227 AVDD-supply = <&reg_audio>;
228 CPVDD-supply = <&reg_audio>;
229 MICVDD-supply = <&reg_audio>;
230 PLLVDD-supply = <&reg_audio>;
231 SPKVDD1-supply = <&reg_audio>;
232 SPKVDD2-supply = <&reg_audio>;
233 gpio-cfg = <
234 0x0000 /* 0:Default */
235 0x0000 /* 1:Default */
236 0x0013 /* 2:FN_DMICCLK */
237 0x0000 /* 3:Default */
238 0x8014 /* 4:FN_DMICCDAT */
239 0x0000 /* 5:Default */
240 >;
545fb52e
SL		 241 };
242
243 ov5642: camera@3c {
244 compatible = "ovti,ov5642";
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_ov5642>;
247 clocks = <&clks IMX6QDL_CLK_CKO>;
248 clock-names = "xclk";
249 reg = <0x3c>;
250 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
251 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
252 rev B board is VGEN5 */
253 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
254 powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
255 reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
256 status = "disabled";
257
258 port {
259 ov5642_to_ipu1_csi0_mux: endpoint {
260 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
261 bus-width = <8>;
262 hsync-active = <1>;
263 vsync-active = <1>;
264 };
265 };
266 };
20426feb
NC		 267};
268
4b444bb8
FE		 269&i2c2 {
270 clock-frequency = <100000>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_i2c2>;
273 status = "okay";
274
545fb52e
SL		 275 ov5640: camera@3c {
276 compatible = "ovti,ov5640";
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_ov5640>;
279 reg = <0x3c>;
280 clocks = <&clks IMX6QDL_CLK_CKO>;
281 clock-names = "xclk";
282 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
283 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
284 rev B board is VGEN5 */
285 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
286 powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
287 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
288
289 port {
545fb52e
SL		 290 ov5640_to_mipi_csi2: endpoint {
291 remote-endpoint = <&mipi_csi2_in>;
292 clock-lanes = <0>;
293 data-lanes = <1 2>;
294 };
295 };
296 };
297
8dccafaa 298 pmic: pfuze100@8 {
4b444bb8
FE		 299 compatible = "fsl,pfuze100";
300 reg = <0x08>;
301
302 regulators {
303 sw1a_reg: sw1ab {
304 regulator-min-microvolt = <300000>;
305 regulator-max-microvolt = <1875000>;
306 regulator-boot-on;
307 regulator-always-on;
308 regulator-ramp-delay = <6250>;
309 };
310
311 sw1c_reg: sw1c {
312 regulator-min-microvolt = <300000>;
313 regulator-max-microvolt = <1875000>;
314 regulator-boot-on;
315 regulator-always-on;
316 regulator-ramp-delay = <6250>;
317 };
318
319 sw2_reg: sw2 {
320 regulator-min-microvolt = <800000>;
321 regulator-max-microvolt = <3300000>;
322 regulator-boot-on;
323 regulator-always-on;
5d625375 324 regulator-ramp-delay = <6250>;
4b444bb8
FE		 325 };
326
327 sw3a_reg: sw3a {
328 regulator-min-microvolt = <400000>;
329 regulator-max-microvolt = <1975000>;
330 regulator-boot-on;
331 regulator-always-on;
332 };
333
334 sw3b_reg: sw3b {
335 regulator-min-microvolt = <400000>;
336 regulator-max-microvolt = <1975000>;
337 regulator-boot-on;
338 regulator-always-on;
339 };
340
341 sw4_reg: sw4 {
342 regulator-min-microvolt = <800000>;
343 regulator-max-microvolt = <3300000>;
344 };
345
346 swbst_reg: swbst {
347 regulator-min-microvolt = <5000000>;
348 regulator-max-microvolt = <5150000>;
349 };
350
351 snvs_reg: vsnvs {
352 regulator-min-microvolt = <1000000>;
353 regulator-max-microvolt = <3000000>;
354 regulator-boot-on;
355 regulator-always-on;
356 };
357
358 vref_reg: vrefddr {
359 regulator-boot-on;
360 regulator-always-on;
361 };
362
363 vgen1_reg: vgen1 {
364 regulator-min-microvolt = <800000>;
365 regulator-max-microvolt = <1550000>;
366 };
367
368 vgen2_reg: vgen2 {
369 regulator-min-microvolt = <800000>;
370 regulator-max-microvolt = <1550000>;
371 };
372
373 vgen3_reg: vgen3 {
374 regulator-min-microvolt = <1800000>;
375 regulator-max-microvolt = <3300000>;
376 };
377
378 vgen4_reg: vgen4 {
379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <3300000>;
381 regulator-always-on;
382 };
383
384 vgen5_reg: vgen5 {
385 regulator-min-microvolt = <1800000>;
386 regulator-max-microvolt = <3300000>;
387 regulator-always-on;
388 };
389
390 vgen6_reg: vgen6 {
391 regulator-min-microvolt = <1800000>;
392 regulator-max-microvolt = <3300000>;
393 regulator-always-on;
394 };
395 };
396 };
397};
398
38501179
FE		 399&i2c3 {
400 clock-frequency = <100000>;
401 pinctrl-names = "default";
817c27a1 402 pinctrl-0 = <&pinctrl_i2c3>;
38501179
FE		 403 status = "okay";
404
8dccafaa 405 egalax_ts@4 {
38501179
FE		 406 compatible = "eeti,egalax_ts";
407 reg = <0x04>;
408 interrupt-parent = <&gpio6>;
409 interrupts = <7 2>;
410 wakeup-gpios = <&gpio6 7 0>;
411 };
412};
413
c56009b2
SG		 414&iomuxc {
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_hog>;
417
817c27a1 418 imx6qdl-sabresd {
c56009b2
SG		 419 pinctrl_hog: hoggrp {
420 fsl,pins = <
9a060c1a
FE		 421 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
422 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
423 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
424 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
c56009b2 425 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
9a060c1a
FE		 426 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
427 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
428 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
429 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
c56009b2
SG		 430 >;
431 };
817c27a1
SG		 432
433 pinctrl_audmux: audmuxgrp {
434 fsl,pins = <
77112dd5
NC		 435 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
436 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
437 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
438 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
817c27a1
SG		 439 >;
440 };
441
442 pinctrl_ecspi1: ecspi1grp {
443 fsl,pins = <
444 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
445 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
446 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
f3c72380 447 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
817c27a1
SG		 448 >;
449 };
450
451 pinctrl_enet: enetgrp {
452 fsl,pins = <
453 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
454 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
c007b3a6
UKK		 455 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
456 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
457 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
458 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
459 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
460 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
817c27a1 461 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
c007b3a6
UKK		 462 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
463 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
464 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
465 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
466 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
467 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
817c27a1
SG		 468 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
469 >;
470 };
471
8e4422ae
AH		 472 pinctrl_gpio_keys: gpio_keysgrp {
473 fsl,pins = <
9a060c1a
FE		 474 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
475 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
476 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
8e4422ae
AH		 477 >;
478 };
479
12ce81e9
FE		 480 pinctrl_hdmi_cec: hdmicecgrp {
481 fsl,pins = <
482 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
483 >;
484 };
485
817c27a1
SG		 486 pinctrl_i2c1: i2c1grp {
487 fsl,pins = <
488 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
489 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
490 >;
491 };
492
4b444bb8
FE		 493 pinctrl_i2c2: i2c2grp {
494 fsl,pins = <
495 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
496 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
497 >;
498 };
499
817c27a1
SG		 500 pinctrl_i2c3: i2c3grp {
501 fsl,pins = <
502 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
503 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
504 >;
505 };
506
545fb52e
SL		 507 pinctrl_ipu1_csi0: ipu1csi0grp {
508 fsl,pins = <
509 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
510 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
511 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
512 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
513 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
514 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
515 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
516 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
517 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
518 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
519 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
520 >;
521 };
522
523 pinctrl_ov5640: ov5640grp {
524 fsl,pins = <
525 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
526 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
527 >;
528 };
529
530 pinctrl_ov5642: ov5642grp {
531 fsl,pins = <
532 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
533 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
534 >;
535 };
536
9d4ebb36
MV		 537 pinctrl_pcie: pciegrp {
538 fsl,pins = <
9a060c1a 539 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
9d4ebb36
MV		 540 >;
541 };
542
78827ec0
LS		 543 pinctrl_pcie_reg: pciereggrp {
544 fsl,pins = <
545 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
546 >;
547 };
548
817c27a1
SG		 549 pinctrl_pwm1: pwm1grp {
550 fsl,pins = <
551 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
552 >;
553 };
554
555 pinctrl_uart1: uart1grp {
556 fsl,pins = <
557 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
558 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
559 >;
560 };
561
562 pinctrl_usbotg: usbotggrp {
563 fsl,pins = <
564 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
565 >;
566 };
567
568 pinctrl_usdhc2: usdhc2grp {
569 fsl,pins = <
570 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
571 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
572 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
573 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
574 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
575 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
576 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
577 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
578 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
579 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
580 >;
581 };
582
583 pinctrl_usdhc3: usdhc3grp {
584 fsl,pins = <
585 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
586 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
587 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
588 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
589 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
590 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
591 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
592 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
593 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
594 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
595 >;
596 };
e02ab39a
FE		 597
598 pinctrl_usdhc4: usdhc4grp {
599 fsl,pins = <
600 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
601 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
602 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
603 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
604 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
605 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
606 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
607 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
608 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
609 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
610 >;
611 };
49607ff7
FE		 612
613 pinctrl_wdog: wdoggrp {
614 fsl,pins = <
615 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
616 >;
617 };
c56009b2 618 };
702bfbef
VS		 619
620 gpio_leds {
621 pinctrl_gpio_leds: gpioledsgrp {
622 fsl,pins = <
9a060c1a 623 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
702bfbef
VS		 624 >;
625 };
626 };
c56009b2
SG		 627};
628
b7fb7105
SG		 629&ldb {
630 status = "okay";
631
632 lvds-channel@1 {
633 fsl,data-mapping = "spwg";
634 fsl,data-width = <18>;
635 status = "okay";
636
e0884948
FE		 637 port@4 {
638 reg = <4>;
639
640 lvds0_out: endpoint {
641 remote-endpoint = <&panel_in>;
b7fb7105
SG		 642 };
643 };
644 };
645};
646
9d4ebb36
MV		 647&pcie {
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_pcie>;
f1472f82 650 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
46c7ec9f 651 vpcie-supply = <&reg_pcie>;
9d4ebb36
MV		 652 status = "okay";
653};
654
2f35c0c4
RP		 655&pwm1 {
656 pinctrl-names = "default";
817c27a1 657 pinctrl-0 = <&pinctrl_pwm1>;
2f35c0c4
RP		 658 status = "okay";
659};
660
c23568db
LC		 661&reg_arm {
662 vin-supply = <&sw1a_reg>;
663};
664
665&reg_pu {
666 vin-supply = <&sw1c_reg>;
667};
668
669&reg_soc {
670 vin-supply = <&sw1c_reg>;
671};
672
422b0676
RG		 673&snvs_poweroff {
674 status = "okay";
675};
676
48828700 677&ssi2 {
48828700
NC		 678 status = "okay";
679};
680
082d33d0
SG		 681&uart1 {
682 pinctrl-names = "default";
817c27a1 683 pinctrl-0 = <&pinctrl_uart1>;
082d33d0
SG		 684 status = "okay";
685};
686
687&usbh1 {
015fa46d 688 vbus-supply = <&reg_usb_h1_vbus>;
082d33d0
SG		 689 status = "okay";
690};
691
692&usbotg {
693 vbus-supply = <&reg_usb_otg_vbus>;
694 pinctrl-names = "default";
817c27a1 695 pinctrl-0 = <&pinctrl_usbotg>;
082d33d0
SG		 696 disable-over-current;
697 status = "okay";
698};
699
700&usdhc2 {
701 pinctrl-names = "default";
817c27a1 702 pinctrl-0 = <&pinctrl_usdhc2>;
e367817a 703 bus-width = <8>;
89c1a8cf
DA		 704 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
705 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
082d33d0
SG		 706 status = "okay";
707};
708
709&usdhc3 {
710 pinctrl-names = "default";
817c27a1 711 pinctrl-0 = <&pinctrl_usdhc3>;
e367817a 712 bus-width = <8>;
89c1a8cf
DA		 713 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
714 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
082d33d0
SG		 715 status = "okay";
716};
e02ab39a
FE		 717
718&usdhc4 {
719 pinctrl-names = "default";
720 pinctrl-0 = <&pinctrl_usdhc4>;
721 bus-width = <8>;
722 non-removable;
723 no-1-8-v;
724 status = "okay";
725};
49607ff7
FE		 726
727&wdog1 {
728 status = "disabled";
729};
730
731&wdog2 {
732 pinctrl-names = "default";
733 pinctrl-0 = <&pinctrl_wdog>;
734 fsl,ext-reset-output;
735 status = "okay";
736};
Linux 6.x block layer and io_uring tree(s)