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4fe69a93 PZ |
1 | /* |
2 | * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
26888190 PZ |
12 | #include <dt-bindings/gpio/gpio.h> |
13 | ||
4fe69a93 PZ |
14 | / { |
15 | model = "Phytec phyFLEX-i.MX6 Ouad"; | |
16 | compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; | |
17 | ||
18 | memory { | |
19 | reg = <0x10000000 0x80000000>; | |
20 | }; | |
21 | ||
22 | regulators { | |
23 | compatible = "simple-bus"; | |
24 | #address-cells = <1>; | |
25 | #size-cells = <0>; | |
26 | ||
27 | reg_usb_otg_vbus: regulator@0 { | |
28 | compatible = "regulator-fixed"; | |
29 | reg = <0>; | |
30 | regulator-name = "usb_otg_vbus"; | |
31 | regulator-min-microvolt = <5000000>; | |
32 | regulator-max-microvolt = <5000000>; | |
33 | gpio = <&gpio4 15 0>; | |
34 | }; | |
35 | ||
36 | reg_usb_h1_vbus: regulator@1 { | |
37 | compatible = "regulator-fixed"; | |
38 | reg = <1>; | |
39 | regulator-name = "usb_h1_vbus"; | |
40 | regulator-min-microvolt = <5000000>; | |
41 | regulator-max-microvolt = <5000000>; | |
42 | gpio = <&gpio1 0 0>; | |
43 | }; | |
44 | }; | |
94a1bbf8 PZ |
45 | |
46 | gpio_leds: leds { | |
47 | compatible = "gpio-leds"; | |
48 | ||
49 | green { | |
50 | label = "phyflex:green"; | |
51 | gpios = <&gpio1 30 0>; | |
52 | }; | |
53 | ||
54 | red { | |
55 | label = "phyflex:red"; | |
56 | gpios = <&gpio2 31 0>; | |
57 | }; | |
58 | }; | |
4fe69a93 PZ |
59 | }; |
60 | ||
8fa91c8e DL |
61 | &audmux { |
62 | pinctrl-names = "default"; | |
63 | pinctrl-0 = <&pinctrl_audmux>; | |
64 | status = "disabled"; | |
65 | }; | |
66 | ||
4fe69a93 PZ |
67 | &ecspi3 { |
68 | pinctrl-names = "default"; | |
69 | pinctrl-0 = <&pinctrl_ecspi3>; | |
70 | status = "okay"; | |
71 | fsl,spi-num-chipselects = <1>; | |
72 | cs-gpios = <&gpio4 24 0>; | |
73 | ||
74 | flash@0 { | |
75 | compatible = "m25p80"; | |
76 | spi-max-frequency = <20000000>; | |
77 | reg = <0>; | |
78 | }; | |
79 | }; | |
80 | ||
35008832 CH |
81 | &fec { |
82 | pinctrl-names = "default"; | |
83 | pinctrl-0 = <&pinctrl_enet>; | |
84 | phy-mode = "rgmii"; | |
85 | phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; | |
86 | phy-supply = <&vdd_eth_io_reg>; | |
87 | status = "disabled"; | |
88 | }; | |
89 | ||
90 | &gpmi { | |
91 | pinctrl-names = "default"; | |
92 | pinctrl-0 = <&pinctrl_gpmi_nand>; | |
93 | nand-on-flash-bbt; | |
0019d182 | 94 | status = "okay"; |
35008832 CH |
95 | }; |
96 | ||
4fe69a93 PZ |
97 | &i2c1 { |
98 | pinctrl-names = "default"; | |
99 | pinctrl-0 = <&pinctrl_i2c1>; | |
100 | status = "okay"; | |
101 | ||
102 | eeprom@50 { | |
103 | compatible = "atmel,24c32"; | |
104 | reg = <0x50>; | |
105 | }; | |
106 | ||
107 | pmic@58 { | |
bd597f47 | 108 | compatible = "dlg,da9063"; |
4fe69a93 | 109 | reg = <0x58>; |
c082fd42 CH |
110 | interrupt-parent = <&gpio2>; |
111 | interrupts = <9 0x8>; /* active-low GPIO2_9 */ | |
4fe69a93 PZ |
112 | |
113 | regulators { | |
114 | vddcore_reg: bcore1 { | |
115 | regulator-min-microvolt = <730000>; | |
116 | regulator-max-microvolt = <1380000>; | |
117 | regulator-always-on; | |
118 | }; | |
119 | ||
120 | vddsoc_reg: bcore2 { | |
121 | regulator-min-microvolt = <730000>; | |
122 | regulator-max-microvolt = <1380000>; | |
123 | regulator-always-on; | |
124 | }; | |
125 | ||
126 | vdd_ddr3_reg: bpro { | |
127 | regulator-min-microvolt = <1500000>; | |
128 | regulator-max-microvolt = <1500000>; | |
129 | regulator-always-on; | |
130 | }; | |
131 | ||
132 | vdd_3v3_reg: bperi { | |
133 | regulator-min-microvolt = <3300000>; | |
134 | regulator-max-microvolt = <3300000>; | |
135 | regulator-always-on; | |
136 | }; | |
137 | ||
138 | vdd_buckmem_reg: bmem { | |
139 | regulator-min-microvolt = <3300000>; | |
140 | regulator-max-microvolt = <3300000>; | |
141 | regulator-always-on; | |
142 | }; | |
143 | ||
144 | vdd_eth_reg: bio { | |
145 | regulator-min-microvolt = <1200000>; | |
146 | regulator-max-microvolt = <1200000>; | |
147 | regulator-always-on; | |
148 | }; | |
149 | ||
150 | vdd_eth_io_reg: ldo4 { | |
151 | regulator-min-microvolt = <2500000>; | |
152 | regulator-max-microvolt = <2500000>; | |
153 | regulator-always-on; | |
154 | }; | |
155 | ||
156 | vdd_mx6_snvs_reg: ldo5 { | |
157 | regulator-min-microvolt = <3000000>; | |
158 | regulator-max-microvolt = <3000000>; | |
159 | regulator-always-on; | |
160 | }; | |
161 | ||
162 | vdd_3v3_pmic_io_reg: ldo6 { | |
163 | regulator-min-microvolt = <3300000>; | |
164 | regulator-max-microvolt = <3300000>; | |
165 | regulator-always-on; | |
166 | }; | |
167 | ||
168 | vdd_sd0_reg: ldo9 { | |
169 | regulator-min-microvolt = <3300000>; | |
170 | regulator-max-microvolt = <3300000>; | |
171 | }; | |
172 | ||
173 | vdd_sd1_reg: ldo10 { | |
174 | regulator-min-microvolt = <3300000>; | |
175 | regulator-max-microvolt = <3300000>; | |
176 | }; | |
177 | ||
178 | vdd_mx6_high_reg: ldo11 { | |
179 | regulator-min-microvolt = <3000000>; | |
180 | regulator-max-microvolt = <3000000>; | |
181 | regulator-always-on; | |
182 | }; | |
183 | }; | |
184 | }; | |
185 | }; | |
186 | ||
d76fab80 DL |
187 | &i2c2 { |
188 | pinctrl-names = "default"; | |
189 | pinctrl-0 = <&pinctrl_i2c2>; | |
190 | clock-frequency = <100000>; | |
191 | }; | |
192 | ||
193 | &i2c3 { | |
194 | pinctrl-names = "default"; | |
195 | pinctrl-0 = <&pinctrl_i2c3>; | |
196 | clock-frequency = <100000>; | |
197 | }; | |
198 | ||
4fe69a93 PZ |
199 | &iomuxc { |
200 | pinctrl-names = "default"; | |
201 | pinctrl-0 = <&pinctrl_hog>; | |
202 | ||
203 | imx6q-phytec-pfla02 { | |
204 | pinctrl_hog: hoggrp { | |
205 | fsl,pins = < | |
206 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 | |
207 | MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ | |
c082fd42 | 208 | MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */ |
94a1bbf8 PZ |
209 | MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ |
210 | MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ | |
4fe69a93 PZ |
211 | >; |
212 | }; | |
213 | ||
214 | pinctrl_ecspi3: ecspi3grp { | |
215 | fsl,pins = < | |
216 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | |
217 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | |
218 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | |
219 | >; | |
220 | }; | |
221 | ||
222 | pinctrl_enet: enetgrp { | |
223 | fsl,pins = < | |
224 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | |
225 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | |
226 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
227 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
228 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
229 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
230 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
231 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
232 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
233 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
234 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
235 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
236 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
237 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
238 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
239 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | |
240 | >; | |
241 | }; | |
242 | ||
243 | pinctrl_gpmi_nand: gpminandgrp { | |
244 | fsl,pins = < | |
245 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | |
246 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | |
247 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | |
248 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | |
249 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | |
250 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | |
251 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | |
252 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | |
253 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | |
254 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | |
255 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | |
256 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | |
257 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | |
258 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | |
259 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | |
260 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | |
261 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | |
262 | >; | |
263 | }; | |
264 | ||
265 | pinctrl_i2c1: i2c1grp { | |
266 | fsl,pins = < | |
267 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | |
268 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | |
269 | >; | |
270 | }; | |
271 | ||
d76fab80 DL |
272 | pinctrl_i2c2: i2c2grp { |
273 | fsl,pins = < | |
274 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | |
275 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | |
276 | >; | |
277 | }; | |
278 | ||
279 | pinctrl_i2c3: i2c3grp { | |
280 | fsl,pins = < | |
281 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | |
282 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | |
283 | >; | |
284 | }; | |
285 | ||
14e2833d PZ |
286 | pinctrl_uart3: uart3grp { |
287 | fsl,pins = < | |
288 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | |
289 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | |
290 | MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 | |
291 | MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 | |
292 | >; | |
293 | }; | |
294 | ||
4fe69a93 PZ |
295 | pinctrl_uart4: uart4grp { |
296 | fsl,pins = < | |
297 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | |
298 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | |
299 | >; | |
300 | }; | |
301 | ||
302 | pinctrl_usbh1: usbh1grp { | |
303 | fsl,pins = < | |
304 | MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 | |
305 | >; | |
306 | }; | |
307 | ||
308 | pinctrl_usbotg: usbotggrp { | |
309 | fsl,pins = < | |
310 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | |
311 | MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 | |
312 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 | |
313 | >; | |
314 | }; | |
315 | ||
316 | pinctrl_usdhc2: usdhc2grp { | |
317 | fsl,pins = < | |
318 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | |
319 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | |
320 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | |
321 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | |
322 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | |
323 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | |
324 | >; | |
325 | }; | |
326 | ||
327 | pinctrl_usdhc3: usdhc3grp { | |
328 | fsl,pins = < | |
329 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
330 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
331 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
332 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
333 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
334 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
335 | >; | |
336 | }; | |
337 | ||
338 | pinctrl_usdhc3_cdwp: usdhc3cdwp { | |
339 | fsl,pins = < | |
340 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 | |
341 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 | |
342 | >; | |
343 | }; | |
8fa91c8e DL |
344 | |
345 | pinctrl_audmux: audmuxgrp { | |
346 | fsl,pins = < | |
347 | MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 | |
348 | MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 | |
349 | MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 | |
350 | MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 | |
351 | >; | |
352 | }; | |
4fe69a93 PZ |
353 | }; |
354 | }; | |
355 | ||
14e2833d PZ |
356 | &uart3 { |
357 | pinctrl-names = "default"; | |
358 | pinctrl-0 = <&pinctrl_uart3>; | |
359 | status = "disabled"; | |
360 | }; | |
361 | ||
4fe69a93 PZ |
362 | &uart4 { |
363 | pinctrl-names = "default"; | |
364 | pinctrl-0 = <&pinctrl_uart4>; | |
365 | status = "disabled"; | |
366 | }; | |
367 | ||
368 | &usbh1 { | |
369 | vbus-supply = <®_usb_h1_vbus>; | |
370 | pinctrl-names = "default"; | |
371 | pinctrl-0 = <&pinctrl_usbh1>; | |
372 | status = "disabled"; | |
373 | }; | |
374 | ||
375 | &usbotg { | |
376 | vbus-supply = <®_usb_otg_vbus>; | |
377 | pinctrl-names = "default"; | |
378 | pinctrl-0 = <&pinctrl_usbotg>; | |
379 | disable-over-current; | |
380 | status = "disabled"; | |
381 | }; | |
382 | ||
383 | &usdhc2 { | |
384 | pinctrl-names = "default"; | |
385 | pinctrl-0 = <&pinctrl_usdhc2>; | |
386 | cd-gpios = <&gpio1 4 0>; | |
387 | wp-gpios = <&gpio1 2 0>; | |
388 | status = "disabled"; | |
389 | }; | |
390 | ||
391 | &usdhc3 { | |
392 | pinctrl-names = "default"; | |
393 | pinctrl-0 = <&pinctrl_usdhc3 | |
394 | &pinctrl_usdhc3_cdwp>; | |
395 | cd-gpios = <&gpio1 27 0>; | |
396 | wp-gpios = <&gpio1 29 0>; | |
397 | status = "disabled"; | |
398 | }; |