[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-icore-rqs.dtsi

/*
 * Copyright (C) 2015 Amarula Solutions B.V.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>

/ {
	memory {
		reg = <0x10000000 0x80000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_2p5v: regulator-2p5v {
		compatible = "regulator-fixed";
		regulator-name = "2P5V";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_sd3_vmmc: regulator-sd3-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "P3V3_SD3_SWITCHED";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
		enable-active-high;
	};

	reg_sd4_vmmc: regulator-sd4-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "P3V3_SD4_SWITCHED";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_usb_h1_vbus: regulator-usb-h1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_h1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_otg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	usb_hub: usb-hub {
		compatible = "smsc,usb3503a";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbhub>;
		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
		clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
		clock-names = "refclk";
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,widgets =
			"Microphone", "Mic Jack",
			"Headphone", "Headphone Jack",
			"Line", "Line In Jack",
			"Speaker", "Line Out Jack",
			"Speaker", "Ext Spk";
		simple-audio-card,routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";

		simple-audio-card,cpu {
			sound-dai = <&ssi1>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
		};
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";

	audmux_ssi1 {
		fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
		fsl,port-config = <
			(IMX_AUDMUX_V2_PTCR_TFSDIR |
			IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
			IMX_AUDMUX_V2_PTCR_TCLKDIR |
			IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
			IMX_AUDMUX_V2_PTCR_SYN)
			IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
		>;
	};

	audmux_aud4 {
		fsl,audmux-port = <MX51_AUDMUX_PORT4>;
		fsl,port-config = <
			IMX_AUDMUX_V2_PTCR_SYN
			IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
		>;
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	xceiver-supply = <&reg_3p3v>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can2>;
	xceiver-supply = <&reg_3p3v>;
	status = "okay";
};

&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-handle = <&eth_phy>;
	phy-mode = "rgmii";
	status = "okay";

	mdio {
		eth_phy: ethernet-phy {
			rxc-skew-ps = <1140>;
			txc-skew-ps = <1140>;
			txen-skew-ps = <600>;
			rxdv-skew-ps = <240>;
			rxd0-skew-ps = <420>;
			rxd1-skew-ps = <600>;
			rxd2-skew-ps = <420>;
			rxd3-skew-ps = <240>;
			txd0-skew-ps = <60>;
			txd1-skew-ps = <60>;
			txd2-skew-ps = <60>;
			txd3-skew-ps = <240>;
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	sgtl5000: codec@a {
		#sound-dai-cells = <0>;
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks IMX6QDL_CLK_CKO>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
		VDDD-supply = <&reg_1p8v>;
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&ssi1 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbh1 {
	vbus-supply = <&reg_usb_h1_vbus>;
	disable-over-current;
	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	no-1-8-v;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	vmcc-supply = <&reg_sd3_vmmc>;
	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
	bus-witdh = <4>;
	no-1-8-v;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc4>;
	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
	vmcc-supply = <&reg_sd4_vmmc>;
	bus-witdh = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
};

&iomuxc {
	pinctrl_audmux: audmux {
		fsl,pins = <
			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
		>;
	};

	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
		>;
	};

	pinctrl_can1: can1grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
		>;
	};

	pinctrl_can2: can2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
			MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
			MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
			MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
		>;
	};

	pinctrl_pcie: pciegrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059	/* PCIe Reset */
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
		>;
	};

	pinctrl_usbhub: usbhubgrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_6__GPIO1_IO06  0x1f059	/* HUB USB Reset */
		>;
	};

	pinctrl_usbotg: usbotggrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
			MX6QDL_PAD_GPIO_1__GPIO1_IO01  0x1f059	/* CD */
			MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1f059	/* PWR */
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170B1
			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100B1
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170F9
			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100F9
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
		>;
	};

	pinctrl_usdhc4: usdhc4grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
		>;
	};

	pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170B1
			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100B1
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
		>;
	};

	pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170F9
			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100F9
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
		>;
	};
};
Commit	Line	Data
cc42603d MT	1	/*
	2	* Copyright (C) 2015 Amarula Solutions B.V.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
13283626	13	* This file is distributed in the hope that it will be useful,
cc42603d MT	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
13283626	18	* Or, alternatively,
cc42603d MT	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
13283626	23	* restriction, including without limitation the rights to use,
cc42603d MT	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
13283626	32	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
cc42603d MT	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
13283626	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
cc42603d MT	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
	40	*/
	41
	42	#include <dt-bindings/gpio/gpio.h>
	43	#include <dt-bindings/clock/imx6qdl-clock.h>
b5307edb	44	#include <dt-bindings/sound/fsl-imx-audmux.h>
cc42603d MT	45
	46	/ {
	47	memory {
	48	reg = <0x10000000 0x80000000>;
	49	};
	50
	51	reg_1p8v: regulator-1p8v {
	52	compatible = "regulator-fixed";
	53	regulator-name = "1P8V";
	54	regulator-min-microvolt = <1800000>;
	55	regulator-max-microvolt = <1800000>;
	56	regulator-boot-on;
	57	regulator-always-on;
	58	};
	59
	60	reg_2p5v: regulator-2p5v {
	61	compatible = "regulator-fixed";
	62	regulator-name = "2P5V";
	63	regulator-min-microvolt = <2500000>;
	64	regulator-max-microvolt = <2500000>;
	65	regulator-boot-on;
	66	regulator-always-on;
	67	};
	68
	69	reg_3p3v: regulator-3p3v {
	70	compatible = "regulator-fixed";
	71	regulator-name = "3P3V";
	72	regulator-min-microvolt = <3300000>;
	73	regulator-max-microvolt = <3300000>;
	74	regulator-boot-on;
	75	regulator-always-on;
	76	};
	77
	78	reg_sd3_vmmc: regulator-sd3-vmmc {
	79	compatible = "regulator-fixed";
	80	regulator-name = "P3V3_SD3_SWITCHED";
	81	regulator-min-microvolt = <3300000>;
	82	regulator-max-microvolt = <3300000>;
	83	gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
	84	enable-active-high;
	85	};
	86
	87	reg_sd4_vmmc: regulator-sd4-vmmc {
	88	compatible = "regulator-fixed";
	89	regulator-name = "P3V3_SD4_SWITCHED";
	90	regulator-min-microvolt = <3300000>;
	91	regulator-max-microvolt = <3300000>;
	92	regulator-boot-on;
	93	regulator-always-on;
	94	};
	95
	96	reg_usb_h1_vbus: regulator-usb-h1-vbus {
	97	compatible = "regulator-fixed";
	98	regulator-name = "usb_h1_vbus";
	99	regulator-min-microvolt = <5000000>;
	100	regulator-max-microvolt = <5000000>;
	101	regulator-boot-on;
	102	regulator-always-on;
	103	};
	104
	105	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	106	compatible = "regulator-fixed";
	107	regulator-name = "usb_otg_vbus";
	108	regulator-min-microvolt = <5000000>;
109	regulator-max-microvolt = <5000000>;
110	regulator-boot-on;
111	regulator-always-on;
112	};
113
114	usb_hub: usb-hub {
115	compatible = "smsc,usb3503a";
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_usbhub>;
118	reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
119	clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
120	clock-names = "refclk";
121	};
4f0c2c75 JT	122
4f0c2c75 JT	123	sound {
b5307edb JT	124	compatible = "simple-audio-card";
	125	simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000";
	126	simple-audio-card,format = "i2s";
	127	simple-audio-card,bitclock-master = <&dailink_master>;
	128	simple-audio-card,frame-master = <&dailink_master>;
	129	simple-audio-card,widgets =
	130	"Microphone", "Mic Jack",
	131	"Headphone", "Headphone Jack",
	132	"Line", "Line In Jack",
	133	"Speaker", "Line Out Jack",
	134	"Speaker", "Ext Spk";
	135	simple-audio-card,routing =
4f0c2c75 JT	136	"MIC_IN", "Mic Jack",
	137	"Mic Jack", "Mic Bias",
	138	"Headphone Jack", "HP_OUT";
cc42603d	139
b5307edb JT	140	simple-audio-card,cpu {
	141	sound-dai = <&ssi1>;
	142	};
	143
	144	dailink_master: simple-audio-card,codec {
	145	sound-dai = <&sgtl5000>;
	146	};
	147	};
cc42603d MT	148	};
	149
	150	&audmux {
	151	pinctrl-names = "default";
	152	pinctrl-0 = <&pinctrl_audmux>;
	153	status = "okay";
b5307edb JT	154
	155	audmux_ssi1 {
	156	fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
	157	fsl,port-config = <
	158	(IMX_AUDMUX_V2_PTCR_TFSDIR \|
	159	IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) \|
	160	IMX_AUDMUX_V2_PTCR_TCLKDIR \|
	161	IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) \|
	162	IMX_AUDMUX_V2_PTCR_SYN)
	163	IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
	164	>;
	165	};
	166
	167	audmux_aud4 {
	168	fsl,audmux-port = <MX51_AUDMUX_PORT4>;
	169	fsl,port-config = <
	170	IMX_AUDMUX_V2_PTCR_SYN
	171	IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
	172	>;
	173	};
	174	};
	175
0ec7a7d3 JT	176	&can1 {
	177	pinctrl-names = "default";
	178	pinctrl-0 = <&pinctrl_can1>;
	179	xceiver-supply = <&reg_3p3v>;
	180	status = "okay";
	181	};
	182
	183	&can2 {
	184	pinctrl-names = "default";
	185	pinctrl-0 = <&pinctrl_can2>;
	186	xceiver-supply = <&reg_3p3v>;
	187	status = "okay";
	188	};
	189
b5307edb JT	190	&clks {
	191	assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
	192	assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
cc42603d MT	193	};
	194
	195	&fec {
	196	pinctrl-names = "default";
	197	pinctrl-0 = <&pinctrl_enet>;
	198	phy-handle = <&eth_phy>;
	199	phy-mode = "rgmii";
	200	status = "okay";
	201
	202	mdio {
	203	eth_phy: ethernet-phy {
	204	rxc-skew-ps = <1140>;
	205	txc-skew-ps = <1140>;
	206	txen-skew-ps = <600>;
	207	rxdv-skew-ps = <240>;
	208	rxd0-skew-ps = <420>;
	209	rxd1-skew-ps = <600>;
	210	rxd2-skew-ps = <420>;
	211	rxd3-skew-ps = <240>;
	212	txd0-skew-ps = <60>;
	213	txd1-skew-ps = <60>;
	214	txd2-skew-ps = <60>;
	215	txd3-skew-ps = <240>;
	216	};
	217	};
	218	};
	219
	220	&i2c1 {
	221	clock-frequency = <100000>;
	222	pinctrl-names = "default";
	223	pinctrl-0 = <&pinctrl_i2c1>;
	224	status = "okay";
	225	};
	226
	227	&i2c2 {
	228	clock-frequency = <100000>;
	229	pinctrl-names = "default";
	230	pinctrl-0 = <&pinctrl_i2c2>;
	231	status = "okay";
	232	};
	233
	234	&i2c3 {
	235	pinctrl-names = "default";
	236	pinctrl-0 = <&pinctrl_i2c3>;
	237	status = "okay";
4f0c2c75 JT	238
4f0c2c75 JT	239	sgtl5000: codec@a {
b5307edb	240	#sound-dai-cells = <0>;
4f0c2c75 JT	241	compatible = "fsl,sgtl5000";
	242	reg = <0x0a>;
	243	clocks = <&clks IMX6QDL_CLK_CKO>;
	244	VDDA-supply = <&reg_2p5v>;
	245	VDDIO-supply = <&reg_3p3v>;
	246	VDDD-supply = <&reg_1p8v>;
	247	};
cc42603d MT	248	};
	249
	250	&pcie {
	251	pinctrl-names = "default";
	252	pinctrl-0 = <&pinctrl_pcie>;
	253	reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
	254	status = "okay";
	255	};
	256
	257	&ssi1 {
b5307edb	258	fsl,mode = "i2s-slave";
cc42603d MT	259	status = "okay";
	260	};
	261
	262	&uart4 {
	263	pinctrl-names = "default";
	264	pinctrl-0 = <&pinctrl_uart4>;
	265	status = "okay";
	266	};
	267
	268	&usbh1 {
	269	vbus-supply = <&reg_usb_h1_vbus>;
	270	disable-over-current;
	271	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	272	status = "okay";
	273	};
	274
	275	&usbotg {
	276	vbus-supply = <&reg_usb_otg_vbus>;
	277	pinctrl-names = "default";
	278	pinctrl-0 = <&pinctrl_usbotg>;
	279	disable-over-current;
	280	status = "okay";
	281	};
	282
	283	&usdhc1 {
	284	pinctrl-names = "default";
	285	pinctrl-0 = <&pinctrl_usdhc1>;
	286	no-1-8-v;
	287	status = "okay";
	288	};
	289
	290	&usdhc3 {
	291	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	292	pinctrl-0 = <&pinctrl_usdhc3>;
	293	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	294	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	295	vmcc-supply = <&reg_sd3_vmmc>;
	296	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
ca38f9cb	297	bus-witdh = <4>;
cc42603d MT	298	no-1-8-v;
	299	status = "okay";
	300	};
	301
	302	&usdhc4 {
	303	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	304	pinctrl-0 = <&pinctrl_usdhc4>;
	305	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
	306	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
	307	vmcc-supply = <&reg_sd4_vmmc>;
ca38f9cb	308	bus-witdh = <8>;
cc42603d MT	309	no-1-8-v;
	310	non-removable;
	311	status = "okay";
	312	};
	313
	314	&iomuxc {
	315	pinctrl_audmux: audmux {
	316	fsl,pins = <
	317	MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
	318	MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
	319	MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
	320	MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
	321	>;
	322	};
	323
	324	pinctrl_enet: enetgrp {
	325	fsl,pins = <
	326	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	327	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
c007b3a6 UKK	328	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	329	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	330	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	331	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	332	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	333	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
cc42603d	334	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
c007b3a6 UKK	335	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	336	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	337	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	338	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	339	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	340	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
cc42603d MT	341	MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
	342	>;
	343	};
	344
0ec7a7d3 JT	345	pinctrl_can1: can1grp {
	346	fsl,pins = <
	347	MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
	348	MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
	349	>;
	350	};
	351
	352	pinctrl_can2: can2grp {
	353	fsl,pins = <
	354	MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
	355	MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
	356	>;
	357	};
	358
cc42603d MT	359	pinctrl_i2c1: i2c1grp {
	360	fsl,pins = <
	361	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	362	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	363	>;
	364	};
	365
	366	pinctrl_i2c2: i2c2grp {
	367	fsl,pins = <
	368	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	369	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	370	>;
	371	};
	372
	373	pinctrl_i2c3: i2c3grp {
	374	fsl,pins = <
	375	MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
	376	MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
	377	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
	378	>;
	379	};
	380
	381	pinctrl_pcie: pciegrp {
	382	fsl,pins = <
	383	MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */
	384	>;
	385	};
	386
	387	pinctrl_uart4: uart4grp {
	388	fsl,pins = <
	389	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	390	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	391	>;
	392	};
	393
	394	pinctrl_usbhub: usbhubgrp {
	395	fsl,pins = <
	396	MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */
	397	>;
	398	};
	399
	400	pinctrl_usbotg: usbotggrp {
	401	fsl,pins = <
	402	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
	403	>;
	404	};
	405
	406	pinctrl_usdhc1: usdhc1grp {
	407	fsl,pins = <
	408	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
	409	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
	410	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
	411	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
	412	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
	413	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
	414	>;
	415	};
	416
	417	pinctrl_usdhc3: usdhc3grp {
	418	fsl,pins = <
	419	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
	420	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
	421	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
	422	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
423	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
424	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
425	MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */
426	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */
427	>;
428	};
429
430	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
431	fsl,pins = <
432	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1
433	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1
434	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
435	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
436	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
437	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
438	>;
439	};
440
441	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
442	fsl,pins = <
443	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
444	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
445	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
446	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
447	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
448	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
449	>;
450	};
451
452	pinctrl_usdhc4: usdhc4grp {
453	fsl,pins = <
454	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
455	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
456	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
457	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
458	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
459	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
460	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
461	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
462	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
463	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
464	>;
465	};
466
467	pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
468	fsl,pins = <
469	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1
470	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1
471	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
472	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
473	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
474	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
475	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
476	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
477	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
478	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
479	>;
480	};
481
482	pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
483	fsl,pins = <
484	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9
485	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9
486	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
487	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
488	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
489	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
490	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
491	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
492	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
493	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
494	>;
495	};
496	};