[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-gw54xx.dtsi

/*
 * Copyright 2013 Gateworks Corporation
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	/* these are used by bootloader for disabling nodes */
	aliases {
		led0 = &led0;
		led1 = &led1;
		led2 = &led2;
		nand = &gpmi;
		ssi0 = &ssi1;
		usb0 = &usbh1;
		usb1 = &usbotg;
	};

	chosen {
		bootargs = "console=ttymxc1,115200";
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm4 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <7>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led0: user1 {
			label = "user1";
			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		led1: user2 {
			label = "user2";
			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
			default-state = "off";
		};

		led2: user3 {
			label = "user3";
			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
			default-state = "off";
		};
	};

	memory {
		reg = <0x10000000 0x40000000>;
	};

	pps {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;
		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_1p0v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "1P0V";
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1000000>;
			regulator-always-on;
		};

		reg_3p3v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		reg_usb_h1_vbus: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "usb_h1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			regulator-always-on;
		};

		reg_usb_otg_vbus: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "usb_otg_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};

	sound {
		compatible = "fsl,imx6q-ventana-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "sgtl5000-audio";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <4>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
	status = "okay";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
};

&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};

&ecspi2 {
	cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
};

&hdmi {
	ddc-i2c-bus = <&i2c3>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	eeprom1: eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom2: eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom3: eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom4: eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	gpio: pca9555@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	rtc: ds1672@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic: pfuze100@8 {
		compatible = "fsl,pfuze100";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3950000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3a {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3b_reg: sw3b {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks IMX6QDL_CLK_CKO>;
		VDDA-supply = <&sw4_reg>;
		VDDIO-supply = <&reg_3p3v>;
	};

	touchscreen: egalax_ts@4 {
		compatible = "eeti,egalax_ts";
		reg = <0x04>;
		interrupt-parent = <&gpio7>;
		interrupts = <12 2>;
		wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
	};
};

&ldb {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		status = "okay";

		display-timings {
			native-mode = <&timing0>;
			timing0: hsd100pxn1 {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
	status = "disabled";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
	status = "disabled";
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
	status = "disabled";
};

&pwm4 {
	pinctrl-names = "default", "state_dio";
	pinctrl-0 = <&pinctrl_pwm4_backlight>;
	pinctrl-1 = <&pinctrl_pwm4_dio>;
	status = "okay";
};

&ssi1 {
	status = "okay";
};

&ssi2 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
};

&usbh1 {
	vbus-supply = <&reg_usb_h1_vbus>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	no-1-8-v; /* firmware will remove if board revision supports */
	status = "okay";
};

&wdog1 {
	status = "disabled";
};

&wdog2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_audmux: audmuxgrp {
		fsl,pins = <
			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
			MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
			MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0 /* AUD4_MCK */
		>;
	};

	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
		>;
	};

	pinctrl_ecspi2: escpi2grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x100b1
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x4001b0b0 /* CAN_STBY */
		>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
		>;
	};

	pinctrl_pcie: pciegrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0 /* PCIE IRQ */
			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0 /* PCIE RST */
		>;
	};

	pinctrl_pps: ppsgrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
		>;
	};

	pinctrl_pwm4_backlight: pwm4grpbacklight {
		fsl,pins = <
			/* LVDS_PWM J6.5 */
			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
		>;
	};

	pinctrl_pwm4_dio: pwm4grpdio {
		fsl,pins = <
			/* DIO3 J16.4 */
			MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x4001b0b1 /* TEN */
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
		>;
	};

	pinctrl_usbotg: usbotggrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* PWR_EN */
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX6QDL_PAD_SD1_DAT3__WDOG2_B		0x1b0b0
		>;
	};
};
Commit	Line	Data
e3946fe8 TH	1	/*
	2	* Copyright 2013 Gateworks Corporation
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
326cdb16 TH	12	#include <dt-bindings/gpio/gpio.h>
326cdb16 TH	13
e3946fe8 TH	14	/ {
	15	/* these are used by bootloader for disabling nodes */
	16	aliases {
e3946fe8 TH	17	led0 = &led0;
	18	led1 = &led1;
	19	led2 = &led2;
	20	nand = &gpmi;
e3946fe8 TH	21	ssi0 = &ssi1;
	22	usb0 = &usbh1;
	23	usb1 = &usbotg;
e3946fe8 TH	24	};
	25
	26	chosen {
	27	bootargs = "console=ttymxc1,115200";
	28	};
	29
b3253241 TH	30	backlight {
	31	compatible = "pwm-backlight";
	32	pwms = <&pwm4 0 5000000>;
	33	brightness-levels = <0 4 8 16 32 64 128 255>;
	34	default-brightness-level = <7>;
	35	};
	36
e3946fe8 TH	37	leds {
e3946fe8 TH	38	compatible = "gpio-leds";
b5f37b76 TH	39	pinctrl-names = "default";
b5f37b76 TH	40	pinctrl-0 = <&pinctrl_gpio_leds>;
e3946fe8 TH	41
	42	led0: user1 {
	43	label = "user1";
326cdb16	44	gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
e3946fe8 TH	45	default-state = "on";
	46	linux,default-trigger = "heartbeat";
	47	};
	48
	49	led1: user2 {
	50	label = "user2";
326cdb16	51	gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
e3946fe8 TH	52	default-state = "off";
	53	};
	54
	55	led2: user3 {
	56	label = "user3";
326cdb16	57	gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
e3946fe8 TH	58	default-state = "off";
	59	};
	60	};
	61
	62	memory {
	63	reg = <0x10000000 0x40000000>;
	64	};
	65
	66	pps {
	67	compatible = "pps-gpio";
b5f37b76 TH	68	pinctrl-names = "default";
b5f37b76 TH	69	pinctrl-0 = <&pinctrl_pps>;
326cdb16	70	gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
e3946fe8 TH	71	status = "okay";
	72	};
	73
	74	regulators {
	75	compatible = "simple-bus";
	76	#address-cells = <1>;
	77	#size-cells = <0>;
	78
	79	reg_1p0v: regulator@0 {
	80	compatible = "regulator-fixed";
	81	reg = <0>;
	82	regulator-name = "1P0V";
	83	regulator-min-microvolt = <1000000>;
	84	regulator-max-microvolt = <1000000>;
	85	regulator-always-on;
	86	};
	87
	88	reg_3p3v: regulator@1 {
	89	compatible = "regulator-fixed";
	90	reg = <1>;
	91	regulator-name = "3P3V";
	92	regulator-min-microvolt = <3300000>;
	93	regulator-max-microvolt = <3300000>;
	94	regulator-always-on;
	95	};
	96
	97	reg_usb_h1_vbus: regulator@2 {
	98	compatible = "regulator-fixed";
	99	reg = <2>;
	100	regulator-name = "usb_h1_vbus";
	101	regulator-min-microvolt = <5000000>;
	102	regulator-max-microvolt = <5000000>;
	103	regulator-always-on;
	104	};
	105
	106	reg_usb_otg_vbus: regulator@3 {
	107	compatible = "regulator-fixed";
	108	reg = <3>;
	109	regulator-name = "usb_otg_vbus";
	110	regulator-min-microvolt = <5000000>;
	111	regulator-max-microvolt = <5000000>;
326cdb16	112	gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
e3946fe8 TH	113	enable-active-high;
	114	};
	115	};
	116
	117	sound {
b12d1e94	118	compatible = "fsl,imx6q-ventana-sgtl5000",
e3946fe8	119	"fsl,imx-audio-sgtl5000";
b12d1e94	120	model = "sgtl5000-audio";
e3946fe8 TH	121	ssi-controller = <&ssi1>;
	122	audio-codec = <&codec>;
	123	audio-routing =
	124	"MIC_IN", "Mic Jack",
	125	"Mic Jack", "Mic Bias",
	126	"Headphone Jack", "HP_OUT";
	127	mux-int-port = <1>;
	128	mux-ext-port = <4>;
	129	};
	130	};
	131
	132	&audmux {
	133	pinctrl-names = "default";
	134	pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
	135	status = "okay";
	136	};
	137
	138	&can1 {
	139	pinctrl-names = "default";
	140	pinctrl-0 = <&pinctrl_flexcan1>;
	141	status = "okay";
	142	};
	143
e726a9fd TH	144	&clks {
e726a9fd TH	145	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
bf5393c5	146	<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
e726a9fd	147	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
bf5393c5	148	<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
e726a9fd TH	149	};
e726a9fd TH	150
b0a5c46d	151	&ecspi2 {
b0a5c46d TH	152	cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	153	pinctrl-names = "default";
	154	pinctrl-0 = <&pinctrl_ecspi2>;
	155	status = "okay";
	156	};
	157
e3946fe8 TH	158	&fec {
	159	pinctrl-names = "default";
	160	pinctrl-0 = <&pinctrl_enet>;
3a35e470	161	phy-mode = "rgmii-id";
326cdb16	162	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
e3946fe8 TH	163	status = "okay";
	164	};
	165
	166	&gpmi {
	167	pinctrl-names = "default";
	168	pinctrl-0 = <&pinctrl_gpmi_nand>;
	169	status = "okay";
	170	};
	171
aef15dba TH	172	&hdmi {
	173	ddc-i2c-bus = <&i2c3>;
	174	status = "okay";
	175	};
	176
e3946fe8 TH	177	&i2c1 {
	178	clock-frequency = <100000>;
	179	pinctrl-names = "default";
	180	pinctrl-0 = <&pinctrl_i2c1>;
	181	status = "okay";
	182
	183	eeprom1: eeprom@50 {
	184	compatible = "atmel,24c02";
	185	reg = <0x50>;
	186	pagesize = <16>;
	187	};
	188
	189	eeprom2: eeprom@51 {
	190	compatible = "atmel,24c02";
	191	reg = <0x51>;
	192	pagesize = <16>;
	193	};
	194
	195	eeprom3: eeprom@52 {
	196	compatible = "atmel,24c02";
	197	reg = <0x52>;
	198	pagesize = <16>;
	199	};
	200
	201	eeprom4: eeprom@53 {
	202	compatible = "atmel,24c02";
	203	reg = <0x53>;
	204	pagesize = <16>;
	205	};
	206
	207	gpio: pca9555@23 {
	208	compatible = "nxp,pca9555";
	209	reg = <0x23>;
	210	gpio-controller;
	211	#gpio-cells = <2>;
	212	};
	213
e3946fe8 TH	214	rtc: ds1672@68 {
	215	compatible = "dallas,ds1672";
	216	reg = <0x68>;
	217	};
	218	};
	219
	220	&i2c2 {
	221	clock-frequency = <100000>;
	222	pinctrl-names = "default";
	223	pinctrl-0 = <&pinctrl_i2c2>;
	224	status = "okay";
	225
8dccafaa	226	pmic: pfuze100@8 {
e3946fe8 TH	227	compatible = "fsl,pfuze100";
	228	reg = <0x08>;
	229
	230	regulators {
	231	sw1a_reg: sw1ab {
	232	regulator-min-microvolt = <300000>;
	233	regulator-max-microvolt = <1875000>;
	234	regulator-boot-on;
	235	regulator-always-on;
	236	regulator-ramp-delay = <6250>;
	237	};
	238
	239	sw1c_reg: sw1c {
	240	regulator-min-microvolt = <300000>;
	241	regulator-max-microvolt = <1875000>;
	242	regulator-boot-on;
	243	regulator-always-on;
	244	regulator-ramp-delay = <6250>;
	245	};
	246
	247	sw2_reg: sw2 {
	248	regulator-min-microvolt = <800000>;
	249	regulator-max-microvolt = <3950000>;
	250	regulator-boot-on;
	251	regulator-always-on;
	252	};
	253
	254	sw3a_reg: sw3a {
	255	regulator-min-microvolt = <400000>;
	256	regulator-max-microvolt = <1975000>;
	257	regulator-boot-on;
	258	regulator-always-on;
	259	};
	260
	261	sw3b_reg: sw3b {
	262	regulator-min-microvolt = <400000>;
	263	regulator-max-microvolt = <1975000>;
	264	regulator-boot-on;
	265	regulator-always-on;
	266	};
	267
	268	sw4_reg: sw4 {
	269	regulator-min-microvolt = <800000>;
	270	regulator-max-microvolt = <3300000>;
	271	};
	272
	273	swbst_reg: swbst {
	274	regulator-min-microvolt = <5000000>;
	275	regulator-max-microvolt = <5150000>;
70b6b438 TH	276	regulator-boot-on;
70b6b438 TH	277	regulator-always-on;
e3946fe8 TH	278	};
	279
	280	snvs_reg: vsnvs {
	281	regulator-min-microvolt = <1000000>;
	282	regulator-max-microvolt = <3000000>;
	283	regulator-boot-on;
	284	regulator-always-on;
	285	};
	286
	287	vref_reg: vrefddr {
	288	regulator-boot-on;
	289	regulator-always-on;
	290	};
	291
	292	vgen1_reg: vgen1 {
	293	regulator-min-microvolt = <800000>;
	294	regulator-max-microvolt = <1550000>;
	295	};
	296
	297	vgen2_reg: vgen2 {
	298	regulator-min-microvolt = <800000>;
	299	regulator-max-microvolt = <1550000>;
	300	};
	301
	302	vgen3_reg: vgen3 {
	303	regulator-min-microvolt = <1800000>;
	304	regulator-max-microvolt = <3300000>;
	305	};
	306
	307	vgen4_reg: vgen4 {
	308	regulator-min-microvolt = <1800000>;
	309	regulator-max-microvolt = <3300000>;
	310	regulator-always-on;
	311	};
	312
	313	vgen5_reg: vgen5 {
	314	regulator-min-microvolt = <1800000>;
	315	regulator-max-microvolt = <3300000>;
	316	regulator-always-on;
	317	};
	318
	319	vgen6_reg: vgen6 {
	320	regulator-min-microvolt = <1800000>;
	321	regulator-max-microvolt = <3300000>;
	322	regulator-always-on;
	323	};
	324	};
	325	};
e3946fe8 TH	326	};
	327
	328	&i2c3 {
	329	clock-frequency = <100000>;
	330	pinctrl-names = "default";
	331	pinctrl-0 = <&pinctrl_i2c3>;
	332	status = "okay";
	333
8dccafaa	334	codec: sgtl5000@a {
e3946fe8 TH	335	compatible = "fsl,sgtl5000";
e3946fe8 TH	336	reg = <0x0a>;
b26a68c1	337	clocks = <&clks IMX6QDL_CLK_CKO>;
e3946fe8 TH	338	VDDA-supply = <&sw4_reg>;
	339	VDDIO-supply = <&reg_3p3v>;
	340	};
	341
8dccafaa	342	touchscreen: egalax_ts@4 {
e3946fe8 TH	343	compatible = "eeti,egalax_ts";
	344	reg = <0x04>;
	345	interrupt-parent = <&gpio7>;
326cdb16 TH	346	interrupts = <12 2>;
326cdb16 TH	347	wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
e3946fe8	348	};
e3946fe8 TH	349	};
e3946fe8 TH	350
b5f37b76 TH	351	&ldb {
b5f37b76 TH	352	status = "okay";
e3946fe8	353
a7668fda	354	lvds-channel@0 {
b5f37b76 TH	355	fsl,data-mapping = "spwg";
	356	fsl,data-width = <18>;
	357	status = "okay";
	358
	359	display-timings {
	360	native-mode = <&timing0>;
	361	timing0: hsd100pxn1 {
	362	clock-frequency = <65000000>;
	363	hactive = <1024>;
	364	vactive = <768>;
	365	hback-porch = <220>;
	366	hfront-porch = <40>;
	367	vback-porch = <21>;
	368	vfront-porch = <7>;
	369	hsync-len = <60>;
	370	vsync-len = <10>;
	371	};
e3946fe8	372	};
b5f37b76 TH	373	};
	374	};
	375
	376	&pcie {
	377	pinctrl-names = "default";
	378	pinctrl-0 = <&pinctrl_pcie>;
	379	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
	380	status = "okay";
b5f37b76	381	};
e3946fe8	382
aa2b2178 TH	383	&pwm1 {
	384	pinctrl-names = "default";
	385	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
	386	status = "disabled";
	387	};
	388
	389	&pwm2 {
	390	pinctrl-names = "default";
	391	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
	392	status = "disabled";
	393	};
	394
	395	&pwm3 {
	396	pinctrl-names = "default";
	397	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
	398	status = "disabled";
	399	};
	400
b5f37b76	401	&pwm4 {
f8ea256e TH	402	pinctrl-names = "default", "state_dio";
	403	pinctrl-0 = <&pinctrl_pwm4_backlight>;
	404	pinctrl-1 = <&pinctrl_pwm4_dio>;
b5f37b76 TH	405	status = "okay";
	406	};
	407
	408	&ssi1 {
b5f37b76 TH	409	status = "okay";
	410	};
	411
	412	&ssi2 {
b5f37b76 TH	413	status = "okay";
	414	};
	415
	416	&uart1 {
	417	pinctrl-names = "default";
	418	pinctrl-0 = <&pinctrl_uart1>;
82515ff7	419	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
b5f37b76 TH	420	status = "okay";
	421	};
	422
	423	&uart2 {
	424	pinctrl-names = "default";
	425	pinctrl-0 = <&pinctrl_uart2>;
	426	status = "okay";
	427	};
	428
	429	&uart5 {
	430	pinctrl-names = "default";
	431	pinctrl-0 = <&pinctrl_uart5>;
	432	status = "okay";
	433	};
	434
	435	&usbotg {
	436	vbus-supply = <&reg_usb_otg_vbus>;
	437	pinctrl-names = "default";
	438	pinctrl-0 = <&pinctrl_usbotg>;
	439	disable-over-current;
	440	status = "okay";
	441	};
	442
	443	&usbh1 {
	444	vbus-supply = <&reg_usb_h1_vbus>;
	445	status = "okay";
	446	};
	447
	448	&usdhc3 {
3ee12d80	449	pinctrl-names = "default", "state_100mhz", "state_200mhz";
b5f37b76	450	pinctrl-0 = <&pinctrl_usdhc3>;
3ee12d80 TH	451	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
3ee12d80 TH	452	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
89c1a8cf	453	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
b5f37b76	454	vmmc-supply = <&reg_3p3v>;
3ee12d80	455	no-1-8-v; /* firmware will remove if board revision supports */
b5f37b76 TH	456	status = "okay";
	457	};
	458
51a012b7 TH	459	&wdog1 {
	460	status = "disabled";
	461	};
	462
	463	&wdog2 {
	464	pinctrl-names = "default";
	465	pinctrl-0 = <&pinctrl_wdog>;
	466	fsl,ext-reset-output;
	467	status = "okay";
	468	};
	469
b5f37b76	470	&iomuxc {
d31c46c0 TH	471	pinctrl_audmux: audmuxgrp {
	472	fsl,pins = <
	473	MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
	474	MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
	475	MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
	476	MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
	477	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
	478	>;
	479	};
e3946fe8	480
d31c46c0 TH	481	pinctrl_enet: enetgrp {
	482	fsl,pins = <
	483	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	484	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	485	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	486	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	487	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	488	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
	489	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	490	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	491	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	492	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	493	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	494	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
	495	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	496	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	497	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	498	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	499	>;
	500	};
e3946fe8	501
d31c46c0 TH	502	pinctrl_ecspi2: escpi2grp {
	503	fsl,pins = <
	504	MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
	505	MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
	506	MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
	507	MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
	508	>;
	509	};
b0a5c46d	510
d31c46c0 TH	511	pinctrl_flexcan1: flexcan1grp {
	512	fsl,pins = <
	513	MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
	514	MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
	515	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
	516	>;
	517	};
b5f37b76	518
d31c46c0 TH	519	pinctrl_gpio_leds: gpioledsgrp {
	520	fsl,pins = <
	521	MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
	522	MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
	523	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
	524	>;
	525	};
e3946fe8	526
d31c46c0 TH	527	pinctrl_gpmi_nand: gpminandgrp {
	528	fsl,pins = <
	529	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	530	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	531	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	532	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	533	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	534	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	535	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	536	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	537	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	538	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	539	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	540	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	541	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	542	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	543	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	544	>;
	545	};
e3946fe8	546
d31c46c0 TH	547	pinctrl_i2c1: i2c1grp {
	548	fsl,pins = <
	549	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	550	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	551	>;
	552	};
e3946fe8	553
d31c46c0 TH	554	pinctrl_i2c2: i2c2grp {
	555	fsl,pins = <
	556	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	557	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	558	>;
	559	};
e3946fe8	560
d31c46c0 TH	561	pinctrl_i2c3: i2c3grp {
	562	fsl,pins = <
	563	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	564	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	565	>;
	566	};
e3946fe8	567
d31c46c0 TH	568	pinctrl_pcie: pciegrp {
	569	fsl,pins = <
	570	MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
	571	MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
	572	>;
	573	};
b5f37b76	574
d31c46c0 TH	575	pinctrl_pps: ppsgrp {
	576	fsl,pins = <
	577	MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
	578	>;
	579	};
b5f37b76	580
d31c46c0 TH	581	pinctrl_pwm1: pwm1grp {
	582	fsl,pins = <
	583	MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
	584	>;
	585	};
aa2b2178	586
d31c46c0 TH	587	pinctrl_pwm2: pwm2grp {
	588	fsl,pins = <
	589	MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
	590	>;
	591	};
aa2b2178	592
d31c46c0 TH	593	pinctrl_pwm3: pwm3grp {
	594	fsl,pins = <
	595	MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
	596	>;
	597	};
aa2b2178	598
d31c46c0 TH	599	pinctrl_pwm4_backlight: pwm4grpbacklight {
	600	fsl,pins = <
	601	/* LVDS_PWM J6.5 */
	602	MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
	603	>;
	604	};
b3253241	605
d31c46c0 TH	606	pinctrl_pwm4_dio: pwm4grpdio {
	607	fsl,pins = <
	608	/* DIO3 J16.4 */
	609	MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
	610	>;
	611	};
f8ea256e	612
d31c46c0 TH	613	pinctrl_uart1: uart1grp {
	614	fsl,pins = <
	615	MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
	616	MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
	617	MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
	618	>;
	619	};
e3946fe8	620
d31c46c0 TH	621	pinctrl_uart2: uart2grp {
	622	fsl,pins = <
	623	MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
	624	MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
	625	>;
	626	};
e3946fe8	627
d31c46c0 TH	628	pinctrl_uart5: uart5grp {
	629	fsl,pins = <
	630	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	631	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	632	>;
	633	};
e3946fe8	634
d31c46c0 TH	635	pinctrl_usbotg: usbotggrp {
	636	fsl,pins = <
	637	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
	638	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
	639	>;
	640	};
e3946fe8	641
d31c46c0 TH	642	pinctrl_usdhc3: usdhc3grp {
	643	fsl,pins = <
	644	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	645	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	646	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	647	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	648	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	649	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	650	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
	651	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
	652	>;
	653	};
3ee12d80	654
d31c46c0 TH	655	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	656	fsl,pins = <
	657	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
	658	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
	659	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
	660	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
	661	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
	662	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
	663	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
	664	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
	665	>;
	666	};
3ee12d80	667
d31c46c0 TH	668	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	669	fsl,pins = <
	670	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	671	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	672	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	673	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	674	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	675	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	676	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
	677	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
	678	>;
	679	};
51a012b7	680
d31c46c0 TH	681	pinctrl_wdog: wdoggrp {
	682	fsl,pins = <
	683	MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
	684	>;
e3946fe8 TH	685	};
e3946fe8 TH	686	};