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Merge remote-tracking branches 'asoc/fix/rt5665', 'asoc/fix/simple', 'asoc/fix/sti...
[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-gw51xx.dtsi
CommitLineData
e3946fe8
TH		 1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
326cdb16
TH		 12#include <dt-bindings/gpio/gpio.h>
13
e3946fe8
TH		 14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
e3946fe8
TH		 17 led0 = &led0;
18 led1 = &led1;
19 nand = &gpmi;
20 usb0 = &usbh1;
21 usb1 = &usbotg;
22 };
23
24 chosen {
25 bootargs = "console=ttymxc1,115200";
26 };
27
28 leds {
29 compatible = "gpio-leds";
b5f37b76
TH		 30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_gpio_leds>;
e3946fe8
TH		 32
33 led0: user1 {
34 label = "user1";
326cdb16 35 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
e3946fe8
TH		 36 default-state = "on";
37 linux,default-trigger = "heartbeat";
38 };
39
40 led1: user2 {
41 label = "user2";
326cdb16 42 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
e3946fe8
TH		 43 default-state = "off";
44 };
45 };
46
47 memory {
48 reg = <0x10000000 0x20000000>;
49 };
50
51 pps {
52 compatible = "pps-gpio";
b5f37b76
TH		 53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_pps>;
326cdb16 55 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
e3946fe8
TH		 56 status = "okay";
57 };
58
5051bff3
TH		 59 reg_3p3v: regulator-3p3v {
60 compatible = "regulator-fixed";
61 regulator-name = "3P3V";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 regulator-always-on;
65 };
e3946fe8 66
5051bff3
TH		 67 reg_5p0v: regulator-5p0v {
68 compatible = "regulator-fixed";
69 regulator-name = "5P0V";
70 regulator-min-microvolt = <5000000>;
71 regulator-max-microvolt = <5000000>;
72 regulator-always-on;
73 };
e3946fe8 74
5051bff3
TH		 75 reg_usb_otg_vbus: regulator-usb-otg-vbus {
76 compatible = "regulator-fixed";
77 regulator-name = "usb_otg_vbus";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
81 enable-active-high;
e3946fe8
TH		 82 };
83};
84
85&fec {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_enet>;
3a35e470 88 phy-mode = "rgmii-id";
326cdb16 89 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
e3946fe8
TH		 90 status = "okay";
91};
92
93&gpmi {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_gpmi_nand>;
96 status = "okay";
97};
98
aef15dba
TH		 99&hdmi {
100 ddc-i2c-bus = <&i2c3>;
101 status = "okay";
102};
103
e3946fe8
TH		 104&i2c1 {
105 clock-frequency = <100000>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_i2c1>;
108 status = "okay";
109
110 eeprom1: eeprom@50 {
111 compatible = "atmel,24c02";
112 reg = <0x50>;
113 pagesize = <16>;
114 };
115
116 eeprom2: eeprom@51 {
117 compatible = "atmel,24c02";
118 reg = <0x51>;
119 pagesize = <16>;
120 };
121
122 eeprom3: eeprom@52 {
123 compatible = "atmel,24c02";
124 reg = <0x52>;
125 pagesize = <16>;
126 };
127
128 eeprom4: eeprom@53 {
129 compatible = "atmel,24c02";
130 reg = <0x53>;
131 pagesize = <16>;
132 };
133
134 gpio: pca9555@23 {
135 compatible = "nxp,pca9555";
136 reg = <0x23>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
e3946fe8
TH		 141 rtc: ds1672@68 {
142 compatible = "dallas,ds1672";
143 reg = <0x68>;
144 };
145};
146
147&i2c2 {
148 clock-frequency = <100000>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_i2c2>;
151 status = "okay";
5051bff3
TH		 152
153 ltc3676: pmic@3c {
154 compatible = "lltc,ltc3676";
155 reg = <0x3c>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_pmic>;
158 interrupt-parent = <&gpio1>;
159 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
160
161 regulators {
162 /* VDD_SOC (1+R1/R2 = 1.635) */
163 reg_vdd_soc: sw1 {
164 regulator-name = "vddsoc";
165 regulator-min-microvolt = <674400>;
166 regulator-max-microvolt = <1308000>;
167 lltc,fb-voltage-divider = <127000 200000>;
168 regulator-ramp-delay = <7000>;
169 regulator-boot-on;
170 regulator-always-on;
171 };
172
173 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
174 reg_1p8v: sw2 {
175 regulator-name = "vdd1p8";
176 regulator-min-microvolt = <1033310>;
177 regulator-max-microvolt = <2004000>;
178 lltc,fb-voltage-divider = <301000 200000>;
179 regulator-ramp-delay = <7000>;
180 regulator-boot-on;
181 regulator-always-on;
182 };
183
184 /* VDD_ARM (1+R1/R2 = 1.635) */
185 reg_vdd_arm: sw3 {
186 regulator-name = "vddarm";
187 regulator-min-microvolt = <674400>;
188 regulator-max-microvolt = <1308000>;
189 lltc,fb-voltage-divider = <127000 200000>;
190 regulator-ramp-delay = <7000>;
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 /* VDD_DDR (1+R1/R2 = 2.105) */
196 reg_vdd_ddr: sw4 {
197 regulator-name = "vddddr";
198 regulator-min-microvolt = <868310>;
199 regulator-max-microvolt = <1684000>;
200 lltc,fb-voltage-divider = <221000 200000>;
201 regulator-ramp-delay = <7000>;
202 regulator-boot-on;
203 regulator-always-on;
204 };
205
206 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
207 reg_2p5v: ldo2 {
208 regulator-name = "vdd2p5";
209 regulator-min-microvolt = <2490375>;
210 regulator-max-microvolt = <2490375>;
211 lltc,fb-voltage-divider = <487000 200000>;
212 regulator-boot-on;
213 regulator-always-on;
214 };
215
216 /* VDD_HIGH (1+R1/R2 = 4.17) */
217 reg_3p0v: ldo4 {
218 regulator-name = "vdd3p0";
219 regulator-min-microvolt = <3023250>;
220 regulator-max-microvolt = <3023250>;
221 lltc,fb-voltage-divider = <634000 200000>;
222 regulator-boot-on;
223 regulator-always-on;
224 };
225 };
226 };
e3946fe8
TH		 227};
228
229&i2c3 {
230 clock-frequency = <100000>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c3>;
233 status = "okay";
e3946fe8
TH		 234};
235
b5f37b76 236&pcie {
e3946fe8 237 pinctrl-names = "default";
b5f37b76
TH		 238 pinctrl-0 = <&pinctrl_pcie>;
239 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
240 status = "okay";
241};
e3946fe8 242
aa2b2178
TH		 243&pwm2 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
246 status = "disabled";
247};
248
249&pwm3 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
252 status = "disabled";
253};
254
255&pwm4 {
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
258 status = "disabled";
259};
260
b5f37b76
TH		 261&uart1 {
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_uart1>;
264 status = "okay";
265};
266
267&uart2 {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_uart2>;
270 status = "okay";
271};
272
273&uart3 {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_uart3>;
276 status = "okay";
277};
e3946fe8 278
b5f37b76
TH		 279&uart5 {
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_uart5>;
282 status = "okay";
283};
284
285&usbotg {
286 vbus-supply = <&reg_usb_otg_vbus>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_usbotg>;
289 disable-over-current;
290 status = "okay";
291};
292
293&usbh1 {
294 status = "okay";
295};
296
51a012b7
TH		 297&wdog1 {
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_wdog>;
300 fsl,ext-reset-output;
301};
302
b5f37b76
TH		 303&iomuxc {
304 imx6qdl-gw51xx {
e3946fe8
TH		 305 pinctrl_enet: enetgrp {
306 fsl,pins = <
c007b3a6
UKK		 307 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
308 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
309 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
310 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
311 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
312 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
313 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
314 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
315 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
316 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
317 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
318 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
e3946fe8
TH		 319 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
320 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
321 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
322 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
b5f37b76
TH		 323 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
324 >;
325 };
326
327 pinctrl_gpio_leds: gpioledsgrp {
328 fsl,pins = <
329 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
330 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
e3946fe8
TH		 331 >;
332 };
333
334 pinctrl_gpmi_nand: gpminandgrp {
335 fsl,pins = <
336 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
337 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
338 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
339 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
340 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
e3946fe8
TH		 341 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
342 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
343 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
344 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
345 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
346 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
347 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
348 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
349 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
350 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
351 >;
352 };
353
354 pinctrl_i2c1: i2c1grp {
355 fsl,pins = <
356 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
357 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
358 >;
359 };
360
361 pinctrl_i2c2: i2c2grp {
362 fsl,pins = <
363 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
364 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
365 >;
366 };
367
368 pinctrl_i2c3: i2c3grp {
369 fsl,pins = <
370 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
371 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
372 >;
373 };
374
b5f37b76
TH		 375 pinctrl_pcie: pciegrp {
376 fsl,pins = <
377 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
378 >;
379 };
380
5051bff3
TH		 381 pinctrl_pmic: pmicgrp {
382 fsl,pins = <
383 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
384 >;
385 };
386
b5f37b76
TH		 387 pinctrl_pps: ppsgrp {
388 fsl,pins = <
389 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
390 >;
391 };
392
aa2b2178
TH		 393 pinctrl_pwm2: pwm2grp {
394 fsl,pins = <
395 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
396 >;
397 };
398
399 pinctrl_pwm3: pwm3grp {
400 fsl,pins = <
c382e5cc 401 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
aa2b2178
TH		 402 >;
403 };
404
405 pinctrl_pwm4: pwm4grp {
406 fsl,pins = <
c382e5cc 407 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
aa2b2178
TH		 408 >;
409 };
410
e3946fe8
TH		 411 pinctrl_uart1: uart1grp {
412 fsl,pins = <
413 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
414 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
415 >;
416 };
417
418 pinctrl_uart2: uart2grp {
419 fsl,pins = <
420 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
421 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
422 >;
423 };
424
425 pinctrl_uart3: uart3grp {
426 fsl,pins = <
427 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
428 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
429 >;
430 };
431
432 pinctrl_uart5: uart5grp {
433 fsl,pins = <
434 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
435 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
436 >;
437 };
438
439 pinctrl_usbotg: usbotggrp {
440 fsl,pins = <
441 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
b5f37b76 442 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
e3946fe8
TH		 443 >;
444 };
51a012b7
TH		 445
446 pinctrl_wdog: wdoggrp {
447 fsl,pins = <
448 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
449 >;
450 };
e3946fe8
TH		 451 };
452};
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