[linux-2.6-block.git] / arch / arm / boot / dts / imx6q.dtsi


/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
#include "imx6qdl.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			operating-points = <
				/* kHz    uV */
				1200000 1275000
				996000  1250000
				792000  1150000
				396000  975000
			>;
			fsl,soc-operating-points = <
				/* ARM kHz  SOC-PU uV */
				1200000 1275000
				996000	1250000
				792000	1175000
				396000	1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks 104>, <&clks 6>, <&clks 16>,
				 <&clks 17>, <&clks 170>;
			clock-names = "arm", "pll2_pfd2_396m", "step",
				      "pll1_sw", "pll1_sys";
			arm-supply = <&reg_arm>;
			pu-supply = <&reg_pu>;
			soc-supply = <&reg_soc>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	soc {
		ocram: sram@00900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x40000>;
			clocks = <&clks 142>;
		};

		aips-bus@02000000 { /* AIPS1 */
			spba-bus@02000000 {
				ecspi5: ecspi@02018000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02018000 0x4000>;
					interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks 116>, <&clks 116>;
					clock-names = "ipg", "per";
					status = "disabled";
				};
			};

			iomuxc: iomuxc@020e0000 {
				compatible = "fsl,imx6q-iomuxc";

				ipu2 {
					pinctrl_ipu2_1: ipu2grp-1 {
						fsl,pins = <
							MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
							MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
							MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
							MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
							MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
							MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
							MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
							MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
							MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
							MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
							MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
							MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
							MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
							MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
							MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
							MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
							MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
							MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
							MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
							MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
							MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
							MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
							MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
							MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
							MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
							MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
							MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
							MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
							MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
						>;
					};
				};
			};
		};

		sata: sata@02200000 {
			compatible = "fsl,imx6q-ahci";
			reg = <0x02200000 0x4000>;
			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
			clock-names = "sata", "sata_ref", "ahb";
			status = "disabled";
		};

		ipu2: ipu@02800000 {
			#crtc-cells = <1>;
			compatible = "fsl,imx6q-ipu";
			reg = <0x02800000 0x400000>;
			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 133>, <&clks 134>, <&clks 137>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 4>;
		};
	};
};

&ldb {
	clocks = <&clks 33>, <&clks 34>,
		 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
		 <&clks 135>, <&clks 136>;
	clock-names = "di0_pll", "di1_pll",
		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
		      "di0", "di1";

	lvds-channel@0 {
		crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
	};

	lvds-channel@1 {
		crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
	};
};
Commit	Line	Data
7c1da585 SG	1
	2	/*
	3	* Copyright 2013 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	*/
	10
e6117ff3	11	#include <dt-bindings/interrupt-controller/irq.h>
e1641531	12	#include "imx6q-pinfunc.h"
c56009b2	13	#include "imx6qdl.dtsi"
7c1da585 SG	14
	15	/ {
	16	cpus {
	17	#address-cells = <1>;
	18	#size-cells = <0>;
	19
	20	cpu@0 {
	21	compatible = "arm,cortex-a9";
7925e89f	22	device_type = "cpu";
7c1da585 SG	23	reg = <0>;
	24	next-level-cache = <&L2>;
	25	operating-points = <
	26	/* kHz uV */
	27	1200000 1275000
	28	996000 1250000
	29	792000 1150000
26ea5801	30	396000 975000
7c1da585	31	>;
69171eda AH	32	fsl,soc-operating-points = <
	33	/* ARM kHz SOC-PU uV */
	34	1200000 1275000
	35	996000 1250000
	36	792000 1175000
	37	396000 1175000
	38	>;
7c1da585 SG	39	clock-latency = <61036>; /* two CLK32 periods */
	40	clocks = <&clks 104>, <&clks 6>, <&clks 16>,
	41	<&clks 17>, <&clks 170>;
	42	clock-names = "arm", "pll2_pfd2_396m", "step",
	43	"pll1_sw", "pll1_sys";
	44	arm-supply = <&reg_arm>;
	45	pu-supply = <&reg_pu>;
	46	soc-supply = <&reg_soc>;
	47	};
	48
	49	cpu@1 {
	50	compatible = "arm,cortex-a9";
7925e89f	51	device_type = "cpu";
7c1da585 SG	52	reg = <1>;
	53	next-level-cache = <&L2>;
	54	};
	55
	56	cpu@2 {
	57	compatible = "arm,cortex-a9";
7925e89f	58	device_type = "cpu";
7c1da585 SG	59	reg = <2>;
	60	next-level-cache = <&L2>;
	61	};
	62
	63	cpu@3 {
	64	compatible = "arm,cortex-a9";
7925e89f	65	device_type = "cpu";
7c1da585 SG	66	reg = <3>;
	67	next-level-cache = <&L2>;
	68	};
	69	};
	70
	71	soc {
951ebf58 SG	72	ocram: sram@00900000 {
	73	compatible = "mmio-sram";
	74	reg = <0x00900000 0x40000>;
	75	clocks = <&clks 142>;
	76	};
	77
7c1da585 SG	78	aips-bus@02000000 { /* AIPS1 */
	79	spba-bus@02000000 {
	80	ecspi5: ecspi@02018000 {
	81	#address-cells = <1>;
	82	#size-cells = <0>;
	83	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	84	reg = <0x02018000 0x4000>;
e6117ff3	85	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
7c1da585 SG	86	clocks = <&clks 116>, <&clks 116>;
	87	clock-names = "ipg", "per";
	88	status = "disabled";
	89	};
	90	};
	91
	92	iomuxc: iomuxc@020e0000 {
	93	compatible = "fsl,imx6q-iomuxc";
b72ce929 SG	94
	95	ipu2 {
	96	pinctrl_ipu2_1: ipu2grp-1 {
	97	fsl,pins = <
	98	MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
	99	MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
	100	MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
	101	MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
	102	MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
	103	MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
	104	MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
	105	MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
	106	MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
	107	MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
	108	MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
	109	MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
	110	MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
	111	MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
	112	MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
	113	MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
	114	MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
	115	MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
	116	MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
	117	MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
	118	MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
	119	MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
	120	MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
	121	MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
	122	MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
	123	MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
	124	MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
	125	MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
	126	MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
	127	>;
	128	};
	129	};
7c1da585 SG	130	};
	131	};
	132
0fb1f804 RZ	133	sata: sata@02200000 {
	134	compatible = "fsl,imx6q-ahci";
	135	reg = <0x02200000 0x4000>;
e6117ff3	136	interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
0fb1f804 RZ	137	clocks = <&clks 154>, <&clks 187>, <&clks 105>;
	138	clock-names = "sata", "sata_ref", "ahb";
	139	status = "disabled";
	140	};
	141
7c1da585 SG	142	ipu2: ipu@02800000 {
	143	#crtc-cells = <1>;
	144	compatible = "fsl,imx6q-ipu";
	145	reg = <0x02800000 0x400000>;
e6117ff3 TK	146	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
e6117ff3 TK	147	<0 7 IRQ_TYPE_LEVEL_HIGH>;
7c1da585 SG	148	clocks = <&clks 133>, <&clks 134>, <&clks 137>;
7c1da585 SG	149	clock-names = "bus", "di0", "di1";
09ebf366	150	resets = <&src 4>;
7c1da585 SG	151	};
	152	};
	153	};
41c04342 ST	154
	155	&ldb {
	156	clocks = <&clks 33>, <&clks 34>,
	157	<&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
	158	<&clks 135>, <&clks 136>;
	159	clock-names = "di0_pll", "di1_pll",
	160	"di0_sel", "di1_sel", "di2_sel", "di3_sel",
	161	"di0", "di1";
	162
	163	lvds-channel@0 {
	164	crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
	165	};
	166
	167	lvds-channel@1 {
	168	crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
	169	};
	170	};