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7c1da585 SG |
1 | |
2 | /* | |
3 | * Copyright 2013 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | */ | |
10 | ||
e6117ff3 | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
e1641531 | 12 | #include "imx6q-pinfunc.h" |
c56009b2 | 13 | #include "imx6qdl.dtsi" |
7c1da585 SG |
14 | |
15 | / { | |
a26be0f0 SH |
16 | aliases { |
17 | spi4 = &ecspi5; | |
18 | }; | |
19 | ||
7c1da585 SG |
20 | cpus { |
21 | #address-cells = <1>; | |
22 | #size-cells = <0>; | |
23 | ||
24 | cpu@0 { | |
25 | compatible = "arm,cortex-a9"; | |
7925e89f | 26 | device_type = "cpu"; |
7c1da585 SG |
27 | reg = <0>; |
28 | next-level-cache = <&L2>; | |
29 | operating-points = < | |
30 | /* kHz uV */ | |
31 | 1200000 1275000 | |
32 | 996000 1250000 | |
89ef8ef4 | 33 | 852000 1250000 |
7c1da585 | 34 | 792000 1150000 |
26ea5801 | 35 | 396000 975000 |
7c1da585 | 36 | >; |
69171eda AH |
37 | fsl,soc-operating-points = < |
38 | /* ARM kHz SOC-PU uV */ | |
39 | 1200000 1275000 | |
40 | 996000 1250000 | |
89ef8ef4 | 41 | 852000 1250000 |
69171eda AH |
42 | 792000 1175000 |
43 | 396000 1175000 | |
7c1da585 SG |
44 | >; |
45 | clock-latency = <61036>; /* two CLK32 periods */ | |
46 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, | |
47 | <&clks 17>, <&clks 170>; | |
48 | clock-names = "arm", "pll2_pfd2_396m", "step", | |
49 | "pll1_sw", "pll1_sys"; | |
50 | arm-supply = <®_arm>; | |
51 | pu-supply = <®_pu>; | |
52 | soc-supply = <®_soc>; | |
53 | }; | |
54 | ||
55 | cpu@1 { | |
56 | compatible = "arm,cortex-a9"; | |
7925e89f | 57 | device_type = "cpu"; |
7c1da585 SG |
58 | reg = <1>; |
59 | next-level-cache = <&L2>; | |
60 | }; | |
61 | ||
62 | cpu@2 { | |
63 | compatible = "arm,cortex-a9"; | |
7925e89f | 64 | device_type = "cpu"; |
7c1da585 SG |
65 | reg = <2>; |
66 | next-level-cache = <&L2>; | |
67 | }; | |
68 | ||
69 | cpu@3 { | |
70 | compatible = "arm,cortex-a9"; | |
7925e89f | 71 | device_type = "cpu"; |
7c1da585 SG |
72 | reg = <3>; |
73 | next-level-cache = <&L2>; | |
74 | }; | |
75 | }; | |
76 | ||
77 | soc { | |
951ebf58 SG |
78 | ocram: sram@00900000 { |
79 | compatible = "mmio-sram"; | |
80 | reg = <0x00900000 0x40000>; | |
81 | clocks = <&clks 142>; | |
82 | }; | |
83 | ||
7c1da585 SG |
84 | aips-bus@02000000 { /* AIPS1 */ |
85 | spba-bus@02000000 { | |
86 | ecspi5: ecspi@02018000 { | |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
89 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
90 | reg = <0x02018000 0x4000>; | |
e6117ff3 | 91 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
7c1da585 SG |
92 | clocks = <&clks 116>, <&clks 116>; |
93 | clock-names = "ipg", "per"; | |
94 | status = "disabled"; | |
95 | }; | |
96 | }; | |
97 | ||
98 | iomuxc: iomuxc@020e0000 { | |
99 | compatible = "fsl,imx6q-iomuxc"; | |
b72ce929 SG |
100 | |
101 | ipu2 { | |
102 | pinctrl_ipu2_1: ipu2grp-1 { | |
103 | fsl,pins = < | |
104 | MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 | |
105 | MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 | |
106 | MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 | |
107 | MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 | |
108 | MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 | |
109 | MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 | |
110 | MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 | |
111 | MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 | |
112 | MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 | |
113 | MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 | |
114 | MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 | |
115 | MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 | |
116 | MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 | |
117 | MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 | |
118 | MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 | |
119 | MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 | |
120 | MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 | |
121 | MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 | |
122 | MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 | |
123 | MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 | |
124 | MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 | |
125 | MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 | |
126 | MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 | |
127 | MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 | |
128 | MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 | |
129 | MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 | |
130 | MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 | |
131 | MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 | |
132 | MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 | |
133 | >; | |
134 | }; | |
135 | }; | |
7c1da585 SG |
136 | }; |
137 | }; | |
138 | ||
0fb1f804 RZ |
139 | sata: sata@02200000 { |
140 | compatible = "fsl,imx6q-ahci"; | |
141 | reg = <0x02200000 0x4000>; | |
e6117ff3 | 142 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
0fb1f804 RZ |
143 | clocks = <&clks 154>, <&clks 187>, <&clks 105>; |
144 | clock-names = "sata", "sata_ref", "ahb"; | |
145 | status = "disabled"; | |
146 | }; | |
147 | ||
7c1da585 | 148 | ipu2: ipu@02800000 { |
4520e692 PZ |
149 | #address-cells = <1>; |
150 | #size-cells = <0>; | |
7c1da585 SG |
151 | compatible = "fsl,imx6q-ipu"; |
152 | reg = <0x02800000 0x400000>; | |
e6117ff3 TK |
153 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, |
154 | <0 7 IRQ_TYPE_LEVEL_HIGH>; | |
7c1da585 SG |
155 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; |
156 | clock-names = "bus", "di0", "di1"; | |
09ebf366 | 157 | resets = <&src 4>; |
4520e692 PZ |
158 | |
159 | ipu2_di0: port@2 { | |
160 | #address-cells = <1>; | |
161 | #size-cells = <0>; | |
162 | reg = <2>; | |
163 | ||
164 | ipu2_di0_disp0: endpoint@0 { | |
165 | }; | |
166 | ||
167 | ipu2_di0_hdmi: endpoint@1 { | |
168 | remote-endpoint = <&hdmi_mux_2>; | |
169 | }; | |
170 | ||
171 | ipu2_di0_mipi: endpoint@2 { | |
172 | }; | |
173 | ||
174 | ipu2_di0_lvds0: endpoint@3 { | |
175 | remote-endpoint = <&lvds0_mux_2>; | |
176 | }; | |
177 | ||
178 | ipu2_di0_lvds1: endpoint@4 { | |
179 | remote-endpoint = <&lvds1_mux_2>; | |
180 | }; | |
181 | }; | |
182 | ||
183 | ipu2_di1: port@3 { | |
184 | #address-cells = <1>; | |
185 | #size-cells = <0>; | |
186 | reg = <3>; | |
187 | ||
188 | ipu2_di1_hdmi: endpoint@1 { | |
189 | remote-endpoint = <&hdmi_mux_3>; | |
190 | }; | |
191 | ||
192 | ipu2_di1_mipi: endpoint@2 { | |
193 | }; | |
194 | ||
195 | ipu2_di1_lvds0: endpoint@3 { | |
196 | remote-endpoint = <&lvds0_mux_3>; | |
197 | }; | |
198 | ||
199 | ipu2_di1_lvds1: endpoint@4 { | |
200 | remote-endpoint = <&lvds1_mux_3>; | |
201 | }; | |
202 | }; | |
203 | }; | |
204 | }; | |
205 | ||
206 | display-subsystem { | |
207 | compatible = "fsl,imx-display-subsystem"; | |
208 | ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; | |
209 | }; | |
210 | }; | |
211 | ||
212 | &hdmi { | |
213 | compatible = "fsl,imx6q-hdmi"; | |
214 | ||
215 | port@2 { | |
216 | reg = <2>; | |
217 | ||
218 | hdmi_mux_2: endpoint { | |
219 | remote-endpoint = <&ipu2_di0_hdmi>; | |
220 | }; | |
221 | }; | |
222 | ||
223 | port@3 { | |
224 | reg = <3>; | |
225 | ||
226 | hdmi_mux_3: endpoint { | |
227 | remote-endpoint = <&ipu2_di1_hdmi>; | |
7c1da585 SG |
228 | }; |
229 | }; | |
230 | }; | |
41c04342 ST |
231 | |
232 | &ldb { | |
233 | clocks = <&clks 33>, <&clks 34>, | |
234 | <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, | |
235 | <&clks 135>, <&clks 136>; | |
236 | clock-names = "di0_pll", "di1_pll", | |
237 | "di0_sel", "di1_sel", "di2_sel", "di3_sel", | |
238 | "di0", "di1"; | |
239 | ||
240 | lvds-channel@0 { | |
4520e692 PZ |
241 | port@2 { |
242 | reg = <2>; | |
243 | ||
244 | lvds0_mux_2: endpoint { | |
245 | remote-endpoint = <&ipu2_di0_lvds0>; | |
246 | }; | |
247 | }; | |
248 | ||
249 | port@3 { | |
250 | reg = <3>; | |
251 | ||
252 | lvds0_mux_3: endpoint { | |
253 | remote-endpoint = <&ipu2_di1_lvds0>; | |
254 | }; | |
255 | }; | |
41c04342 ST |
256 | }; |
257 | ||
258 | lvds-channel@1 { | |
4520e692 PZ |
259 | port@2 { |
260 | reg = <2>; | |
261 | ||
262 | lvds1_mux_2: endpoint { | |
263 | remote-endpoint = <&ipu2_di0_lvds1>; | |
264 | }; | |
265 | }; | |
266 | ||
267 | port@3 { | |
268 | reg = <3>; | |
269 | ||
270 | lvds1_mux_3: endpoint { | |
271 | remote-endpoint = <&ipu2_di1_lvds1>; | |
272 | }; | |
273 | }; | |
41c04342 ST |
274 | }; |
275 | }; | |
04cec1a2 | 276 | |
4520e692 PZ |
277 | &mipi_dsi { |
278 | port@2 { | |
279 | reg = <2>; | |
280 | ||
281 | mipi_mux_2: endpoint { | |
282 | remote-endpoint = <&ipu2_di0_mipi>; | |
283 | }; | |
284 | }; | |
285 | ||
286 | port@3 { | |
287 | reg = <3>; | |
288 | ||
289 | mipi_mux_3: endpoint { | |
290 | remote-endpoint = <&ipu2_di1_mipi>; | |
291 | }; | |
292 | }; | |
04cec1a2 | 293 | }; |