Commit | Line | Data |
---|---|---|
73d2b4cd SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /include/ "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
8f9ffecf RZ |
17 | serial0 = &uart1; |
18 | serial1 = &uart2; | |
19 | serial2 = &uart3; | |
20 | serial3 = &uart4; | |
21 | serial4 = &uart5; | |
73d2b4cd SG |
22 | }; |
23 | ||
24 | tzic: tz-interrupt-controller@0fffc000 { | |
25 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
26 | interrupt-controller; | |
27 | #interrupt-cells = <1>; | |
28 | reg = <0x0fffc000 0x4000>; | |
29 | }; | |
30 | ||
31 | clocks { | |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | ||
35 | ckil { | |
36 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
37 | clock-frequency = <32768>; | |
38 | }; | |
39 | ||
40 | ckih1 { | |
41 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
42 | clock-frequency = <22579200>; | |
43 | }; | |
44 | ||
45 | ckih2 { | |
46 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
47 | clock-frequency = <0>; | |
48 | }; | |
49 | ||
50 | osc { | |
51 | compatible = "fsl,imx-osc", "fixed-clock"; | |
52 | clock-frequency = <24000000>; | |
53 | }; | |
54 | }; | |
55 | ||
56 | soc { | |
57 | #address-cells = <1>; | |
58 | #size-cells = <1>; | |
59 | compatible = "simple-bus"; | |
60 | interrupt-parent = <&tzic>; | |
61 | ranges; | |
62 | ||
63 | aips@50000000 { /* AIPS1 */ | |
64 | compatible = "fsl,aips-bus", "simple-bus"; | |
65 | #address-cells = <1>; | |
66 | #size-cells = <1>; | |
67 | reg = <0x50000000 0x10000000>; | |
68 | ranges; | |
69 | ||
70 | spba@50000000 { | |
71 | compatible = "fsl,spba-bus", "simple-bus"; | |
72 | #address-cells = <1>; | |
73 | #size-cells = <1>; | |
74 | reg = <0x50000000 0x40000>; | |
75 | ranges; | |
76 | ||
77 | esdhc@50004000 { /* ESDHC1 */ | |
78 | compatible = "fsl,imx53-esdhc"; | |
79 | reg = <0x50004000 0x4000>; | |
80 | interrupts = <1>; | |
81 | status = "disabled"; | |
82 | }; | |
83 | ||
84 | esdhc@50008000 { /* ESDHC2 */ | |
85 | compatible = "fsl,imx53-esdhc"; | |
86 | reg = <0x50008000 0x4000>; | |
87 | interrupts = <2>; | |
88 | status = "disabled"; | |
89 | }; | |
90 | ||
0c456cfa | 91 | uart3: serial@5000c000 { |
73d2b4cd SG |
92 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
93 | reg = <0x5000c000 0x4000>; | |
94 | interrupts = <33>; | |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
98 | ecspi@50010000 { /* ECSPI1 */ | |
99 | #address-cells = <1>; | |
100 | #size-cells = <0>; | |
101 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
102 | reg = <0x50010000 0x4000>; | |
103 | interrupts = <36>; | |
104 | status = "disabled"; | |
105 | }; | |
106 | ||
107 | esdhc@50020000 { /* ESDHC3 */ | |
108 | compatible = "fsl,imx53-esdhc"; | |
109 | reg = <0x50020000 0x4000>; | |
110 | interrupts = <3>; | |
111 | status = "disabled"; | |
112 | }; | |
113 | ||
114 | esdhc@50024000 { /* ESDHC4 */ | |
115 | compatible = "fsl,imx53-esdhc"; | |
116 | reg = <0x50024000 0x4000>; | |
117 | interrupts = <4>; | |
118 | status = "disabled"; | |
119 | }; | |
120 | }; | |
121 | ||
4d191868 | 122 | gpio1: gpio@53f84000 { |
73d2b4cd SG |
123 | compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; |
124 | reg = <0x53f84000 0x4000>; | |
125 | interrupts = <50 51>; | |
126 | gpio-controller; | |
127 | #gpio-cells = <2>; | |
128 | interrupt-controller; | |
129 | #interrupt-cells = <1>; | |
130 | }; | |
131 | ||
4d191868 | 132 | gpio2: gpio@53f88000 { |
73d2b4cd SG |
133 | compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; |
134 | reg = <0x53f88000 0x4000>; | |
135 | interrupts = <52 53>; | |
136 | gpio-controller; | |
137 | #gpio-cells = <2>; | |
138 | interrupt-controller; | |
139 | #interrupt-cells = <1>; | |
140 | }; | |
141 | ||
4d191868 | 142 | gpio3: gpio@53f8c000 { |
73d2b4cd SG |
143 | compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; |
144 | reg = <0x53f8c000 0x4000>; | |
145 | interrupts = <54 55>; | |
146 | gpio-controller; | |
147 | #gpio-cells = <2>; | |
148 | interrupt-controller; | |
149 | #interrupt-cells = <1>; | |
150 | }; | |
151 | ||
4d191868 | 152 | gpio4: gpio@53f90000 { |
73d2b4cd SG |
153 | compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; |
154 | reg = <0x53f90000 0x4000>; | |
155 | interrupts = <56 57>; | |
156 | gpio-controller; | |
157 | #gpio-cells = <2>; | |
158 | interrupt-controller; | |
159 | #interrupt-cells = <1>; | |
160 | }; | |
161 | ||
162 | wdog@53f98000 { /* WDOG1 */ | |
163 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; | |
164 | reg = <0x53f98000 0x4000>; | |
165 | interrupts = <58>; | |
166 | status = "disabled"; | |
167 | }; | |
168 | ||
169 | wdog@53f9c000 { /* WDOG2 */ | |
170 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; | |
171 | reg = <0x53f9c000 0x4000>; | |
172 | interrupts = <59>; | |
173 | status = "disabled"; | |
174 | }; | |
175 | ||
0c456cfa | 176 | uart1: serial@53fbc000 { |
73d2b4cd SG |
177 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
178 | reg = <0x53fbc000 0x4000>; | |
179 | interrupts = <31>; | |
180 | status = "disabled"; | |
181 | }; | |
182 | ||
0c456cfa | 183 | uart2: serial@53fc0000 { |
73d2b4cd SG |
184 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
185 | reg = <0x53fc0000 0x4000>; | |
186 | interrupts = <32>; | |
187 | status = "disabled"; | |
188 | }; | |
189 | ||
4d191868 | 190 | gpio5: gpio@53fdc000 { |
73d2b4cd SG |
191 | compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; |
192 | reg = <0x53fdc000 0x4000>; | |
193 | interrupts = <103 104>; | |
194 | gpio-controller; | |
195 | #gpio-cells = <2>; | |
196 | interrupt-controller; | |
197 | #interrupt-cells = <1>; | |
198 | }; | |
199 | ||
4d191868 | 200 | gpio6: gpio@53fe0000 { |
73d2b4cd SG |
201 | compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; |
202 | reg = <0x53fe0000 0x4000>; | |
203 | interrupts = <105 106>; | |
204 | gpio-controller; | |
205 | #gpio-cells = <2>; | |
206 | interrupt-controller; | |
207 | #interrupt-cells = <1>; | |
208 | }; | |
209 | ||
4d191868 | 210 | gpio7: gpio@53fe4000 { |
73d2b4cd SG |
211 | compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; |
212 | reg = <0x53fe4000 0x4000>; | |
213 | interrupts = <107 108>; | |
214 | gpio-controller; | |
215 | #gpio-cells = <2>; | |
216 | interrupt-controller; | |
217 | #interrupt-cells = <1>; | |
218 | }; | |
219 | ||
220 | i2c@53fec000 { /* I2C3 */ | |
221 | #address-cells = <1>; | |
222 | #size-cells = <0>; | |
223 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; | |
224 | reg = <0x53fec000 0x4000>; | |
225 | interrupts = <64>; | |
226 | status = "disabled"; | |
227 | }; | |
228 | ||
0c456cfa | 229 | uart4: serial@53ff0000 { |
73d2b4cd SG |
230 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
231 | reg = <0x53ff0000 0x4000>; | |
232 | interrupts = <13>; | |
233 | status = "disabled"; | |
234 | }; | |
235 | }; | |
236 | ||
237 | aips@60000000 { /* AIPS2 */ | |
238 | compatible = "fsl,aips-bus", "simple-bus"; | |
239 | #address-cells = <1>; | |
240 | #size-cells = <1>; | |
241 | reg = <0x60000000 0x10000000>; | |
242 | ranges; | |
243 | ||
0c456cfa | 244 | uart5: serial@63f90000 { |
73d2b4cd SG |
245 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
246 | reg = <0x63f90000 0x4000>; | |
247 | interrupts = <86>; | |
248 | status = "disabled"; | |
249 | }; | |
250 | ||
251 | ecspi@63fac000 { /* ECSPI2 */ | |
252 | #address-cells = <1>; | |
253 | #size-cells = <0>; | |
254 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
255 | reg = <0x63fac000 0x4000>; | |
256 | interrupts = <37>; | |
257 | status = "disabled"; | |
258 | }; | |
259 | ||
260 | sdma@63fb0000 { | |
261 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; | |
262 | reg = <0x63fb0000 0x4000>; | |
263 | interrupts = <6>; | |
264 | }; | |
265 | ||
266 | cspi@63fc0000 { | |
267 | #address-cells = <1>; | |
268 | #size-cells = <0>; | |
269 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
270 | reg = <0x63fc0000 0x4000>; | |
271 | interrupts = <38>; | |
272 | status = "disabled"; | |
273 | }; | |
274 | ||
275 | i2c@63fc4000 { /* I2C2 */ | |
276 | #address-cells = <1>; | |
277 | #size-cells = <0>; | |
278 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; | |
279 | reg = <0x63fc4000 0x4000>; | |
280 | interrupts = <63>; | |
281 | status = "disabled"; | |
282 | }; | |
283 | ||
284 | i2c@63fc8000 { /* I2C1 */ | |
285 | #address-cells = <1>; | |
286 | #size-cells = <0>; | |
287 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; | |
288 | reg = <0x63fc8000 0x4000>; | |
289 | interrupts = <62>; | |
290 | status = "disabled"; | |
291 | }; | |
292 | ||
0c456cfa | 293 | ethernet@63fec000 { |
73d2b4cd SG |
294 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
295 | reg = <0x63fec000 0x4000>; | |
296 | interrupts = <87>; | |
297 | status = "disabled"; | |
298 | }; | |
299 | }; | |
300 | }; | |
301 | }; |