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ARM: dts: imx6q-gw5xxx: remove dead 'crtcs' property
[linux-2.6-block.git] / arch / arm / boot / dts / imx53.dtsi
CommitLineData
73d2b4cd
SG		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
36dffd8f 13#include "skeleton.dtsi"
e1641531 14#include "imx53-pinfunc.h"
564695dd 15#include <dt-bindings/clock/imx5-clock.h>
4e05a7af
DC		 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
73d2b4cd
SG		 18
19/ {
20 aliases {
5230f8fe
SG		 21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 gpio6 = &gpio7;
c60dc1d1
PZ		 28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
c63d06de
SH		 31 mmc0 = &esdhc1;
32 mmc1 = &esdhc2;
33 mmc2 = &esdhc3;
34 mmc3 = &esdhc4;
cf4e577e
SH		 35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 serial4 = &uart5;
40 spi0 = &ecspi1;
41 spi1 = &ecspi2;
42 spi2 = &cspi;
73d2b4cd
SG		 43 };
44
070bd7e4
FE		 45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a8";
51 reg = <0x0>;
52 };
53 };
54
e05c8c9a
PZ		 55 display-subsystem {
56 compatible = "fsl,imx-display-subsystem";
57 ports = <&ipu_di0>, <&ipu_di1>;
58 };
59
73d2b4cd
SG		 60 tzic: tz-interrupt-controller@0fffc000 {
61 compatible = "fsl,imx53-tzic", "fsl,tzic";
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 reg = <0x0fffc000 0x4000>;
65 };
66
67 clocks {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 ckil {
72 compatible = "fsl,imx-ckil", "fixed-clock";
73 clock-frequency = <32768>;
74 };
75
76 ckih1 {
77 compatible = "fsl,imx-ckih1", "fixed-clock";
78 clock-frequency = <22579200>;
79 };
80
81 ckih2 {
82 compatible = "fsl,imx-ckih2", "fixed-clock";
83 clock-frequency = <0>;
84 };
85
86 osc {
87 compatible = "fsl,imx-osc", "fixed-clock";
88 clock-frequency = <24000000>;
89 };
90 };
91
92 soc {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 compatible = "simple-bus";
96 interrupt-parent = <&tzic>;
97 ranges;
98
7affee43
MV		 99 sata: sata@10000000 {
100 compatible = "fsl,imx53-ahci";
101 reg = <0x10000000 0x1000>;
102 interrupts = <28>;
103 clocks = <&clks IMX5_CLK_SATA_GATE>,
104 <&clks IMX5_CLK_SATA_REF>,
105 <&clks IMX5_CLK_AHB>;
106 clock-names = "sata_gate", "sata_ref", "ahb";
107 status = "disabled";
108 };
109
abed9a6b 110 ipu: ipu@18000000 {
e05c8c9a
PZ		 111 #address-cells = <1>;
112 #size-cells = <0>;
abed9a6b
SH		 113 compatible = "fsl,imx53-ipu";
114 reg = <0x18000000 0x080000000>;
115 interrupts = <11 10>;
564695dd
LS		 116 clocks = <&clks IMX5_CLK_IPU_GATE>,
117 <&clks IMX5_CLK_IPU_DI0_GATE>,
118 <&clks IMX5_CLK_IPU_DI1_GATE>;
4438a6a1 119 clock-names = "bus", "di0", "di1";
8d84c374 120 resets = <&src 2>;
e05c8c9a
PZ		 121
122 ipu_di0: port@2 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <2>;
126
127 ipu_di0_disp0: endpoint@0 {
128 reg = <0>;
129 };
130
131 ipu_di0_lvds0: endpoint@1 {
132 reg = <1>;
133 remote-endpoint = <&lvds0_in>;
134 };
135 };
136
137 ipu_di1: port@3 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 reg = <3>;
141
142 ipu_di1_disp1: endpoint@0 {
143 reg = <0>;
144 };
145
146 ipu_di1_lvds1: endpoint@1 {
147 reg = <1>;
148 remote-endpoint = <&lvds1_in>;
149 };
150
151 ipu_di1_tve: endpoint@2 {
152 reg = <2>;
153 remote-endpoint = <&tve_in>;
154 };
155 };
abed9a6b
SH		 156 };
157
73d2b4cd
SG		 158 aips@50000000 { /* AIPS1 */
159 compatible = "fsl,aips-bus", "simple-bus";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 reg = <0x50000000 0x10000000>;
163 ranges;
164
165 spba@50000000 {
166 compatible = "fsl,spba-bus", "simple-bus";
167 #address-cells = <1>;
168 #size-cells = <1>;
169 reg = <0x50000000 0x40000>;
170 ranges;
171
7b7d6727 172 esdhc1: esdhc@50004000 {
73d2b4cd
SG		 173 compatible = "fsl,imx53-esdhc";
174 reg = <0x50004000 0x4000>;
175 interrupts = <1>;
564695dd
LS		 176 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
177 <&clks IMX5_CLK_DUMMY>,
178 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
f40f38d1 179 clock-names = "ipg", "ahb", "per";
c104b6a2 180 bus-width = <4>;
73d2b4cd
SG		 181 status = "disabled";
182 };
183
7b7d6727 184 esdhc2: esdhc@50008000 {
73d2b4cd
SG		 185 compatible = "fsl,imx53-esdhc";
186 reg = <0x50008000 0x4000>;
187 interrupts = <2>;
564695dd
LS		 188 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
189 <&clks IMX5_CLK_DUMMY>,
190 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
f40f38d1 191 clock-names = "ipg", "ahb", "per";
c104b6a2 192 bus-width = <4>;
73d2b4cd
SG		 193 status = "disabled";
194 };
195
0c456cfa 196 uart3: serial@5000c000 {
73d2b4cd
SG		 197 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
198 reg = <0x5000c000 0x4000>;
199 interrupts = <33>;
564695dd
LS		 200 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
201 <&clks IMX5_CLK_UART3_PER_GATE>;
f40f38d1 202 clock-names = "ipg", "per";
73d2b4cd
SG		 203 status = "disabled";
204 };
205
7b7d6727 206 ecspi1: ecspi@50010000 {
73d2b4cd
SG		 207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
210 reg = <0x50010000 0x4000>;
211 interrupts = <36>;
564695dd
LS		 212 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
213 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
f40f38d1 214 clock-names = "ipg", "per";
73d2b4cd
SG		 215 status = "disabled";
216 };
217
ffc505c0 218 ssi2: ssi@50014000 {
28f93d0b
MP		 219 compatible = "fsl,imx53-ssi",
220 "fsl,imx51-ssi",
221 "fsl,imx21-ssi";
ffc505c0
SG		 222 reg = <0x50014000 0x4000>;
223 interrupts = <30>;
564695dd 224 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
5da826ab
SG		 225 dmas = <&sdma 24 1 0>,
226 <&sdma 25 1 0>;
227 dma-names = "rx", "tx";
ffc505c0
SG		 228 fsl,fifo-depth = <15>;
229 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
230 status = "disabled";
231 };
232
7b7d6727 233 esdhc3: esdhc@50020000 {
73d2b4cd
SG		 234 compatible = "fsl,imx53-esdhc";
235 reg = <0x50020000 0x4000>;
236 interrupts = <3>;
564695dd
LS		 237 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
238 <&clks IMX5_CLK_DUMMY>,
239 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
f40f38d1 240 clock-names = "ipg", "ahb", "per";
c104b6a2 241 bus-width = <4>;
73d2b4cd
SG		 242 status = "disabled";
243 };
244
7b7d6727 245 esdhc4: esdhc@50024000 {
73d2b4cd
SG		 246 compatible = "fsl,imx53-esdhc";
247 reg = <0x50024000 0x4000>;
248 interrupts = <4>;
564695dd
LS		 249 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
250 <&clks IMX5_CLK_DUMMY>,
251 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
f40f38d1 252 clock-names = "ipg", "ahb", "per";
c104b6a2 253 bus-width = <4>;
73d2b4cd
SG		 254 status = "disabled";
255 };
256 };
257
a79025c4
MG		 258 usbphy0: usbphy@0 {
259 compatible = "usb-nop-xceiv";
564695dd 260 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
a79025c4
MG		 261 clock-names = "main_clk";
262 status = "okay";
263 };
264
265 usbphy1: usbphy@1 {
266 compatible = "usb-nop-xceiv";
564695dd 267 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
a79025c4
MG		 268 clock-names = "main_clk";
269 status = "okay";
270 };
271
7b7d6727 272 usbotg: usb@53f80000 {
212d0b83
MG		 273 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
274 reg = <0x53f80000 0x0200>;
275 interrupts = <18>;
564695dd 276 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 277 fsl,usbmisc = <&usbmisc 0>;
a79025c4 278 fsl,usbphy = <&usbphy0>;
212d0b83
MG		 279 status = "disabled";
280 };
281
7b7d6727 282 usbh1: usb@53f80200 {
212d0b83
MG		 283 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
284 reg = <0x53f80200 0x0200>;
285 interrupts = <14>;
564695dd 286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 287 fsl,usbmisc = <&usbmisc 1>;
a79025c4 288 fsl,usbphy = <&usbphy1>;
212d0b83
MG		 289 status = "disabled";
290 };
291
7b7d6727 292 usbh2: usb@53f80400 {
212d0b83
MG		 293 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
294 reg = <0x53f80400 0x0200>;
295 interrupts = <16>;
564695dd 296 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 297 fsl,usbmisc = <&usbmisc 2>;
212d0b83
MG		 298 status = "disabled";
299 };
300
7b7d6727 301 usbh3: usb@53f80600 {
212d0b83
MG		 302 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
303 reg = <0x53f80600 0x0200>;
304 interrupts = <17>;
564695dd 305 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021 306 fsl,usbmisc = <&usbmisc 3>;
212d0b83
MG		 307 status = "disabled";
308 };
309
a5735021
MG		 310 usbmisc: usbmisc@53f80800 {
311 #index-cells = <1>;
312 compatible = "fsl,imx53-usbmisc";
313 reg = <0x53f80800 0x200>;
564695dd 314 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
a5735021
MG		 315 };
316
4d191868 317 gpio1: gpio@53f84000 {
aeb27748 318 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 319 reg = <0x53f84000 0x4000>;
320 interrupts = <50 51>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 interrupt-controller;
88cde8b7 324 #interrupt-cells = <2>;
73d2b4cd
SG		 325 };
326
4d191868 327 gpio2: gpio@53f88000 {
aeb27748 328 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 329 reg = <0x53f88000 0x4000>;
330 interrupts = <52 53>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
88cde8b7 334 #interrupt-cells = <2>;
73d2b4cd
SG		 335 };
336
4d191868 337 gpio3: gpio@53f8c000 {
aeb27748 338 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 339 reg = <0x53f8c000 0x4000>;
340 interrupts = <54 55>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
88cde8b7 344 #interrupt-cells = <2>;
73d2b4cd
SG		 345 };
346
4d191868 347 gpio4: gpio@53f90000 {
aeb27748 348 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 349 reg = <0x53f90000 0x4000>;
350 interrupts = <56 57>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
88cde8b7 354 #interrupt-cells = <2>;
73d2b4cd
SG		 355 };
356
675e4d03
RL		 357 kpp: kpp@53f94000 {
358 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
359 reg = <0x53f94000 0x4000>;
360 interrupts = <60>;
564695dd 361 clocks = <&clks IMX5_CLK_DUMMY>;
675e4d03
RL		 362 status = "disabled";
363 };
364
7b7d6727 365 wdog1: wdog@53f98000 {
73d2b4cd
SG		 366 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
367 reg = <0x53f98000 0x4000>;
368 interrupts = <58>;
564695dd 369 clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd
SG		 370 };
371
7b7d6727 372 wdog2: wdog@53f9c000 {
73d2b4cd
SG		 373 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
374 reg = <0x53f9c000 0x4000>;
375 interrupts = <59>;
564695dd 376 clocks = <&clks IMX5_CLK_DUMMY>;
73d2b4cd
SG		 377 status = "disabled";
378 };
379
cc8aae9b
SH		 380 gpt: timer@53fa0000 {
381 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
382 reg = <0x53fa0000 0x4000>;
383 interrupts = <39>;
564695dd
LS		 384 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
385 <&clks IMX5_CLK_GPT_HF_GATE>;
cc8aae9b
SH		 386 clock-names = "ipg", "per";
387 };
388
7b7d6727 389 iomuxc: iomuxc@53fa8000 {
5be03a7b
SG		 390 compatible = "fsl,imx53-iomuxc";
391 reg = <0x53fa8000 0x4000>;
5be03a7b
SG		 392 };
393
5af9f143
PZ		 394 gpr: iomuxc-gpr@53fa8000 {
395 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
396 reg = <0x53fa8000 0xc>;
397 };
398
420714aa
PZ		 399 ldb: ldb@53fa8008 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 compatible = "fsl,imx53-ldb";
403 reg = <0x53fa8008 0x4>;
404 gpr = <&gpr>;
564695dd
LS		 405 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
406 <&clks IMX5_CLK_LDB_DI1_SEL>,
407 <&clks IMX5_CLK_IPU_DI0_SEL>,
408 <&clks IMX5_CLK_IPU_DI1_SEL>,
409 <&clks IMX5_CLK_LDB_DI0_GATE>,
410 <&clks IMX5_CLK_LDB_DI1_GATE>;
420714aa
PZ		 411 clock-names = "di0_pll", "di1_pll",
412 "di0_sel", "di1_sel",
413 "di0", "di1";
414 status = "disabled";
415
416 lvds-channel@0 {
417 reg = <0>;
420714aa 418 status = "disabled";
e05c8c9a
PZ		 419
420 port {
421 lvds0_in: endpoint {
422 remote-endpoint = <&ipu_di0_lvds0>;
423 };
424 };
420714aa
PZ		 425 };
426
427 lvds-channel@1 {
428 reg = <1>;
420714aa 429 status = "disabled";
e05c8c9a
PZ		 430
431 port {
432 lvds1_in: endpoint {
433 remote-endpoint = <&ipu_di0_lvds0>;
434 };
435 };
420714aa
PZ		 436 };
437 };
438
9ae90afa
SH		 439 pwm1: pwm@53fb4000 {
440 #pwm-cells = <2>;
441 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
442 reg = <0x53fb4000 0x4000>;
564695dd
LS		 443 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
444 <&clks IMX5_CLK_PWM1_HF_GATE>;
9ae90afa
SH		 445 clock-names = "ipg", "per";
446 interrupts = <61>;
447 };
448
449 pwm2: pwm@53fb8000 {
450 #pwm-cells = <2>;
451 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
452 reg = <0x53fb8000 0x4000>;
564695dd
LS		 453 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
454 <&clks IMX5_CLK_PWM2_HF_GATE>;
9ae90afa
SH		 455 clock-names = "ipg", "per";
456 interrupts = <94>;
457 };
458
0c456cfa 459 uart1: serial@53fbc000 {
73d2b4cd
SG		 460 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
461 reg = <0x53fbc000 0x4000>;
462 interrupts = <31>;
564695dd
LS		 463 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
464 <&clks IMX5_CLK_UART1_PER_GATE>;
f40f38d1 465 clock-names = "ipg", "per";
73d2b4cd
SG		 466 status = "disabled";
467 };
468
0c456cfa 469 uart2: serial@53fc0000 {
73d2b4cd
SG		 470 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
471 reg = <0x53fc0000 0x4000>;
472 interrupts = <32>;
564695dd
LS		 473 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
474 <&clks IMX5_CLK_UART2_PER_GATE>;
f40f38d1 475 clock-names = "ipg", "per";
73d2b4cd
SG		 476 status = "disabled";
477 };
478
a9d1f924
ST		 479 can1: can@53fc8000 {
480 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
481 reg = <0x53fc8000 0x4000>;
482 interrupts = <82>;
564695dd
LS		 483 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
484 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
f40f38d1 485 clock-names = "ipg", "per";
a9d1f924
ST		 486 status = "disabled";
487 };
488
489 can2: can@53fcc000 {
490 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
491 reg = <0x53fcc000 0x4000>;
492 interrupts = <83>;
564695dd
LS		 493 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
494 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
f40f38d1 495 clock-names = "ipg", "per";
a9d1f924
ST		 496 status = "disabled";
497 };
498
8d84c374
PZ		 499 src: src@53fd0000 {
500 compatible = "fsl,imx53-src", "fsl,imx51-src";
501 reg = <0x53fd0000 0x4000>;
502 #reset-cells = <1>;
503 };
504
f40f38d1
FE		 505 clks: ccm@53fd4000{
506 compatible = "fsl,imx53-ccm";
507 reg = <0x53fd4000 0x4000>;
508 interrupts = <0 71 0x04 0 72 0x04>;
509 #clock-cells = <1>;
510 };
511
4d191868 512 gpio5: gpio@53fdc000 {
aeb27748 513 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 514 reg = <0x53fdc000 0x4000>;
515 interrupts = <103 104>;
516 gpio-controller;
517 #gpio-cells = <2>;
518 interrupt-controller;
88cde8b7 519 #interrupt-cells = <2>;
73d2b4cd
SG		 520 };
521
4d191868 522 gpio6: gpio@53fe0000 {
aeb27748 523 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 524 reg = <0x53fe0000 0x4000>;
525 interrupts = <105 106>;
526 gpio-controller;
527 #gpio-cells = <2>;
528 interrupt-controller;
88cde8b7 529 #interrupt-cells = <2>;
73d2b4cd
SG		 530 };
531
4d191868 532 gpio7: gpio@53fe4000 {
aeb27748 533 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd
SG		 534 reg = <0x53fe4000 0x4000>;
535 interrupts = <107 108>;
536 gpio-controller;
537 #gpio-cells = <2>;
538 interrupt-controller;
88cde8b7 539 #interrupt-cells = <2>;
73d2b4cd
SG		 540 };
541
7b7d6727 542 i2c3: i2c@53fec000 {
73d2b4cd
SG		 543 #address-cells = <1>;
544 #size-cells = <0>;
5bdfba29 545 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 546 reg = <0x53fec000 0x4000>;
547 interrupts = <64>;
564695dd 548 clocks = <&clks IMX5_CLK_I2C3_GATE>;
73d2b4cd
SG		 549 status = "disabled";
550 };
551
0c456cfa 552 uart4: serial@53ff0000 {
73d2b4cd
SG		 553 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
554 reg = <0x53ff0000 0x4000>;
555 interrupts = <13>;
564695dd
LS		 556 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
557 <&clks IMX5_CLK_UART4_PER_GATE>;
f40f38d1 558 clock-names = "ipg", "per";
73d2b4cd
SG		 559 status = "disabled";
560 };
561 };
562
563 aips@60000000 { /* AIPS2 */
564 compatible = "fsl,aips-bus", "simple-bus";
565 #address-cells = <1>;
566 #size-cells = <1>;
567 reg = <0x60000000 0x10000000>;
568 ranges;
569
4f3b2a41
SH		 570 iim: iim@63f98000 {
571 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
572 reg = <0x63f98000 0x4000>;
573 interrupts = <69>;
564695dd 574 clocks = <&clks IMX5_CLK_IIM_GATE>;
4f3b2a41
SH		 575 };
576
0c456cfa 577 uart5: serial@63f90000 {
73d2b4cd
SG		 578 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
579 reg = <0x63f90000 0x4000>;
580 interrupts = <86>;
564695dd
LS		 581 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
582 <&clks IMX5_CLK_UART5_PER_GATE>;
f40f38d1 583 clock-names = "ipg", "per";
73d2b4cd
SG		 584 status = "disabled";
585 };
586
a82b7b9c
MF		 587 owire: owire@63fa4000 {
588 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
589 reg = <0x63fa4000 0x4000>;
564695dd 590 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
a82b7b9c
MF		 591 status = "disabled";
592 };
593
7b7d6727 594 ecspi2: ecspi@63fac000 {
73d2b4cd
SG		 595 #address-cells = <1>;
596 #size-cells = <0>;
597 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
598 reg = <0x63fac000 0x4000>;
599 interrupts = <37>;
564695dd
LS		 600 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
601 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
f40f38d1 602 clock-names = "ipg", "per";
73d2b4cd
SG		 603 status = "disabled";
604 };
605
7b7d6727 606 sdma: sdma@63fb0000 {
73d2b4cd
SG		 607 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
608 reg = <0x63fb0000 0x4000>;
609 interrupts = <6>;
564695dd
LS		 610 clocks = <&clks IMX5_CLK_SDMA_GATE>,
611 <&clks IMX5_CLK_SDMA_GATE>;
f40f38d1 612 clock-names = "ipg", "ahb";
fb72bb21 613 #dma-cells = <3>;
7e4f0365 614 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
73d2b4cd
SG		 615 };
616
7b7d6727 617 cspi: cspi@63fc0000 {
73d2b4cd
SG		 618 #address-cells = <1>;
619 #size-cells = <0>;
620 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
621 reg = <0x63fc0000 0x4000>;
622 interrupts = <38>;
564695dd
LS		 623 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
624 <&clks IMX5_CLK_CSPI_IPG_GATE>;
f40f38d1 625 clock-names = "ipg", "per";
73d2b4cd
SG		 626 status = "disabled";
627 };
628
7b7d6727 629 i2c2: i2c@63fc4000 {
73d2b4cd
SG		 630 #address-cells = <1>;
631 #size-cells = <0>;
5bdfba29 632 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 633 reg = <0x63fc4000 0x4000>;
634 interrupts = <63>;
564695dd 635 clocks = <&clks IMX5_CLK_I2C2_GATE>;
73d2b4cd
SG		 636 status = "disabled";
637 };
638
7b7d6727 639 i2c1: i2c@63fc8000 {
73d2b4cd
SG		 640 #address-cells = <1>;
641 #size-cells = <0>;
5bdfba29 642 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd
SG		 643 reg = <0x63fc8000 0x4000>;
644 interrupts = <62>;
564695dd 645 clocks = <&clks IMX5_CLK_I2C1_GATE>;
73d2b4cd
SG		 646 status = "disabled";
647 };
648
ffc505c0 649 ssi1: ssi@63fcc000 {
28f93d0b
MP		 650 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
651 "fsl,imx21-ssi";
ffc505c0
SG		 652 reg = <0x63fcc000 0x4000>;
653 interrupts = <29>;
564695dd 654 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
5da826ab
SG		 655 dmas = <&sdma 28 0 0>,
656 <&sdma 29 0 0>;
657 dma-names = "rx", "tx";
ffc505c0
SG		 658 fsl,fifo-depth = <15>;
659 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
660 status = "disabled";
661 };
662
7b7d6727 663 audmux: audmux@63fd0000 {
ffc505c0
SG		 664 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
665 reg = <0x63fd0000 0x4000>;
666 status = "disabled";
667 };
668
7b7d6727 669 nfc: nand@63fdb000 {
75453a08
SH		 670 compatible = "fsl,imx53-nand";
671 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
672 interrupts = <8>;
564695dd 673 clocks = <&clks IMX5_CLK_NFC_GATE>;
75453a08
SH		 674 status = "disabled";
675 };
676
ffc505c0 677 ssi3: ssi@63fe8000 {
28f93d0b
MP		 678 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
679 "fsl,imx21-ssi";
ffc505c0
SG		 680 reg = <0x63fe8000 0x4000>;
681 interrupts = <96>;
564695dd 682 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
5da826ab
SG		 683 dmas = <&sdma 46 0 0>,
684 <&sdma 47 0 0>;
685 dma-names = "rx", "tx";
ffc505c0
SG		 686 fsl,fifo-depth = <15>;
687 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
688 status = "disabled";
689 };
690
7b7d6727 691 fec: ethernet@63fec000 {
73d2b4cd
SG		 692 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
693 reg = <0x63fec000 0x4000>;
694 interrupts = <87>;
564695dd
LS		 695 clocks = <&clks IMX5_CLK_FEC_GATE>,
696 <&clks IMX5_CLK_FEC_GATE>,
697 <&clks IMX5_CLK_FEC_GATE>;
f40f38d1 698 clock-names = "ipg", "ahb", "ptp";
73d2b4cd
SG		 699 status = "disabled";
700 };
19194c2b
PZ		 701
702 tve: tve@63ff0000 {
703 compatible = "fsl,imx53-tve";
704 reg = <0x63ff0000 0x1000>;
705 interrupts = <92>;
564695dd
LS		 706 clocks = <&clks IMX5_CLK_TVE_GATE>,
707 <&clks IMX5_CLK_IPU_DI1_SEL>;
19194c2b 708 clock-names = "tve", "di_sel";
19194c2b 709 status = "disabled";
e05c8c9a
PZ		 710
711 port {
712 tve_in: endpoint {
713 remote-endpoint = <&ipu_di1_tve>;
714 };
715 };
19194c2b 716 };
fbf970f6
FE		 717
718 vpu: vpu@63ff4000 {
719 compatible = "fsl,imx53-vpu";
720 reg = <0x63ff4000 0x1000>;
721 interrupts = <9>;
564695dd
LS		 722 clocks = <&clks IMX5_CLK_VPU_GATE>,
723 <&clks IMX5_CLK_VPU_GATE>;
fbf970f6
FE		 724 clock-names = "per", "ahb";
725 iram = <&ocram>;
726 status = "disabled";
727 };
73d2b4cd 728 };
481fbe13
PZ		 729
730 ocram: sram@f8000000 {
731 compatible = "mmio-sram";
732 reg = <0xf8000000 0x20000>;
564695dd 733 clocks = <&clks IMX5_CLK_OCRAM>;
481fbe13 734 };
73d2b4cd
SG		 735 };
736};
Linux 6.x block layer and io_uring tree(s)