projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 73d2b4cd SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 36dffd8f | 13 | #include "skeleton.dtsi" |
| e1641531 | 14 | #include "imx53-pinfunc.h" |
| 564695dd | 15 | #include <dt-bindings/clock/imx5-clock.h> |
| 4e05a7af DC |
16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/input/input.h> | |
| 34adba71 | 18 | #include <dt-bindings/interrupt-controller/irq.h> |
| 73d2b4cd SG |
19 | |
| 20 | / { | |
| 21 | aliases { | |
| 22970070 | 22 | ethernet0 = &fec; |
| 5230f8fe SG |
23 | gpio0 = &gpio1; |
| 24 | gpio1 = &gpio2; | |
| 25 | gpio2 = &gpio3; | |
| 26 | gpio3 = &gpio4; | |
| 27 | gpio4 = &gpio5; | |
| 28 | gpio5 = &gpio6; | |
| 29 | gpio6 = &gpio7; | |
| c60dc1d1 PZ |
30 | i2c0 = &i2c1; |
| 31 | i2c1 = &i2c2; | |
| 32 | i2c2 = &i2c3; | |
| c63d06de SH |
33 | mmc0 = &esdhc1; |
| 34 | mmc1 = &esdhc2; | |
| 35 | mmc2 = &esdhc3; | |
| 36 | mmc3 = &esdhc4; | |
| cf4e577e SH |
37 | serial0 = &uart1; |
| 38 | serial1 = &uart2; | |
| 39 | serial2 = &uart3; | |
| 40 | serial3 = &uart4; | |
| 41 | serial4 = &uart5; | |
| 42 | spi0 = &ecspi1; | |
| 43 | spi1 = &ecspi2; | |
| 44 | spi2 = &cspi; | |
| 73d2b4cd SG |
45 | }; |
| 46 | ||
| 070bd7e4 FE |
47 | cpus { |
| 48 | #address-cells = <1>; | |
| 49 | #size-cells = <0>; | |
| 791f4166 | 50 | cpu0: cpu@0 { |
| 070bd7e4 FE |
51 | device_type = "cpu"; |
| 52 | compatible = "arm,cortex-a8"; | |
| 53 | reg = <0x0>; | |
| 791f4166 LS |
54 | clocks = <&clks IMX5_CLK_ARM>; |
| 55 | clock-latency = <61036>; | |
| 56 | voltage-tolerance = <5>; | |
| 57 | operating-points = < | |
| 58 | /* kHz */ | |
| 59 | 166666 850000 | |
| 60 | 400000 900000 | |
| 61 | 800000 1050000 | |
| 62 | 1000000 1200000 | |
| 63 | 1200000 1300000 | |
| 64 | >; | |
| 070bd7e4 FE |
65 | }; |
| 66 | }; | |
| 67 | ||
| e05c8c9a PZ |
68 | display-subsystem { |
| 69 | compatible = "fsl,imx-display-subsystem"; | |
| 70 | ports = <&ipu_di0>, <&ipu_di1>; | |
| 71 | }; | |
| 72 | ||
| 73d2b4cd SG |
73 | tzic: tz-interrupt-controller@0fffc000 { |
| 74 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
| 75 | interrupt-controller; | |
| 76 | #interrupt-cells = <1>; | |
| 77 | reg = <0x0fffc000 0x4000>; | |
| 78 | }; | |
| 79 | ||
| 80 | clocks { | |
| 81 | #address-cells = <1>; | |
| 82 | #size-cells = <0>; | |
| 83 | ||
| 84 | ckil { | |
| 85 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 86 | #clock-cells = <0>; |
| 73d2b4cd SG |
87 | clock-frequency = <32768>; |
| 88 | }; | |
| 89 | ||
| 90 | ckih1 { | |
| 91 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 92 | #clock-cells = <0>; |
| 73d2b4cd SG |
93 | clock-frequency = <22579200>; |
| 94 | }; | |
| 95 | ||
| 96 | ckih2 { | |
| 97 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 4b2b4043 | 98 | #clock-cells = <0>; |
| 73d2b4cd SG |
99 | clock-frequency = <0>; |
| 100 | }; | |
| 101 | ||
| 102 | osc { | |
| 103 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 104 | #clock-cells = <0>; |
| 73d2b4cd SG |
105 | clock-frequency = <24000000>; |
| 106 | }; | |
| 107 | }; | |
| 108 | ||
| 109 | soc { | |
| 110 | #address-cells = <1>; | |
| 111 | #size-cells = <1>; | |
| 112 | compatible = "simple-bus"; | |
| 113 | interrupt-parent = <&tzic>; | |
| 114 | ranges; | |
| 115 | ||
| 7affee43 MV |
116 | sata: sata@10000000 { |
| 117 | compatible = "fsl,imx53-ahci"; | |
| 118 | reg = <0x10000000 0x1000>; | |
| 119 | interrupts = <28>; | |
| 120 | clocks = <&clks IMX5_CLK_SATA_GATE>, | |
| 121 | <&clks IMX5_CLK_SATA_REF>, | |
| 122 | <&clks IMX5_CLK_AHB>; | |
| 02578153 | 123 | clock-names = "sata", "sata_ref", "ahb"; |
| 7affee43 MV |
124 | status = "disabled"; |
| 125 | }; | |
| 126 | ||
| abed9a6b | 127 | ipu: ipu@18000000 { |
| e05c8c9a PZ |
128 | #address-cells = <1>; |
| 129 | #size-cells = <0>; | |
| abed9a6b | 130 | compatible = "fsl,imx53-ipu"; |
| 6d66da89 | 131 | reg = <0x18000000 0x08000000>; |
| abed9a6b | 132 | interrupts = <11 10>; |
| 564695dd LS |
133 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 134 | <&clks IMX5_CLK_IPU_DI0_GATE>, | |
| 135 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
| 4438a6a1 | 136 | clock-names = "bus", "di0", "di1"; |
| 8d84c374 | 137 | resets = <&src 2>; |
| e05c8c9a PZ |
138 | |
| 139 | ipu_di0: port@2 { | |
| 140 | #address-cells = <1>; | |
| 141 | #size-cells = <0>; | |
| 142 | reg = <2>; | |
| 143 | ||
| 144 | ipu_di0_disp0: endpoint@0 { | |
| 145 | reg = <0>; | |
| 146 | }; | |
| 147 | ||
| 148 | ipu_di0_lvds0: endpoint@1 { | |
| 149 | reg = <1>; | |
| 150 | remote-endpoint = <&lvds0_in>; | |
| 151 | }; | |
| 152 | }; | |
| 153 | ||
| 154 | ipu_di1: port@3 { | |
| 155 | #address-cells = <1>; | |
| 156 | #size-cells = <0>; | |
| 157 | reg = <3>; | |
| 158 | ||
| 159 | ipu_di1_disp1: endpoint@0 { | |
| 160 | reg = <0>; | |
| 161 | }; | |
| 162 | ||
| 163 | ipu_di1_lvds1: endpoint@1 { | |
| 164 | reg = <1>; | |
| 165 | remote-endpoint = <&lvds1_in>; | |
| 166 | }; | |
| 167 | ||
| 168 | ipu_di1_tve: endpoint@2 { | |
| 169 | reg = <2>; | |
| 170 | remote-endpoint = <&tve_in>; | |
| 171 | }; | |
| 172 | }; | |
| abed9a6b SH |
173 | }; |
| 174 | ||
| 73d2b4cd SG |
175 | aips@50000000 { /* AIPS1 */ |
| 176 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 177 | #address-cells = <1>; | |
| 178 | #size-cells = <1>; | |
| 179 | reg = <0x50000000 0x10000000>; | |
| 180 | ranges; | |
| 181 | ||
| 182 | spba@50000000 { | |
| 183 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 184 | #address-cells = <1>; | |
| 185 | #size-cells = <1>; | |
| 186 | reg = <0x50000000 0x40000>; | |
| 187 | ranges; | |
| 188 | ||
| 7b7d6727 | 189 | esdhc1: esdhc@50004000 { |
| 73d2b4cd SG |
190 | compatible = "fsl,imx53-esdhc"; |
| 191 | reg = <0x50004000 0x4000>; | |
| 192 | interrupts = <1>; | |
| 564695dd LS |
193 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 194 | <&clks IMX5_CLK_DUMMY>, | |
| 195 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
| f40f38d1 | 196 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 197 | bus-width = <4>; |
| 73d2b4cd SG |
198 | status = "disabled"; |
| 199 | }; | |
| 200 | ||
| 7b7d6727 | 201 | esdhc2: esdhc@50008000 { |
| 73d2b4cd SG |
202 | compatible = "fsl,imx53-esdhc"; |
| 203 | reg = <0x50008000 0x4000>; | |
| 204 | interrupts = <2>; | |
| 564695dd LS |
205 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 206 | <&clks IMX5_CLK_DUMMY>, | |
| 207 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
| f40f38d1 | 208 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 209 | bus-width = <4>; |
| 73d2b4cd SG |
210 | status = "disabled"; |
| 211 | }; | |
| 212 | ||
| 0c456cfa | 213 | uart3: serial@5000c000 { |
| 73d2b4cd SG |
214 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 215 | reg = <0x5000c000 0x4000>; | |
| 216 | interrupts = <33>; | |
| 564695dd LS |
217 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 218 | <&clks IMX5_CLK_UART3_PER_GATE>; | |
| f40f38d1 | 219 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
220 | status = "disabled"; |
| 221 | }; | |
| 222 | ||
| 7b7d6727 | 223 | ecspi1: ecspi@50010000 { |
| 73d2b4cd SG |
224 | #address-cells = <1>; |
| 225 | #size-cells = <0>; | |
| 226 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 227 | reg = <0x50010000 0x4000>; | |
| 228 | interrupts = <36>; | |
| 564695dd LS |
229 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 230 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | |
| f40f38d1 | 231 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
232 | status = "disabled"; |
| 233 | }; | |
| 234 | ||
| ffc505c0 | 235 | ssi2: ssi@50014000 { |
| 6ff7f51e | 236 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
237 | compatible = "fsl,imx53-ssi", |
| 238 | "fsl,imx51-ssi", | |
| 239 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
240 | reg = <0x50014000 0x4000>; |
| 241 | interrupts = <30>; | |
| 685570ab FE |
242 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, |
| 243 | <&clks IMX5_CLK_SSI2_ROOT_GATE>; | |
| 244 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
245 | dmas = <&sdma 24 1 0>, |
| 246 | <&sdma 25 1 0>; | |
| 247 | dma-names = "rx", "tx"; | |
| ffc505c0 | 248 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
249 | status = "disabled"; |
| 250 | }; | |
| 251 | ||
| 7b7d6727 | 252 | esdhc3: esdhc@50020000 { |
| 73d2b4cd SG |
253 | compatible = "fsl,imx53-esdhc"; |
| 254 | reg = <0x50020000 0x4000>; | |
| 255 | interrupts = <3>; | |
| 564695dd LS |
256 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 257 | <&clks IMX5_CLK_DUMMY>, | |
| 258 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
| f40f38d1 | 259 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 260 | bus-width = <4>; |
| 73d2b4cd SG |
261 | status = "disabled"; |
| 262 | }; | |
| 263 | ||
| 7b7d6727 | 264 | esdhc4: esdhc@50024000 { |
| 73d2b4cd SG |
265 | compatible = "fsl,imx53-esdhc"; |
| 266 | reg = <0x50024000 0x4000>; | |
| 267 | interrupts = <4>; | |
| 564695dd LS |
268 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 269 | <&clks IMX5_CLK_DUMMY>, | |
| 270 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
| f40f38d1 | 271 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 272 | bus-width = <4>; |
| 73d2b4cd SG |
273 | status = "disabled"; |
| 274 | }; | |
| 275 | }; | |
| 276 | ||
| ac08281e ST |
277 | aipstz1: bridge@53f00000 { |
| 278 | compatible = "fsl,imx53-aipstz"; | |
| 279 | reg = <0x53f00000 0x60>; | |
| 280 | }; | |
| 281 | ||
| a79025c4 MG |
282 | usbphy0: usbphy@0 { |
| 283 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 284 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
| a79025c4 MG |
285 | clock-names = "main_clk"; |
| 286 | status = "okay"; | |
| 287 | }; | |
| 288 | ||
| 289 | usbphy1: usbphy@1 { | |
| 290 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 291 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
| a79025c4 MG |
292 | clock-names = "main_clk"; |
| 293 | status = "okay"; | |
| 294 | }; | |
| 295 | ||
| 7b7d6727 | 296 | usbotg: usb@53f80000 { |
| 212d0b83 MG |
297 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 298 | reg = <0x53f80000 0x0200>; | |
| 299 | interrupts = <18>; | |
| 564695dd | 300 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 301 | fsl,usbmisc = <&usbmisc 0>; |
| a79025c4 | 302 | fsl,usbphy = <&usbphy0>; |
| 212d0b83 MG |
303 | status = "disabled"; |
| 304 | }; | |
| 305 | ||
| 7b7d6727 | 306 | usbh1: usb@53f80200 { |
| 212d0b83 MG |
307 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 308 | reg = <0x53f80200 0x0200>; | |
| 309 | interrupts = <14>; | |
| 564695dd | 310 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 311 | fsl,usbmisc = <&usbmisc 1>; |
| a79025c4 | 312 | fsl,usbphy = <&usbphy1>; |
| 3ec481ed | 313 | dr_mode = "host"; |
| 212d0b83 MG |
314 | status = "disabled"; |
| 315 | }; | |
| 316 | ||
| 7b7d6727 | 317 | usbh2: usb@53f80400 { |
| 212d0b83 MG |
318 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 319 | reg = <0x53f80400 0x0200>; | |
| 320 | interrupts = <16>; | |
| 564695dd | 321 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 322 | fsl,usbmisc = <&usbmisc 2>; |
| 3ec481ed | 323 | dr_mode = "host"; |
| 212d0b83 MG |
324 | status = "disabled"; |
| 325 | }; | |
| 326 | ||
| 7b7d6727 | 327 | usbh3: usb@53f80600 { |
| 212d0b83 MG |
328 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 329 | reg = <0x53f80600 0x0200>; | |
| 330 | interrupts = <17>; | |
| 564695dd | 331 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 332 | fsl,usbmisc = <&usbmisc 3>; |
| 3ec481ed | 333 | dr_mode = "host"; |
| 212d0b83 MG |
334 | status = "disabled"; |
| 335 | }; | |
| 336 | ||
| a5735021 MG |
337 | usbmisc: usbmisc@53f80800 { |
| 338 | #index-cells = <1>; | |
| 339 | compatible = "fsl,imx53-usbmisc"; | |
| 340 | reg = <0x53f80800 0x200>; | |
| 564695dd | 341 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 MG |
342 | }; |
| 343 | ||
| 4d191868 | 344 | gpio1: gpio@53f84000 { |
| aeb27748 | 345 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
346 | reg = <0x53f84000 0x4000>; |
| 347 | interrupts = <50 51>; | |
| 348 | gpio-controller; | |
| 349 | #gpio-cells = <2>; | |
| 350 | interrupt-controller; | |
| 88cde8b7 | 351 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
352 | }; |
| 353 | ||
| 4d191868 | 354 | gpio2: gpio@53f88000 { |
| aeb27748 | 355 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
356 | reg = <0x53f88000 0x4000>; |
| 357 | interrupts = <52 53>; | |
| 358 | gpio-controller; | |
| 359 | #gpio-cells = <2>; | |
| 360 | interrupt-controller; | |
| 88cde8b7 | 361 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
362 | }; |
| 363 | ||
| 4d191868 | 364 | gpio3: gpio@53f8c000 { |
| aeb27748 | 365 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
366 | reg = <0x53f8c000 0x4000>; |
| 367 | interrupts = <54 55>; | |
| 368 | gpio-controller; | |
| 369 | #gpio-cells = <2>; | |
| 370 | interrupt-controller; | |
| 88cde8b7 | 371 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
372 | }; |
| 373 | ||
| 4d191868 | 374 | gpio4: gpio@53f90000 { |
| aeb27748 | 375 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
376 | reg = <0x53f90000 0x4000>; |
| 377 | interrupts = <56 57>; | |
| 378 | gpio-controller; | |
| 379 | #gpio-cells = <2>; | |
| 380 | interrupt-controller; | |
| 88cde8b7 | 381 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
382 | }; |
| 383 | ||
| 675e4d03 RL |
384 | kpp: kpp@53f94000 { |
| 385 | compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; | |
| 386 | reg = <0x53f94000 0x4000>; | |
| 387 | interrupts = <60>; | |
| 564695dd | 388 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 675e4d03 RL |
389 | status = "disabled"; |
| 390 | }; | |
| 391 | ||
| 7b7d6727 | 392 | wdog1: wdog@53f98000 { |
| 73d2b4cd SG |
393 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 394 | reg = <0x53f98000 0x4000>; | |
| 395 | interrupts = <58>; | |
| 564695dd | 396 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
397 | }; |
| 398 | ||
| 7b7d6727 | 399 | wdog2: wdog@53f9c000 { |
| 73d2b4cd SG |
400 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 401 | reg = <0x53f9c000 0x4000>; | |
| 402 | interrupts = <59>; | |
| 564695dd | 403 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
404 | status = "disabled"; |
| 405 | }; | |
| 406 | ||
| cc8aae9b SH |
407 | gpt: timer@53fa0000 { |
| 408 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
| 409 | reg = <0x53fa0000 0x4000>; | |
| 410 | interrupts = <39>; | |
| 564695dd LS |
411 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 412 | <&clks IMX5_CLK_GPT_HF_GATE>; | |
| cc8aae9b SH |
413 | clock-names = "ipg", "per"; |
| 414 | }; | |
| 415 | ||
| 7b7d6727 | 416 | iomuxc: iomuxc@53fa8000 { |
| 5be03a7b SG |
417 | compatible = "fsl,imx53-iomuxc"; |
| 418 | reg = <0x53fa8000 0x4000>; | |
| 5be03a7b SG |
419 | }; |
| 420 | ||
| 5af9f143 PZ |
421 | gpr: iomuxc-gpr@53fa8000 { |
| 422 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
| 423 | reg = <0x53fa8000 0xc>; | |
| 424 | }; | |
| 425 | ||
| 420714aa PZ |
426 | ldb: ldb@53fa8008 { |
| 427 | #address-cells = <1>; | |
| 428 | #size-cells = <0>; | |
| 429 | compatible = "fsl,imx53-ldb"; | |
| 430 | reg = <0x53fa8008 0x4>; | |
| 431 | gpr = <&gpr>; | |
| 564695dd LS |
432 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
| 433 | <&clks IMX5_CLK_LDB_DI1_SEL>, | |
| 434 | <&clks IMX5_CLK_IPU_DI0_SEL>, | |
| 435 | <&clks IMX5_CLK_IPU_DI1_SEL>, | |
| 436 | <&clks IMX5_CLK_LDB_DI0_GATE>, | |
| 437 | <&clks IMX5_CLK_LDB_DI1_GATE>; | |
| 420714aa PZ |
438 | clock-names = "di0_pll", "di1_pll", |
| 439 | "di0_sel", "di1_sel", | |
| 440 | "di0", "di1"; | |
| 441 | status = "disabled"; | |
| 442 | ||
| 443 | lvds-channel@0 { | |
| 1b134c9c MN |
444 | #address-cells = <1>; |
| 445 | #size-cells = <0>; | |
| 420714aa | 446 | reg = <0>; |
| 420714aa | 447 | status = "disabled"; |
| e05c8c9a | 448 | |
| 1b134c9c MN |
449 | port@0 { |
| 450 | reg = <0>; | |
| 451 | ||
| e05c8c9a PZ |
452 | lvds0_in: endpoint { |
| 453 | remote-endpoint = <&ipu_di0_lvds0>; | |
| 454 | }; | |
| 455 | }; | |
| 420714aa PZ |
456 | }; |
| 457 | ||
| 458 | lvds-channel@1 { | |
| 1b134c9c MN |
459 | #address-cells = <1>; |
| 460 | #size-cells = <0>; | |
| 420714aa | 461 | reg = <1>; |
| 420714aa | 462 | status = "disabled"; |
| e05c8c9a | 463 | |
| 1b134c9c MN |
464 | port@1 { |
| 465 | reg = <1>; | |
| 466 | ||
| e05c8c9a | 467 | lvds1_in: endpoint { |
| fa1746ae | 468 | remote-endpoint = <&ipu_di1_lvds1>; |
| e05c8c9a PZ |
469 | }; |
| 470 | }; | |
| 420714aa PZ |
471 | }; |
| 472 | }; | |
| 473 | ||
| 9ae90afa SH |
474 | pwm1: pwm@53fb4000 { |
| 475 | #pwm-cells = <2>; | |
| 476 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 477 | reg = <0x53fb4000 0x4000>; | |
| 564695dd LS |
478 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 479 | <&clks IMX5_CLK_PWM1_HF_GATE>; | |
| 9ae90afa SH |
480 | clock-names = "ipg", "per"; |
| 481 | interrupts = <61>; | |
| 482 | }; | |
| 483 | ||
| 484 | pwm2: pwm@53fb8000 { | |
| 485 | #pwm-cells = <2>; | |
| 486 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 487 | reg = <0x53fb8000 0x4000>; | |
| 564695dd LS |
488 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 489 | <&clks IMX5_CLK_PWM2_HF_GATE>; | |
| 9ae90afa SH |
490 | clock-names = "ipg", "per"; |
| 491 | interrupts = <94>; | |
| 492 | }; | |
| 493 | ||
| 0c456cfa | 494 | uart1: serial@53fbc000 { |
| 73d2b4cd SG |
495 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 496 | reg = <0x53fbc000 0x4000>; | |
| 497 | interrupts = <31>; | |
| 564695dd LS |
498 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 499 | <&clks IMX5_CLK_UART1_PER_GATE>; | |
| f40f38d1 | 500 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
501 | status = "disabled"; |
| 502 | }; | |
| 503 | ||
| 0c456cfa | 504 | uart2: serial@53fc0000 { |
| 73d2b4cd SG |
505 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 506 | reg = <0x53fc0000 0x4000>; | |
| 507 | interrupts = <32>; | |
| 564695dd LS |
508 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 509 | <&clks IMX5_CLK_UART2_PER_GATE>; | |
| f40f38d1 | 510 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
511 | status = "disabled"; |
| 512 | }; | |
| 513 | ||
| a9d1f924 ST |
514 | can1: can@53fc8000 { |
| 515 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 516 | reg = <0x53fc8000 0x4000>; | |
| 517 | interrupts = <82>; | |
| 564695dd LS |
518 | clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
| 519 | <&clks IMX5_CLK_CAN1_SERIAL_GATE>; | |
| f40f38d1 | 520 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
521 | status = "disabled"; |
| 522 | }; | |
| 523 | ||
| 524 | can2: can@53fcc000 { | |
| 525 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 526 | reg = <0x53fcc000 0x4000>; | |
| 527 | interrupts = <83>; | |
| 564695dd LS |
528 | clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
| 529 | <&clks IMX5_CLK_CAN2_SERIAL_GATE>; | |
| f40f38d1 | 530 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
531 | status = "disabled"; |
| 532 | }; | |
| 533 | ||
| 8d84c374 PZ |
534 | src: src@53fd0000 { |
| 535 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
| 536 | reg = <0x53fd0000 0x4000>; | |
| 537 | #reset-cells = <1>; | |
| 538 | }; | |
| 539 | ||
| f40f38d1 FE |
540 | clks: ccm@53fd4000{ |
| 541 | compatible = "fsl,imx53-ccm"; | |
| 542 | reg = <0x53fd4000 0x4000>; | |
| 543 | interrupts = <0 71 0x04 0 72 0x04>; | |
| 544 | #clock-cells = <1>; | |
| 545 | }; | |
| 546 | ||
| 4d191868 | 547 | gpio5: gpio@53fdc000 { |
| aeb27748 | 548 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
549 | reg = <0x53fdc000 0x4000>; |
| 550 | interrupts = <103 104>; | |
| 551 | gpio-controller; | |
| 552 | #gpio-cells = <2>; | |
| 553 | interrupt-controller; | |
| 88cde8b7 | 554 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
555 | }; |
| 556 | ||
| 4d191868 | 557 | gpio6: gpio@53fe0000 { |
| aeb27748 | 558 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
559 | reg = <0x53fe0000 0x4000>; |
| 560 | interrupts = <105 106>; | |
| 561 | gpio-controller; | |
| 562 | #gpio-cells = <2>; | |
| 563 | interrupt-controller; | |
| 88cde8b7 | 564 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
565 | }; |
| 566 | ||
| 4d191868 | 567 | gpio7: gpio@53fe4000 { |
| aeb27748 | 568 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
569 | reg = <0x53fe4000 0x4000>; |
| 570 | interrupts = <107 108>; | |
| 571 | gpio-controller; | |
| 572 | #gpio-cells = <2>; | |
| 573 | interrupt-controller; | |
| 88cde8b7 | 574 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
575 | }; |
| 576 | ||
| 7b7d6727 | 577 | i2c3: i2c@53fec000 { |
| 73d2b4cd SG |
578 | #address-cells = <1>; |
| 579 | #size-cells = <0>; | |
| 5bdfba29 | 580 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
581 | reg = <0x53fec000 0x4000>; |
| 582 | interrupts = <64>; | |
| 564695dd | 583 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
| 73d2b4cd SG |
584 | status = "disabled"; |
| 585 | }; | |
| 586 | ||
| 0c456cfa | 587 | uart4: serial@53ff0000 { |
| 73d2b4cd SG |
588 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 589 | reg = <0x53ff0000 0x4000>; | |
| 590 | interrupts = <13>; | |
| 564695dd LS |
591 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
| 592 | <&clks IMX5_CLK_UART4_PER_GATE>; | |
| f40f38d1 | 593 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
594 | status = "disabled"; |
| 595 | }; | |
| 596 | }; | |
| 597 | ||
| 598 | aips@60000000 { /* AIPS2 */ | |
| 599 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 600 | #address-cells = <1>; | |
| 601 | #size-cells = <1>; | |
| 602 | reg = <0x60000000 0x10000000>; | |
| 603 | ranges; | |
| 604 | ||
| ac08281e ST |
605 | aipstz2: bridge@63f00000 { |
| 606 | compatible = "fsl,imx53-aipstz"; | |
| 607 | reg = <0x63f00000 0x60>; | |
| 608 | }; | |
| 609 | ||
| 4f3b2a41 SH |
610 | iim: iim@63f98000 { |
| 611 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | |
| 612 | reg = <0x63f98000 0x4000>; | |
| 613 | interrupts = <69>; | |
| 564695dd | 614 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 4f3b2a41 SH |
615 | }; |
| 616 | ||
| 0c456cfa | 617 | uart5: serial@63f90000 { |
| 73d2b4cd SG |
618 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 619 | reg = <0x63f90000 0x4000>; | |
| 620 | interrupts = <86>; | |
| 564695dd LS |
621 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
| 622 | <&clks IMX5_CLK_UART5_PER_GATE>; | |
| f40f38d1 | 623 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
624 | status = "disabled"; |
| 625 | }; | |
| 626 | ||
| a82b7b9c MF |
627 | owire: owire@63fa4000 { |
| 628 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
| 629 | reg = <0x63fa4000 0x4000>; | |
| 564695dd | 630 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| a82b7b9c MF |
631 | status = "disabled"; |
| 632 | }; | |
| 633 | ||
| 7b7d6727 | 634 | ecspi2: ecspi@63fac000 { |
| 73d2b4cd SG |
635 | #address-cells = <1>; |
| 636 | #size-cells = <0>; | |
| 637 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 638 | reg = <0x63fac000 0x4000>; | |
| 639 | interrupts = <37>; | |
| 564695dd LS |
640 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 641 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | |
| f40f38d1 | 642 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
643 | status = "disabled"; |
| 644 | }; | |
| 645 | ||
| 7b7d6727 | 646 | sdma: sdma@63fb0000 { |
| 73d2b4cd SG |
647 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 648 | reg = <0x63fb0000 0x4000>; | |
| 649 | interrupts = <6>; | |
| 564695dd LS |
650 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 651 | <&clks IMX5_CLK_SDMA_GATE>; | |
| f40f38d1 | 652 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 653 | #dma-cells = <3>; |
| 7e4f0365 | 654 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| 73d2b4cd SG |
655 | }; |
| 656 | ||
| 7b7d6727 | 657 | cspi: cspi@63fc0000 { |
| 73d2b4cd SG |
658 | #address-cells = <1>; |
| 659 | #size-cells = <0>; | |
| 660 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
| 661 | reg = <0x63fc0000 0x4000>; | |
| 662 | interrupts = <38>; | |
| 564695dd LS |
663 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 664 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | |
| f40f38d1 | 665 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
666 | status = "disabled"; |
| 667 | }; | |
| 668 | ||
| 7b7d6727 | 669 | i2c2: i2c@63fc4000 { |
| 73d2b4cd SG |
670 | #address-cells = <1>; |
| 671 | #size-cells = <0>; | |
| 5bdfba29 | 672 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
673 | reg = <0x63fc4000 0x4000>; |
| 674 | interrupts = <63>; | |
| 564695dd | 675 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 73d2b4cd SG |
676 | status = "disabled"; |
| 677 | }; | |
| 678 | ||
| 7b7d6727 | 679 | i2c1: i2c@63fc8000 { |
| 73d2b4cd SG |
680 | #address-cells = <1>; |
| 681 | #size-cells = <0>; | |
| 5bdfba29 | 682 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
683 | reg = <0x63fc8000 0x4000>; |
| 684 | interrupts = <62>; | |
| 564695dd | 685 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 73d2b4cd SG |
686 | status = "disabled"; |
| 687 | }; | |
| 688 | ||
| ffc505c0 | 689 | ssi1: ssi@63fcc000 { |
| 6ff7f51e | 690 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
691 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 692 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
693 | reg = <0x63fcc000 0x4000>; |
| 694 | interrupts = <29>; | |
| 685570ab FE |
695 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, |
| 696 | <&clks IMX5_CLK_SSI1_ROOT_GATE>; | |
| 697 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
698 | dmas = <&sdma 28 0 0>, |
| 699 | <&sdma 29 0 0>; | |
| 700 | dma-names = "rx", "tx"; | |
| ffc505c0 | 701 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
702 | status = "disabled"; |
| 703 | }; | |
| 704 | ||
| 7b7d6727 | 705 | audmux: audmux@63fd0000 { |
| ffc505c0 SG |
706 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 707 | reg = <0x63fd0000 0x4000>; | |
| 708 | status = "disabled"; | |
| 709 | }; | |
| 710 | ||
| 7b7d6727 | 711 | nfc: nand@63fdb000 { |
| 75453a08 SH |
712 | compatible = "fsl,imx53-nand"; |
| 713 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
| 714 | interrupts = <8>; | |
| 564695dd | 715 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 75453a08 SH |
716 | status = "disabled"; |
| 717 | }; | |
| 718 | ||
| ffc505c0 | 719 | ssi3: ssi@63fe8000 { |
| 6ff7f51e | 720 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
721 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 722 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
723 | reg = <0x63fe8000 0x4000>; |
| 724 | interrupts = <96>; | |
| 685570ab FE |
725 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, |
| 726 | <&clks IMX5_CLK_SSI3_ROOT_GATE>; | |
| 727 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
728 | dmas = <&sdma 46 0 0>, |
| 729 | <&sdma 47 0 0>; | |
| 730 | dma-names = "rx", "tx"; | |
| ffc505c0 | 731 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
732 | status = "disabled"; |
| 733 | }; | |
| 734 | ||
| 7b7d6727 | 735 | fec: ethernet@63fec000 { |
| 73d2b4cd SG |
736 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 737 | reg = <0x63fec000 0x4000>; | |
| 738 | interrupts = <87>; | |
| 564695dd LS |
739 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 740 | <&clks IMX5_CLK_FEC_GATE>, | |
| 741 | <&clks IMX5_CLK_FEC_GATE>; | |
| f40f38d1 | 742 | clock-names = "ipg", "ahb", "ptp"; |
| 73d2b4cd SG |
743 | status = "disabled"; |
| 744 | }; | |
| 19194c2b PZ |
745 | |
| 746 | tve: tve@63ff0000 { | |
| 747 | compatible = "fsl,imx53-tve"; | |
| 748 | reg = <0x63ff0000 0x1000>; | |
| 749 | interrupts = <92>; | |
| 564695dd LS |
750 | clocks = <&clks IMX5_CLK_TVE_GATE>, |
| 751 | <&clks IMX5_CLK_IPU_DI1_SEL>; | |
| 19194c2b | 752 | clock-names = "tve", "di_sel"; |
| 19194c2b | 753 | status = "disabled"; |
| e05c8c9a PZ |
754 | |
| 755 | port { | |
| 756 | tve_in: endpoint { | |
| 757 | remote-endpoint = <&ipu_di1_tve>; | |
| 758 | }; | |
| 759 | }; | |
| 19194c2b | 760 | }; |
| fbf970f6 FE |
761 | |
| 762 | vpu: vpu@63ff4000 { | |
| 71946619 | 763 | compatible = "fsl,imx53-vpu", "cnm,coda7541"; |
| fbf970f6 FE |
764 | reg = <0x63ff4000 0x1000>; |
| 765 | interrupts = <9>; | |
| fa97d2f7 | 766 | clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, |
| 564695dd | 767 | <&clks IMX5_CLK_VPU_GATE>; |
| fbf970f6 | 768 | clock-names = "per", "ahb"; |
| b1e2e546 | 769 | resets = <&src 1>; |
| fbf970f6 | 770 | iram = <&ocram>; |
| fbf970f6 | 771 | }; |
| 60811cc2 ST |
772 | |
| 773 | sahara: crypto@63ff8000 { | |
| 774 | compatible = "fsl,imx53-sahara"; | |
| 775 | reg = <0x63ff8000 0x4000>; | |
| 776 | interrupts = <19 20>; | |
| 777 | clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, | |
| 778 | <&clks IMX5_CLK_SAHARA_IPG_GATE>; | |
| 779 | clock-names = "ipg", "ahb"; | |
| 780 | }; | |
| 73d2b4cd | 781 | }; |
| 481fbe13 PZ |
782 | |
| 783 | ocram: sram@f8000000 { | |
| 784 | compatible = "mmio-sram"; | |
| 785 | reg = <0xf8000000 0x20000>; | |
| 564695dd | 786 | clocks = <&clks IMX5_CLK_OCRAM>; |
| 481fbe13 | 787 | }; |
| 49bdf58e ST |
788 | |
| 789 | pmu { | |
| 790 | compatible = "arm,cortex-a8-pmu"; | |
| 791 | interrupts = <77>; | |
| 792 | }; | |
| 73d2b4cd SG |
793 | }; |
| 794 | }; |