Commit | Line | Data |
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9daaf31a SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
e1641531 | 13 | #include "imx51-pinfunc.h" |
ff65d4ca | 14 | #include <dt-bindings/clock/imx5-clock.h> |
bdb3eec7 | 15 | #include <dt-bindings/gpio/gpio.h> |
72d86d26 AS |
16 | #include <dt-bindings/input/input.h> |
17 | #include <dt-bindings/interrupt-controller/irq.h> | |
9daaf31a SG |
18 | |
19 | / { | |
7f107887 FE |
20 | #address-cells = <1>; |
21 | #size-cells = <1>; | |
a971c554 FE |
22 | /* |
23 | * The decompressor and also some bootloaders rely on a | |
24 | * pre-existing /chosen node to be available to insert the | |
25 | * command line and merge other ATAGS info. | |
26 | * Also for U-Boot there must be a pre-existing /memory node. | |
27 | */ | |
28 | chosen {}; | |
29 | memory { device_type = "memory"; reg = <0 0>; }; | |
7f107887 | 30 | |
9daaf31a | 31 | aliases { |
22970070 | 32 | ethernet0 = &fec; |
5230f8fe SG |
33 | gpio0 = &gpio1; |
34 | gpio1 = &gpio2; | |
35 | gpio2 = &gpio3; | |
36 | gpio3 = &gpio4; | |
e3b73c68 SH |
37 | i2c0 = &i2c1; |
38 | i2c1 = &i2c2; | |
f742c22c SH |
39 | mmc0 = &esdhc1; |
40 | mmc1 = &esdhc2; | |
41 | mmc2 = &esdhc3; | |
42 | mmc3 = &esdhc4; | |
e3b73c68 SH |
43 | serial0 = &uart1; |
44 | serial1 = &uart2; | |
45 | serial2 = &uart3; | |
46 | spi0 = &ecspi1; | |
47 | spi1 = &ecspi2; | |
48 | spi2 = &cspi; | |
9daaf31a SG |
49 | }; |
50 | ||
51 | tzic: tz-interrupt-controller@e0000000 { | |
52 | compatible = "fsl,imx51-tzic", "fsl,tzic"; | |
53 | interrupt-controller; | |
54 | #interrupt-cells = <1>; | |
55 | reg = <0xe0000000 0x4000>; | |
56 | }; | |
57 | ||
58 | clocks { | |
59 | #address-cells = <1>; | |
60 | #size-cells = <0>; | |
61 | ||
62 | ckil { | |
63 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
4b2b4043 | 64 | #clock-cells = <0>; |
9daaf31a SG |
65 | clock-frequency = <32768>; |
66 | }; | |
67 | ||
68 | ckih1 { | |
69 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
4b2b4043 | 70 | #clock-cells = <0>; |
677e28b1 | 71 | clock-frequency = <0>; |
9daaf31a SG |
72 | }; |
73 | ||
74 | ckih2 { | |
75 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
4b2b4043 | 76 | #clock-cells = <0>; |
9daaf31a SG |
77 | clock-frequency = <0>; |
78 | }; | |
79 | ||
80 | osc { | |
81 | compatible = "fsl,imx-osc", "fixed-clock"; | |
4b2b4043 | 82 | #clock-cells = <0>; |
9daaf31a SG |
83 | clock-frequency = <24000000>; |
84 | }; | |
85 | }; | |
86 | ||
6f9d62d4 MP |
87 | cpus { |
88 | #address-cells = <1>; | |
89 | #size-cells = <0>; | |
6acde887 | 90 | cpu: cpu@0 { |
6f9d62d4 MP |
91 | device_type = "cpu"; |
92 | compatible = "arm,cortex-a8"; | |
93 | reg = <0>; | |
6acde887 | 94 | clock-latency = <62500>; |
ff65d4ca | 95 | clocks = <&clks IMX5_CLK_CPU_PODF>; |
6f9d62d4 MP |
96 | clock-names = "cpu"; |
97 | operating-points = < | |
6acde887 AS |
98 | 166000 1000000 |
99 | 600000 1050000 | |
100 | 800000 1100000 | |
6f9d62d4 | 101 | >; |
6acde887 | 102 | voltage-tolerance = <5>; |
6f9d62d4 MP |
103 | }; |
104 | }; | |
105 | ||
4e942303 AS |
106 | usbphy { |
107 | #address-cells = <1>; | |
108 | #size-cells = <0>; | |
109 | compatible = "simple-bus"; | |
110 | ||
111 | usbphy0: usbphy@0 { | |
112 | compatible = "usb-nop-xceiv"; | |
113 | reg = <0>; | |
114 | clocks = <&clks IMX5_CLK_USB_PHY_GATE>; | |
115 | clock-names = "main_clk"; | |
6f9d62d4 MP |
116 | }; |
117 | }; | |
118 | ||
de10e04e PZ |
119 | display-subsystem { |
120 | compatible = "fsl,imx-display-subsystem"; | |
121 | ports = <&ipu_di0>, <&ipu_di1>; | |
122 | }; | |
123 | ||
9daaf31a SG |
124 | soc { |
125 | #address-cells = <1>; | |
126 | #size-cells = <1>; | |
127 | compatible = "simple-bus"; | |
128 | interrupt-parent = <&tzic>; | |
129 | ranges; | |
130 | ||
da38ea33 AS |
131 | iram: iram@1ffe0000 { |
132 | compatible = "mmio-sram"; | |
133 | reg = <0x1ffe0000 0x20000>; | |
134 | }; | |
135 | ||
b5af6b10 | 136 | ipu: ipu@40000000 { |
de10e04e PZ |
137 | #address-cells = <1>; |
138 | #size-cells = <0>; | |
b5af6b10 SH |
139 | compatible = "fsl,imx51-ipu"; |
140 | reg = <0x40000000 0x20000000>; | |
141 | interrupts = <11 10>; | |
ff65d4ca | 142 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
46311707 JT |
143 | <&clks IMX5_CLK_IPU_DI0_GATE>, |
144 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
4438a6a1 | 145 | clock-names = "bus", "di0", "di1"; |
8d84c374 | 146 | resets = <&src 2>; |
de10e04e PZ |
147 | |
148 | ipu_di0: port@2 { | |
149 | reg = <2>; | |
150 | ||
f7059428 | 151 | ipu_di0_disp1: endpoint { |
de10e04e PZ |
152 | }; |
153 | }; | |
154 | ||
155 | ipu_di1: port@3 { | |
156 | reg = <3>; | |
157 | ||
f7059428 | 158 | ipu_di1_disp2: endpoint { |
de10e04e PZ |
159 | }; |
160 | }; | |
b5af6b10 SH |
161 | }; |
162 | ||
9daaf31a SG |
163 | aips@70000000 { /* AIPS1 */ |
164 | compatible = "fsl,aips-bus", "simple-bus"; | |
165 | #address-cells = <1>; | |
166 | #size-cells = <1>; | |
167 | reg = <0x70000000 0x10000000>; | |
168 | ranges; | |
169 | ||
170 | spba@70000000 { | |
171 | compatible = "fsl,spba-bus", "simple-bus"; | |
172 | #address-cells = <1>; | |
173 | #size-cells = <1>; | |
174 | reg = <0x70000000 0x40000>; | |
175 | ranges; | |
176 | ||
7b7d6727 | 177 | esdhc1: esdhc@70004000 { |
9daaf31a SG |
178 | compatible = "fsl,imx51-esdhc"; |
179 | reg = <0x70004000 0x4000>; | |
180 | interrupts = <1>; | |
ff65d4ca | 181 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
46311707 JT |
182 | <&clks IMX5_CLK_DUMMY>, |
183 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
f40f38d1 | 184 | clock-names = "ipg", "ahb", "per"; |
9daaf31a SG |
185 | status = "disabled"; |
186 | }; | |
187 | ||
7b7d6727 | 188 | esdhc2: esdhc@70008000 { |
9daaf31a SG |
189 | compatible = "fsl,imx51-esdhc"; |
190 | reg = <0x70008000 0x4000>; | |
191 | interrupts = <2>; | |
ff65d4ca | 192 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
46311707 JT |
193 | <&clks IMX5_CLK_DUMMY>, |
194 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
f40f38d1 | 195 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 196 | bus-width = <4>; |
9daaf31a SG |
197 | status = "disabled"; |
198 | }; | |
199 | ||
0c456cfa | 200 | uart3: serial@7000c000 { |
9daaf31a SG |
201 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
202 | reg = <0x7000c000 0x4000>; | |
203 | interrupts = <33>; | |
ff65d4ca | 204 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
46311707 | 205 | <&clks IMX5_CLK_UART3_PER_GATE>; |
f40f38d1 | 206 | clock-names = "ipg", "per"; |
9daaf31a SG |
207 | status = "disabled"; |
208 | }; | |
209 | ||
7b7d6727 | 210 | ecspi1: ecspi@70010000 { |
9daaf31a SG |
211 | #address-cells = <1>; |
212 | #size-cells = <0>; | |
213 | compatible = "fsl,imx51-ecspi"; | |
214 | reg = <0x70010000 0x4000>; | |
215 | interrupts = <36>; | |
ff65d4ca | 216 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
46311707 | 217 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; |
f40f38d1 | 218 | clock-names = "ipg", "per"; |
9daaf31a SG |
219 | status = "disabled"; |
220 | }; | |
221 | ||
a15d9f89 | 222 | ssi2: ssi@70014000 { |
6ff7f51e | 223 | #sound-dai-cells = <0>; |
a15d9f89 SG |
224 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
225 | reg = <0x70014000 0x4000>; | |
226 | interrupts = <30>; | |
53ec8748 FE |
227 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, |
228 | <&clks IMX5_CLK_SSI2_ROOT_GATE>; | |
229 | clock-names = "ipg", "baud"; | |
5da826ab SG |
230 | dmas = <&sdma 24 1 0>, |
231 | <&sdma 25 1 0>; | |
232 | dma-names = "rx", "tx"; | |
a15d9f89 | 233 | fsl,fifo-depth = <15>; |
a15d9f89 SG |
234 | status = "disabled"; |
235 | }; | |
236 | ||
7b7d6727 | 237 | esdhc3: esdhc@70020000 { |
9daaf31a SG |
238 | compatible = "fsl,imx51-esdhc"; |
239 | reg = <0x70020000 0x4000>; | |
240 | interrupts = <3>; | |
ff65d4ca | 241 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
46311707 JT |
242 | <&clks IMX5_CLK_DUMMY>, |
243 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
f40f38d1 | 244 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 245 | bus-width = <4>; |
9daaf31a SG |
246 | status = "disabled"; |
247 | }; | |
248 | ||
7b7d6727 | 249 | esdhc4: esdhc@70024000 { |
9daaf31a SG |
250 | compatible = "fsl,imx51-esdhc"; |
251 | reg = <0x70024000 0x4000>; | |
252 | interrupts = <4>; | |
ff65d4ca | 253 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
46311707 JT |
254 | <&clks IMX5_CLK_DUMMY>, |
255 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
f40f38d1 | 256 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 257 | bus-width = <4>; |
9daaf31a SG |
258 | status = "disabled"; |
259 | }; | |
260 | }; | |
261 | ||
7b7d6727 | 262 | usbotg: usb@73f80000 { |
212d0b83 MG |
263 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
264 | reg = <0x73f80000 0x0200>; | |
265 | interrupts = <18>; | |
ff65d4ca | 266 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 | 267 | fsl,usbmisc = <&usbmisc 0>; |
a79025c4 | 268 | fsl,usbphy = <&usbphy0>; |
212d0b83 MG |
269 | status = "disabled"; |
270 | }; | |
271 | ||
7b7d6727 | 272 | usbh1: usb@73f80200 { |
212d0b83 MG |
273 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
274 | reg = <0x73f80200 0x0200>; | |
275 | interrupts = <14>; | |
ff65d4ca | 276 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 | 277 | fsl,usbmisc = <&usbmisc 1>; |
3ec481ed | 278 | dr_mode = "host"; |
212d0b83 MG |
279 | status = "disabled"; |
280 | }; | |
281 | ||
7b7d6727 | 282 | usbh2: usb@73f80400 { |
212d0b83 MG |
283 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
284 | reg = <0x73f80400 0x0200>; | |
285 | interrupts = <16>; | |
ff65d4ca | 286 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 | 287 | fsl,usbmisc = <&usbmisc 2>; |
3ec481ed | 288 | dr_mode = "host"; |
212d0b83 MG |
289 | status = "disabled"; |
290 | }; | |
291 | ||
7b7d6727 | 292 | usbh3: usb@73f80600 { |
212d0b83 MG |
293 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
294 | reg = <0x73f80600 0x0200>; | |
295 | interrupts = <17>; | |
ff65d4ca | 296 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 | 297 | fsl,usbmisc = <&usbmisc 3>; |
3ec481ed | 298 | dr_mode = "host"; |
212d0b83 MG |
299 | status = "disabled"; |
300 | }; | |
301 | ||
a5735021 MG |
302 | usbmisc: usbmisc@73f80800 { |
303 | #index-cells = <1>; | |
304 | compatible = "fsl,imx51-usbmisc"; | |
305 | reg = <0x73f80800 0x200>; | |
ff65d4ca | 306 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 MG |
307 | }; |
308 | ||
4d191868 | 309 | gpio1: gpio@73f84000 { |
aeb27748 | 310 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
311 | reg = <0x73f84000 0x4000>; |
312 | interrupts = <50 51>; | |
313 | gpio-controller; | |
314 | #gpio-cells = <2>; | |
315 | interrupt-controller; | |
88cde8b7 | 316 | #interrupt-cells = <2>; |
9daaf31a SG |
317 | }; |
318 | ||
4d191868 | 319 | gpio2: gpio@73f88000 { |
aeb27748 | 320 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
321 | reg = <0x73f88000 0x4000>; |
322 | interrupts = <52 53>; | |
323 | gpio-controller; | |
324 | #gpio-cells = <2>; | |
325 | interrupt-controller; | |
88cde8b7 | 326 | #interrupt-cells = <2>; |
9daaf31a SG |
327 | }; |
328 | ||
4d191868 | 329 | gpio3: gpio@73f8c000 { |
aeb27748 | 330 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
331 | reg = <0x73f8c000 0x4000>; |
332 | interrupts = <54 55>; | |
333 | gpio-controller; | |
334 | #gpio-cells = <2>; | |
335 | interrupt-controller; | |
88cde8b7 | 336 | #interrupt-cells = <2>; |
9daaf31a SG |
337 | }; |
338 | ||
4d191868 | 339 | gpio4: gpio@73f90000 { |
aeb27748 | 340 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
341 | reg = <0x73f90000 0x4000>; |
342 | interrupts = <56 57>; | |
343 | gpio-controller; | |
344 | #gpio-cells = <2>; | |
345 | interrupt-controller; | |
88cde8b7 | 346 | #interrupt-cells = <2>; |
9daaf31a SG |
347 | }; |
348 | ||
6012555c LY |
349 | kpp: kpp@73f94000 { |
350 | compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; | |
351 | reg = <0x73f94000 0x4000>; | |
352 | interrupts = <60>; | |
ff65d4ca | 353 | clocks = <&clks IMX5_CLK_DUMMY>; |
6012555c LY |
354 | status = "disabled"; |
355 | }; | |
356 | ||
7b7d6727 | 357 | wdog1: wdog@73f98000 { |
9daaf31a SG |
358 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
359 | reg = <0x73f98000 0x4000>; | |
360 | interrupts = <58>; | |
ff65d4ca | 361 | clocks = <&clks IMX5_CLK_DUMMY>; |
9daaf31a SG |
362 | }; |
363 | ||
7b7d6727 | 364 | wdog2: wdog@73f9c000 { |
9daaf31a SG |
365 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
366 | reg = <0x73f9c000 0x4000>; | |
367 | interrupts = <59>; | |
ff65d4ca | 368 | clocks = <&clks IMX5_CLK_DUMMY>; |
9daaf31a SG |
369 | status = "disabled"; |
370 | }; | |
371 | ||
ed73c63a SH |
372 | gpt: timer@73fa0000 { |
373 | compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; | |
374 | reg = <0x73fa0000 0x4000>; | |
375 | interrupts = <39>; | |
ff65d4ca | 376 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
46311707 | 377 | <&clks IMX5_CLK_GPT_HF_GATE>; |
ed73c63a SH |
378 | clock-names = "ipg", "per"; |
379 | }; | |
380 | ||
7b7d6727 | 381 | iomuxc: iomuxc@73fa8000 { |
b72cf105 SG |
382 | compatible = "fsl,imx51-iomuxc"; |
383 | reg = <0x73fa8000 0x4000>; | |
b72cf105 SG |
384 | }; |
385 | ||
82a618da SH |
386 | pwm1: pwm@73fb4000 { |
387 | #pwm-cells = <2>; | |
388 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; | |
389 | reg = <0x73fb4000 0x4000>; | |
ff65d4ca | 390 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
46311707 | 391 | <&clks IMX5_CLK_PWM1_HF_GATE>; |
82a618da SH |
392 | clock-names = "ipg", "per"; |
393 | interrupts = <61>; | |
394 | }; | |
395 | ||
396 | pwm2: pwm@73fb8000 { | |
397 | #pwm-cells = <2>; | |
398 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; | |
399 | reg = <0x73fb8000 0x4000>; | |
ff65d4ca | 400 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
46311707 | 401 | <&clks IMX5_CLK_PWM2_HF_GATE>; |
82a618da SH |
402 | clock-names = "ipg", "per"; |
403 | interrupts = <94>; | |
404 | }; | |
405 | ||
0c456cfa | 406 | uart1: serial@73fbc000 { |
9daaf31a SG |
407 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
408 | reg = <0x73fbc000 0x4000>; | |
409 | interrupts = <31>; | |
ff65d4ca | 410 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
46311707 | 411 | <&clks IMX5_CLK_UART1_PER_GATE>; |
f40f38d1 | 412 | clock-names = "ipg", "per"; |
9daaf31a SG |
413 | status = "disabled"; |
414 | }; | |
415 | ||
0c456cfa | 416 | uart2: serial@73fc0000 { |
9daaf31a SG |
417 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
418 | reg = <0x73fc0000 0x4000>; | |
419 | interrupts = <32>; | |
ff65d4ca | 420 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
46311707 | 421 | <&clks IMX5_CLK_UART2_PER_GATE>; |
f40f38d1 | 422 | clock-names = "ipg", "per"; |
9daaf31a SG |
423 | status = "disabled"; |
424 | }; | |
f40f38d1 | 425 | |
8d84c374 PZ |
426 | src: src@73fd0000 { |
427 | compatible = "fsl,imx51-src"; | |
428 | reg = <0x73fd0000 0x4000>; | |
429 | #reset-cells = <1>; | |
430 | }; | |
431 | ||
f40f38d1 FE |
432 | clks: ccm@73fd4000{ |
433 | compatible = "fsl,imx51-ccm"; | |
434 | reg = <0x73fd4000 0x4000>; | |
435 | interrupts = <0 71 0x04 0 72 0x04>; | |
436 | #clock-cells = <1>; | |
437 | }; | |
9daaf31a SG |
438 | }; |
439 | ||
440 | aips@80000000 { /* AIPS2 */ | |
441 | compatible = "fsl,aips-bus", "simple-bus"; | |
442 | #address-cells = <1>; | |
443 | #size-cells = <1>; | |
444 | reg = <0x80000000 0x10000000>; | |
445 | ranges; | |
446 | ||
6510ea25 SH |
447 | iim: iim@83f98000 { |
448 | compatible = "fsl,imx51-iim", "fsl,imx27-iim"; | |
449 | reg = <0x83f98000 0x4000>; | |
450 | interrupts = <69>; | |
ff65d4ca | 451 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
6510ea25 SH |
452 | }; |
453 | ||
ad15f08c AS |
454 | owire: owire@83fa4000 { |
455 | compatible = "fsl,imx51-owire", "fsl,imx21-owire"; | |
456 | reg = <0x83fa4000 0x4000>; | |
457 | interrupts = <88>; | |
ff65d4ca | 458 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
ad15f08c AS |
459 | status = "disabled"; |
460 | }; | |
461 | ||
7b7d6727 | 462 | ecspi2: ecspi@83fac000 { |
9daaf31a SG |
463 | #address-cells = <1>; |
464 | #size-cells = <0>; | |
465 | compatible = "fsl,imx51-ecspi"; | |
466 | reg = <0x83fac000 0x4000>; | |
467 | interrupts = <37>; | |
ff65d4ca | 468 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
46311707 | 469 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; |
f40f38d1 | 470 | clock-names = "ipg", "per"; |
9daaf31a SG |
471 | status = "disabled"; |
472 | }; | |
473 | ||
7b7d6727 | 474 | sdma: sdma@83fb0000 { |
9daaf31a SG |
475 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
476 | reg = <0x83fb0000 0x4000>; | |
477 | interrupts = <6>; | |
ff65d4ca | 478 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
46311707 | 479 | <&clks IMX5_CLK_SDMA_GATE>; |
f40f38d1 | 480 | clock-names = "ipg", "ahb"; |
fb72bb21 | 481 | #dma-cells = <3>; |
7e4f0365 | 482 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; |
9daaf31a SG |
483 | }; |
484 | ||
7b7d6727 | 485 | cspi: cspi@83fc0000 { |
9daaf31a SG |
486 | #address-cells = <1>; |
487 | #size-cells = <0>; | |
488 | compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; | |
489 | reg = <0x83fc0000 0x4000>; | |
490 | interrupts = <38>; | |
ff65d4ca | 491 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
46311707 | 492 | <&clks IMX5_CLK_CSPI_IPG_GATE>; |
f40f38d1 | 493 | clock-names = "ipg", "per"; |
9daaf31a SG |
494 | status = "disabled"; |
495 | }; | |
496 | ||
7b7d6727 | 497 | i2c2: i2c@83fc4000 { |
9daaf31a SG |
498 | #address-cells = <1>; |
499 | #size-cells = <0>; | |
5bdfba29 | 500 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
9daaf31a SG |
501 | reg = <0x83fc4000 0x4000>; |
502 | interrupts = <63>; | |
ff65d4ca | 503 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
9daaf31a SG |
504 | status = "disabled"; |
505 | }; | |
506 | ||
7b7d6727 | 507 | i2c1: i2c@83fc8000 { |
9daaf31a SG |
508 | #address-cells = <1>; |
509 | #size-cells = <0>; | |
5bdfba29 | 510 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
9daaf31a SG |
511 | reg = <0x83fc8000 0x4000>; |
512 | interrupts = <62>; | |
ff65d4ca | 513 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
9daaf31a SG |
514 | status = "disabled"; |
515 | }; | |
516 | ||
a15d9f89 | 517 | ssi1: ssi@83fcc000 { |
6ff7f51e | 518 | #sound-dai-cells = <0>; |
a15d9f89 SG |
519 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
520 | reg = <0x83fcc000 0x4000>; | |
521 | interrupts = <29>; | |
53ec8748 FE |
522 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, |
523 | <&clks IMX5_CLK_SSI1_ROOT_GATE>; | |
524 | clock-names = "ipg", "baud"; | |
5da826ab SG |
525 | dmas = <&sdma 28 0 0>, |
526 | <&sdma 29 0 0>; | |
527 | dma-names = "rx", "tx"; | |
a15d9f89 | 528 | fsl,fifo-depth = <15>; |
a15d9f89 SG |
529 | status = "disabled"; |
530 | }; | |
531 | ||
7b7d6727 | 532 | audmux: audmux@83fd0000 { |
a15d9f89 SG |
533 | compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; |
534 | reg = <0x83fd0000 0x4000>; | |
ff65d4ca | 535 | clocks = <&clks IMX5_CLK_DUMMY>; |
e030df9d | 536 | clock-names = "audmux"; |
a15d9f89 SG |
537 | status = "disabled"; |
538 | }; | |
539 | ||
edd05286 AS |
540 | weim: weim@83fda000 { |
541 | #address-cells = <2>; | |
542 | #size-cells = <1>; | |
543 | compatible = "fsl,imx51-weim"; | |
544 | reg = <0x83fda000 0x1000>; | |
ff65d4ca | 545 | clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; |
edd05286 AS |
546 | ranges = < |
547 | 0 0 0xb0000000 0x08000000 | |
548 | 1 0 0xb8000000 0x08000000 | |
549 | 2 0 0xc0000000 0x08000000 | |
550 | 3 0 0xc8000000 0x04000000 | |
551 | 4 0 0xcc000000 0x02000000 | |
552 | 5 0 0xce000000 0x02000000 | |
553 | >; | |
554 | status = "disabled"; | |
555 | }; | |
556 | ||
7b7d6727 | 557 | nfc: nand@83fdb000 { |
f0e3f89e AS |
558 | #address-cells = <1>; |
559 | #size-cells = <1>; | |
75453a08 SH |
560 | compatible = "fsl,imx51-nand"; |
561 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; | |
562 | interrupts = <8>; | |
ff65d4ca | 563 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
75453a08 SH |
564 | status = "disabled"; |
565 | }; | |
566 | ||
718a3500 SH |
567 | pata: pata@83fe0000 { |
568 | compatible = "fsl,imx51-pata", "fsl,imx27-pata"; | |
569 | reg = <0x83fe0000 0x4000>; | |
570 | interrupts = <70>; | |
ff65d4ca | 571 | clocks = <&clks IMX5_CLK_PATA_GATE>; |
718a3500 SH |
572 | status = "disabled"; |
573 | }; | |
574 | ||
a15d9f89 | 575 | ssi3: ssi@83fe8000 { |
6ff7f51e | 576 | #sound-dai-cells = <0>; |
a15d9f89 SG |
577 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
578 | reg = <0x83fe8000 0x4000>; | |
579 | interrupts = <96>; | |
53ec8748 FE |
580 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, |
581 | <&clks IMX5_CLK_SSI3_ROOT_GATE>; | |
582 | clock-names = "ipg", "baud"; | |
5da826ab SG |
583 | dmas = <&sdma 46 0 0>, |
584 | <&sdma 47 0 0>; | |
585 | dma-names = "rx", "tx"; | |
a15d9f89 | 586 | fsl,fifo-depth = <15>; |
a15d9f89 SG |
587 | status = "disabled"; |
588 | }; | |
589 | ||
7b7d6727 | 590 | fec: ethernet@83fec000 { |
9daaf31a SG |
591 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
592 | reg = <0x83fec000 0x4000>; | |
593 | interrupts = <87>; | |
ff65d4ca | 594 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
46311707 JT |
595 | <&clks IMX5_CLK_FEC_GATE>, |
596 | <&clks IMX5_CLK_FEC_GATE>; | |
f40f38d1 | 597 | clock-names = "ipg", "ahb", "ptp"; |
9daaf31a SG |
598 | status = "disabled"; |
599 | }; | |
600 | }; | |
601 | }; | |
602 | }; |