[linux-2.6-block.git] / arch / arm / boot / dts / imx50.dtsi

/*
 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "imx50-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx5-clock.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 * Also for U-Boot there must be a pre-existing /memory node.
	 */
	chosen {};
	memory { device_type = "memory"; };

	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	tzic: tz-interrupt-controller@fffc000 {
		compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc1: esdhc@50004000 {
					compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
						 <&clks IMX5_CLK_DUMMY>,
						 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc2: esdhc@50008000 {
					compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
						 <&clks IMX5_CLK_DUMMY>,
						 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx50-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
						 <&clks IMX5_CLK_UART3_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@50010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
						 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx50-ssi",
							"fsl,imx51-ssi",
							"fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
					dmas = <&sdma 24 1 0>,
					       <&sdma 25 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				esdhc3: esdhc@50020000 {
					compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
						 <&clks IMX5_CLK_DUMMY>,
						 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@50024000 {
					compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
						 <&clks IMX5_CLK_DUMMY>,
						 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbotg: usb@53f80000 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80000 0x0200>;
				interrupts = <18>;
				clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
				status = "disabled";
			};

			usbh1: usb@53f80200 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80200 0x0200>;
				interrupts = <14>;
				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
				dr_mode = "host";
				status = "disabled";
			};

			usbh2: usb@53f80400 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80400 0x0200>;
				interrupts = <16>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				dr_mode = "host";
				status = "disabled";
			};

			usbh3: usb@53f80600 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80600 0x0200>;
				interrupts = <17>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				dr_mode = "host";
				status = "disabled";
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 151 28>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc  0 75 8>, <&iomuxc 8 100 8>,
					      <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
					      <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
					      <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 108 32>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc  0   8  8>, <&iomuxc 8 45 12>,
					      <&iomuxc 20 140 11>;
			};

			wdog1: wdog@53f98000 {
				compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks IMX5_CLK_DUMMY>;
			};

			gpt: timer@53fa0000 {
				compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
				reg = <0x53fa0000 0x4000>;
				interrupts = <39>;
				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
					 <&clks IMX5_CLK_GPT_HF_GATE>;
				clock-names = "ipg", "per";
			};

			iomuxc: iomuxc@53fa8000 {
				compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
				reg = <0x53fa8000 0x4000>;
			};

			gpr: iomuxc-gpr@53fa8000 {
				compatible = "fsl,imx50-iomuxc-gpr", "syscon";
				reg = <0x53fa8000 0xc>;
			};

			pwm1: pwm@53fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb4000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
					 <&clks IMX5_CLK_PWM1_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@53fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb8000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
					 <&clks IMX5_CLK_PWM2_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
					 <&clks IMX5_CLK_UART1_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
					 <&clks IMX5_CLK_UART2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			src: src@53fd0000 {
				compatible = "fsl,imx50-src", "fsl,imx51-src";
				reg = <0x53fd0000 0x4000>;
				#reset-cells = <1>;
			};

			clks: ccm@53fd4000{
				compatible = "fsl,imx50-ccm";
				reg = <0x53fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
			};

			i2c3: i2c@53fec000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				clocks = <&clks IMX5_CLK_I2C3_GATE>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
					 <&clks IMX5_CLK_UART4_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			uart5: serial@63f90000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
					 <&clks IMX5_CLK_UART5_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			owire: owire@63fa4000 {
				compatible = "fsl,imx50-owire", "fsl,imx21-owire";
				reg = <0x63fa4000 0x4000>;
				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
				status = "disabled";
			};

			ecspi2: ecspi@63fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
					 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@63fb0000 {
				compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks IMX5_CLK_SDMA_GATE>,
					 <&clks IMX5_CLK_SDMA_GATE>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
			};

			cspi: cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
					 <&clks IMX5_CLK_CSPI_IPG_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@63fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks IMX5_CLK_I2C2_GATE>;
				status = "disabled";
			};

			i2c1: i2c@63fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks IMX5_CLK_I2C1_GATE>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
							"fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
				dmas = <&sdma 28 0 0>,
				       <&sdma 29 0 0>;
				dma-names = "rx", "tx";
				fsl,fifo-depth = <15>;
				status = "disabled";
			};

			audmux: audmux@63fd0000 {
				compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			fec: ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks IMX5_CLK_FEC_GATE>,
					 <&clks IMX5_CLK_FEC_GATE>,
					 <&clks IMX5_CLK_FEC_GATE>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
64972acd GU	1	/*
	2	* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
	3	* Copyright 2011 Freescale Semiconductor, Inc.
	4	* Copyright 2011 Linaro Ltd.
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
64972acd	14	#include "imx50-pinfunc.h"
12de44f5	15	#include <dt-bindings/gpio/gpio.h>
6650d6db	16	#include <dt-bindings/clock/imx5-clock.h>
64972acd GU	17
64972acd GU	18	/ {
7f107887 FE	19	#address-cells = <1>;
7f107887 FE	20	#size-cells = <1>;
a971c554 FE	21	/*
	22	* The decompressor and also some bootloaders rely on a
	23	* pre-existing /chosen node to be available to insert the
	24	* command line and merge other ATAGS info.
	25	* Also for U-Boot there must be a pre-existing /memory node.
	26	*/
	27	chosen {};
7f08e6aa	28	memory { device_type = "memory"; };
7f107887	29
64972acd	30	aliases {
22970070	31	ethernet0 = &fec;
64972acd GU	32	gpio0 = &gpio1;
	33	gpio1 = &gpio2;
	34	gpio2 = &gpio3;
	35	gpio3 = &gpio4;
	36	gpio4 = &gpio5;
	37	gpio5 = &gpio6;
	38	serial0 = &uart1;
	39	serial1 = &uart2;
	40	serial2 = &uart3;
	41	serial3 = &uart4;
	42	serial4 = &uart5;
	43	};
	44
	45	cpus {
	46	#address-cells = <1>;
	47	#size-cells = <0>;
	48	cpu@0 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a8";
	51	reg = <0x0>;
	52	};
	53	};
	54
8dccafaa	55	tzic: tz-interrupt-controller@fffc000 {
64972acd GU	56	compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
	57	interrupt-controller;
	58	#interrupt-cells = <1>;
	59	reg = <0x0fffc000 0x4000>;
	60	};
	61
	62	clocks {
64972acd GU	63	ckil {
64972acd GU	64	compatible = "fsl,imx-ckil", "fixed-clock";
4b2b4043	65	#clock-cells = <0>;
64972acd GU	66	clock-frequency = <32768>;
	67	};
	68
	69	ckih1 {
	70	compatible = "fsl,imx-ckih1", "fixed-clock";
4b2b4043	71	#clock-cells = <0>;
64972acd GU	72	clock-frequency = <22579200>;
	73	};
	74
	75	ckih2 {
	76	compatible = "fsl,imx-ckih2", "fixed-clock";
4b2b4043	77	#clock-cells = <0>;
64972acd GU	78	clock-frequency = <0>;
	79	};
	80
	81	osc {
	82	compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043	83	#clock-cells = <0>;
64972acd GU	84	clock-frequency = <24000000>;
	85	};
	86	};
	87
	88	soc {
	89	#address-cells = <1>;
	90	#size-cells = <1>;
	91	compatible = "simple-bus";
	92	interrupt-parent = <&tzic>;
	93	ranges;
	94
	95	aips@50000000 { /* AIPS1 */
	96	compatible = "fsl,aips-bus", "simple-bus";
	97	#address-cells = <1>;
	98	#size-cells = <1>;
	99	reg = <0x50000000 0x10000000>;
	100	ranges;
	101
	102	spba@50000000 {
	103	compatible = "fsl,spba-bus", "simple-bus";
	104	#address-cells = <1>;
	105	#size-cells = <1>;
	106	reg = <0x50000000 0x40000>;
	107	ranges;
	108
	109	esdhc1: esdhc@50004000 {
fe64d054	110	compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
64972acd GU	111	reg = <0x50004000 0x4000>;
64972acd GU	112	interrupts = <1>;
6650d6db	113	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
46311707 JT	114	<&clks IMX5_CLK_DUMMY>,
46311707 JT	115	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
64972acd GU	116	clock-names = "ipg", "ahb", "per";
	117	bus-width = <4>;
	118	status = "disabled";
	119	};
	120
	121	esdhc2: esdhc@50008000 {
fe64d054	122	compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
64972acd GU	123	reg = <0x50008000 0x4000>;
64972acd GU	124	interrupts = <2>;
6650d6db	125	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
46311707 JT	126	<&clks IMX5_CLK_DUMMY>,
46311707 JT	127	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
64972acd GU	128	clock-names = "ipg", "ahb", "per";
	129	bus-width = <4>;
	130	status = "disabled";
	131	};
	132
	133	uart3: serial@5000c000 {
	134	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	135	reg = <0x5000c000 0x4000>;
	136	interrupts = <33>;
6650d6db	137	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
46311707	138	<&clks IMX5_CLK_UART3_PER_GATE>;
64972acd GU	139	clock-names = "ipg", "per";
	140	status = "disabled";
	141	};
	142
	143	ecspi1: ecspi@50010000 {
	144	#address-cells = <1>;
	145	#size-cells = <0>;
	146	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	147	reg = <0x50010000 0x4000>;
	148	interrupts = <36>;
6650d6db	149	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
46311707	150	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
64972acd GU	151	clock-names = "ipg", "per";
	152	status = "disabled";
	153	};
	154
	155	ssi2: ssi@50014000 {
6ff7f51e	156	#sound-dai-cells = <0>;
28f93d0b MP	157	compatible = "fsl,imx50-ssi",
	158	"fsl,imx51-ssi",
	159	"fsl,imx21-ssi";
64972acd GU	160	reg = <0x50014000 0x4000>;
64972acd GU	161	interrupts = <30>;
6650d6db	162	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
d9a9f38f MP	163	dmas = <&sdma 24 1 0>,
	164	<&sdma 25 1 0>;
	165	dma-names = "rx", "tx";
64972acd	166	fsl,fifo-depth = <15>;
64972acd GU	167	status = "disabled";
	168	};
	169
	170	esdhc3: esdhc@50020000 {
fe64d054	171	compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
64972acd GU	172	reg = <0x50020000 0x4000>;
64972acd GU	173	interrupts = <3>;
6650d6db	174	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
46311707 JT	175	<&clks IMX5_CLK_DUMMY>,
46311707 JT	176	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
64972acd GU	177	clock-names = "ipg", "ahb", "per";
	178	bus-width = <4>;
	179	status = "disabled";
	180	};
	181
	182	esdhc4: esdhc@50024000 {
fe64d054	183	compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
64972acd GU	184	reg = <0x50024000 0x4000>;
64972acd GU	185	interrupts = <4>;
6650d6db	186	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
46311707 JT	187	<&clks IMX5_CLK_DUMMY>,
46311707 JT	188	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
64972acd GU	189	clock-names = "ipg", "ahb", "per";
	190	bus-width = <4>;
	191	status = "disabled";
	192	};
	193	};
	194
	195	usbotg: usb@53f80000 {
	196	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	197	reg = <0x53f80000 0x0200>;
	198	interrupts = <18>;
6650d6db	199	clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
64972acd GU	200	status = "disabled";
	201	};
	202
	203	usbh1: usb@53f80200 {
	204	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	205	reg = <0x53f80200 0x0200>;
	206	interrupts = <14>;
6650d6db	207	clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
3ec481ed	208	dr_mode = "host";
64972acd GU	209	status = "disabled";
	210	};
	211
	212	usbh2: usb@53f80400 {
	213	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	214	reg = <0x53f80400 0x0200>;
	215	interrupts = <16>;
6650d6db	216	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
3ec481ed	217	dr_mode = "host";
64972acd GU	218	status = "disabled";
	219	};
	220
	221	usbh3: usb@53f80600 {
	222	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	223	reg = <0x53f80600 0x0200>;
	224	interrupts = <17>;
6650d6db	225	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
3ec481ed	226	dr_mode = "host";
64972acd GU	227	status = "disabled";
	228	};
	229
	230	gpio1: gpio@53f84000 {
	231	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	232	reg = <0x53f84000 0x4000>;
	233	interrupts = <50 51>;
	234	gpio-controller;
	235	#gpio-cells = <2>;
	236	interrupt-controller;
	237	#interrupt-cells = <2>;
bb728d66	238	gpio-ranges = <&iomuxc 0 151 28>;
64972acd GU	239	};
	240
	241	gpio2: gpio@53f88000 {
	242	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	243	reg = <0x53f88000 0x4000>;
	244	interrupts = <52 53>;
	245	gpio-controller;
	246	#gpio-cells = <2>;
	247	interrupt-controller;
	248	#interrupt-cells = <2>;
bb728d66 VZ	249	gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
	250	<&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
	251	<&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
	252	<&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
64972acd GU	253	};
	254
	255	gpio3: gpio@53f8c000 {
	256	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	257	reg = <0x53f8c000 0x4000>;
	258	interrupts = <54 55>;
	259	gpio-controller;
	260	#gpio-cells = <2>;
	261	interrupt-controller;
	262	#interrupt-cells = <2>;
bb728d66	263	gpio-ranges = <&iomuxc 0 108 32>;
64972acd GU	264	};
	265
	266	gpio4: gpio@53f90000 {
	267	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	268	reg = <0x53f90000 0x4000>;
	269	interrupts = <56 57>;
	270	gpio-controller;
	271	#gpio-cells = <2>;
	272	interrupt-controller;
	273	#interrupt-cells = <2>;
bb728d66 VZ	274	gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
bb728d66 VZ	275	<&iomuxc 20 140 11>;
64972acd GU	276	};
	277
	278	wdog1: wdog@53f98000 {
	279	compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
	280	reg = <0x53f98000 0x4000>;
	281	interrupts = <58>;
6650d6db	282	clocks = <&clks IMX5_CLK_DUMMY>;
64972acd GU	283	};
	284
	285	gpt: timer@53fa0000 {
	286	compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
	287	reg = <0x53fa0000 0x4000>;
	288	interrupts = <39>;
6650d6db	289	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
46311707	290	<&clks IMX5_CLK_GPT_HF_GATE>;
64972acd GU	291	clock-names = "ipg", "per";
	292	};
	293
	294	iomuxc: iomuxc@53fa8000 {
	295	compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
	296	reg = <0x53fa8000 0x4000>;
	297	};
	298
	299	gpr: iomuxc-gpr@53fa8000 {
	300	compatible = "fsl,imx50-iomuxc-gpr", "syscon";
	301	reg = <0x53fa8000 0xc>;
	302	};
	303
	304	pwm1: pwm@53fb4000 {
	305	#pwm-cells = <2>;
	306	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	307	reg = <0x53fb4000 0x4000>;
6650d6db	308	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
46311707	309	<&clks IMX5_CLK_PWM1_HF_GATE>;
64972acd GU	310	clock-names = "ipg", "per";
	311	interrupts = <61>;
	312	};
	313
	314	pwm2: pwm@53fb8000 {
	315	#pwm-cells = <2>;
	316	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	317	reg = <0x53fb8000 0x4000>;
6650d6db	318	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
46311707	319	<&clks IMX5_CLK_PWM2_HF_GATE>;
64972acd GU	320	clock-names = "ipg", "per";
	321	interrupts = <94>;
	322	};
	323
	324	uart1: serial@53fbc000 {
	325	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	326	reg = <0x53fbc000 0x4000>;
	327	interrupts = <31>;
6650d6db	328	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
46311707	329	<&clks IMX5_CLK_UART1_PER_GATE>;
64972acd GU	330	clock-names = "ipg", "per";
	331	status = "disabled";
	332	};
	333
	334	uart2: serial@53fc0000 {
	335	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	336	reg = <0x53fc0000 0x4000>;
	337	interrupts = <32>;
6650d6db	338	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
46311707	339	<&clks IMX5_CLK_UART2_PER_GATE>;
64972acd GU	340	clock-names = "ipg", "per";
	341	status = "disabled";
	342	};
	343
	344	src: src@53fd0000 {
	345	compatible = "fsl,imx50-src", "fsl,imx51-src";
	346	reg = <0x53fd0000 0x4000>;
	347	#reset-cells = <1>;
	348	};
	349
	350	clks: ccm@53fd4000{
	351	compatible = "fsl,imx50-ccm";
	352	reg = <0x53fd4000 0x4000>;
	353	interrupts = <0 71 0x04 0 72 0x04>;
	354	#clock-cells = <1>;
	355	};
	356
	357	gpio5: gpio@53fdc000 {
	358	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	359	reg = <0x53fdc000 0x4000>;
	360	interrupts = <103 104>;
	361	gpio-controller;
	362	#gpio-cells = <2>;
	363	interrupt-controller;
	364	#interrupt-cells = <2>;
bb728d66	365	gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
64972acd GU	366	};
	367
	368	gpio6: gpio@53fe0000 {
	369	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	370	reg = <0x53fe0000 0x4000>;
	371	interrupts = <105 106>;
	372	gpio-controller;
	373	#gpio-cells = <2>;
	374	interrupt-controller;
	375	#interrupt-cells = <2>;
bb728d66	376	gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
64972acd GU	377	};
	378
	379	i2c3: i2c@53fec000 {
	380	#address-cells = <1>;
	381	#size-cells = <0>;
	382	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	383	reg = <0x53fec000 0x4000>;
	384	interrupts = <64>;
6650d6db	385	clocks = <&clks IMX5_CLK_I2C3_GATE>;
64972acd GU	386	status = "disabled";
	387	};
	388
	389	uart4: serial@53ff0000 {
	390	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	391	reg = <0x53ff0000 0x4000>;
	392	interrupts = <13>;
6650d6db	393	clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
46311707	394	<&clks IMX5_CLK_UART4_PER_GATE>;
64972acd GU	395	clock-names = "ipg", "per";
	396	status = "disabled";
	397	};
	398	};
	399
	400	aips@60000000 { /* AIPS2 */
	401	compatible = "fsl,aips-bus", "simple-bus";
	402	#address-cells = <1>;
	403	#size-cells = <1>;
	404	reg = <0x60000000 0x10000000>;
	405	ranges;
	406
	407	uart5: serial@63f90000 {
	408	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	409	reg = <0x63f90000 0x4000>;
	410	interrupts = <86>;
6650d6db	411	clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
46311707	412	<&clks IMX5_CLK_UART5_PER_GATE>;
64972acd GU	413	clock-names = "ipg", "per";
	414	status = "disabled";
	415	};
	416
	417	owire: owire@63fa4000 {
	418	compatible = "fsl,imx50-owire", "fsl,imx21-owire";
	419	reg = <0x63fa4000 0x4000>;
6650d6db	420	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
64972acd GU	421	status = "disabled";
	422	};
	423
	424	ecspi2: ecspi@63fac000 {
	425	#address-cells = <1>;
	426	#size-cells = <0>;
	427	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	428	reg = <0x63fac000 0x4000>;
	429	interrupts = <37>;
6650d6db	430	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
46311707	431	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
64972acd GU	432	clock-names = "ipg", "per";
	433	status = "disabled";
	434	};
	435
	436	sdma: sdma@63fb0000 {
	437	compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
	438	reg = <0x63fb0000 0x4000>;
	439	interrupts = <6>;
6650d6db	440	clocks = <&clks IMX5_CLK_SDMA_GATE>,
46311707	441	<&clks IMX5_CLK_SDMA_GATE>;
64972acd	442	clock-names = "ipg", "ahb";
afe42e6a	443	#dma-cells = <3>;
64972acd GU	444	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
	445	};
	446
	447	cspi: cspi@63fc0000 {
	448	#address-cells = <1>;
	449	#size-cells = <0>;
	450	compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
	451	reg = <0x63fc0000 0x4000>;
	452	interrupts = <38>;
6650d6db	453	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
46311707	454	<&clks IMX5_CLK_CSPI_IPG_GATE>;
64972acd GU	455	clock-names = "ipg", "per";
	456	status = "disabled";
	457	};
	458
	459	i2c2: i2c@63fc4000 {
	460	#address-cells = <1>;
	461	#size-cells = <0>;
	462	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	463	reg = <0x63fc4000 0x4000>;
	464	interrupts = <63>;
6650d6db	465	clocks = <&clks IMX5_CLK_I2C2_GATE>;
64972acd GU	466	status = "disabled";
	467	};
	468
	469	i2c1: i2c@63fc8000 {
	470	#address-cells = <1>;
	471	#size-cells = <0>;
	472	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	473	reg = <0x63fc8000 0x4000>;
	474	interrupts = <62>;
6650d6db	475	clocks = <&clks IMX5_CLK_I2C1_GATE>;
64972acd GU	476	status = "disabled";
	477	};
	478
	479	ssi1: ssi@63fcc000 {
6ff7f51e	480	#sound-dai-cells = <0>;
28f93d0b MP	481	compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
28f93d0b MP	482	"fsl,imx21-ssi";
64972acd GU	483	reg = <0x63fcc000 0x4000>;
64972acd GU	484	interrupts = <29>;
6650d6db	485	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
d9a9f38f MP	486	dmas = <&sdma 28 0 0>,
	487	<&sdma 29 0 0>;
	488	dma-names = "rx", "tx";
64972acd	489	fsl,fifo-depth = <15>;
64972acd GU	490	status = "disabled";
	491	};
	492
	493	audmux: audmux@63fd0000 {
	494	compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
	495	reg = <0x63fd0000 0x4000>;
	496	status = "disabled";
	497	};
	498
	499	fec: ethernet@63fec000 {
	500	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	501	reg = <0x63fec000 0x4000>;
	502	interrupts = <87>;
6650d6db	503	clocks = <&clks IMX5_CLK_FEC_GATE>,
46311707 JT	504	<&clks IMX5_CLK_FEC_GATE>,
46311707 JT	505	<&clks IMX5_CLK_FEC_GATE>;
64972acd GU	506	clock-names = "ipg", "ahb", "ptp";
	507	status = "disabled";
	508	};
	509	};
	510	};
	511	};