[linux-2.6-block.git] / arch / arm / boot / dts / imx50.dtsi

/*
 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>

/ {
	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	tzic: tz-interrupt-controller@0fffc000 {
		compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc1: esdhc@50004000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC1_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc2: esdhc@50008000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC2_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx50-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
					         <&clks IMX5_CLK_UART3_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@50010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
					         <&clks IMX5_CLK_ECSPI1_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					compatible = "fsl,imx50-ssi",
							"fsl,imx51-ssi",
							"fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc3: esdhc@50020000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC3_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@50024000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC4_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbotg: usb@53f80000 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80000 0x0200>;
				interrupts = <18>;
				clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
				status = "disabled";
			};

			usbh1: usb@53f80200 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80200 0x0200>;
				interrupts = <14>;
				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
				status = "disabled";
			};

			usbh2: usb@53f80400 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80400 0x0200>;
				interrupts = <16>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				status = "disabled";
			};

			usbh3: usb@53f80600 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80600 0x0200>;
				interrupts = <17>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				status = "disabled";
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			wdog1: wdog@53f98000 {
				compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks IMX5_CLK_DUMMY>;
			};

			gpt: timer@53fa0000 {
				compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
				reg = <0x53fa0000 0x4000>;
				interrupts = <39>;
				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
				         <&clks IMX5_CLK_GPT_HF_GATE>;
				clock-names = "ipg", "per";
			};

			iomuxc: iomuxc@53fa8000 {
				compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
				reg = <0x53fa8000 0x4000>;
			};

			gpr: iomuxc-gpr@53fa8000 {
				compatible = "fsl,imx50-iomuxc-gpr", "syscon";
				reg = <0x53fa8000 0xc>;
			};

			pwm1: pwm@53fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb4000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
				         <&clks IMX5_CLK_PWM1_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@53fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb8000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
				         <&clks IMX5_CLK_PWM2_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
				         <&clks IMX5_CLK_UART1_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
				         <&clks IMX5_CLK_UART2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			src: src@53fd0000 {
				compatible = "fsl,imx50-src", "fsl,imx51-src";
				reg = <0x53fd0000 0x4000>;
				#reset-cells = <1>;
			};

			clks: ccm@53fd4000{
				compatible = "fsl,imx50-ccm";
				reg = <0x53fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c3: i2c@53fec000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				clocks = <&clks IMX5_CLK_I2C3_GATE>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
				         <&clks IMX5_CLK_UART4_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			uart5: serial@63f90000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
				         <&clks IMX5_CLK_UART5_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			owire: owire@63fa4000 {
				compatible = "fsl,imx50-owire", "fsl,imx21-owire";
				reg = <0x63fa4000 0x4000>;
				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
				status = "disabled";
			};

			ecspi2: ecspi@63fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
				         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@63fb0000 {
				compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks IMX5_CLK_SDMA_GATE>,
				         <&clks IMX5_CLK_SDMA_GATE>;
				clock-names = "ipg", "ahb";
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
			};

			cspi: cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
				         <&clks IMX5_CLK_CSPI_IPG_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@63fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks IMX5_CLK_I2C2_GATE>;
				status = "disabled";
			};

			i2c1: i2c@63fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks IMX5_CLK_I2C1_GATE>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
							"fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux: audmux@63fd0000 {
				compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			fec: ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
64972acd GU	1	/*
	2	* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
	3	* Copyright 2011 Freescale Semiconductor, Inc.
	4	* Copyright 2011 Linaro Ltd.
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	#include "skeleton.dtsi"
	15	#include "imx50-pinfunc.h"
6650d6db	16	#include <dt-bindings/clock/imx5-clock.h>
64972acd GU	17
	18	/ {
	19	aliases {
	20	gpio0 = &gpio1;
	21	gpio1 = &gpio2;
	22	gpio2 = &gpio3;
	23	gpio3 = &gpio4;
	24	gpio4 = &gpio5;
	25	gpio5 = &gpio6;
	26	serial0 = &uart1;
	27	serial1 = &uart2;
	28	serial2 = &uart3;
	29	serial3 = &uart4;
	30	serial4 = &uart5;
	31	};
	32
	33	cpus {
	34	#address-cells = <1>;
	35	#size-cells = <0>;
	36	cpu@0 {
	37	device_type = "cpu";
	38	compatible = "arm,cortex-a8";
	39	reg = <0x0>;
	40	};
	41	};
	42
	43	tzic: tz-interrupt-controller@0fffc000 {
	44	compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
	45	interrupt-controller;
	46	#interrupt-cells = <1>;
	47	reg = <0x0fffc000 0x4000>;
	48	};
	49
	50	clocks {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53
	54	ckil {
	55	compatible = "fsl,imx-ckil", "fixed-clock";
	56	clock-frequency = <32768>;
	57	};
	58
	59	ckih1 {
	60	compatible = "fsl,imx-ckih1", "fixed-clock";
	61	clock-frequency = <22579200>;
	62	};
	63
	64	ckih2 {
	65	compatible = "fsl,imx-ckih2", "fixed-clock";
	66	clock-frequency = <0>;
	67	};
	68
	69	osc {
	70	compatible = "fsl,imx-osc", "fixed-clock";
	71	clock-frequency = <24000000>;
	72	};
	73	};
	74
	75	soc {
	76	#address-cells = <1>;
	77	#size-cells = <1>;
	78	compatible = "simple-bus";
	79	interrupt-parent = <&tzic>;
	80	ranges;
81
82	aips@50000000 { /* AIPS1 */
83	compatible = "fsl,aips-bus", "simple-bus";
84	#address-cells = <1>;
85	#size-cells = <1>;
86	reg = <0x50000000 0x10000000>;
87	ranges;
88
89	spba@50000000 {
90	compatible = "fsl,spba-bus", "simple-bus";
91	#address-cells = <1>;
92	#size-cells = <1>;
93	reg = <0x50000000 0x40000>;
94	ranges;
95
96	esdhc1: esdhc@50004000 {
97	compatible = "fsl,imx50-esdhc";
98	reg = <0x50004000 0x4000>;
99	interrupts = <1>;
6650d6db LS	100	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
	101	<&clks IMX5_CLK_DUMMY>,
	102	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
64972acd GU	103	clock-names = "ipg", "ahb", "per";
	104	bus-width = <4>;
	105	status = "disabled";
	106	};
	107
	108	esdhc2: esdhc@50008000 {
	109	compatible = "fsl,imx50-esdhc";
	110	reg = <0x50008000 0x4000>;
	111	interrupts = <2>;
6650d6db LS	112	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
	113	<&clks IMX5_CLK_DUMMY>,
	114	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
64972acd GU	115	clock-names = "ipg", "ahb", "per";
	116	bus-width = <4>;
	117	status = "disabled";
	118	};
	119
	120	uart3: serial@5000c000 {
	121	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	122	reg = <0x5000c000 0x4000>;
	123	interrupts = <33>;
6650d6db LS	124	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
6650d6db LS	125	<&clks IMX5_CLK_UART3_PER_GATE>;
64972acd GU	126	clock-names = "ipg", "per";
	127	status = "disabled";
	128	};
	129
	130	ecspi1: ecspi@50010000 {
	131	#address-cells = <1>;
	132	#size-cells = <0>;
	133	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	134	reg = <0x50010000 0x4000>;
	135	interrupts = <36>;
6650d6db LS	136	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
6650d6db LS	137	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
64972acd GU	138	clock-names = "ipg", "per";
	139	status = "disabled";
	140	};
	141
	142	ssi2: ssi@50014000 {
28f93d0b MP	143	compatible = "fsl,imx50-ssi",
	144	"fsl,imx51-ssi",
	145	"fsl,imx21-ssi";
64972acd GU	146	reg = <0x50014000 0x4000>;
64972acd GU	147	interrupts = <30>;
6650d6db	148	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
64972acd GU	149	fsl,fifo-depth = <15>;
	150	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	151	status = "disabled";
	152	};
	153
	154	esdhc3: esdhc@50020000 {
	155	compatible = "fsl,imx50-esdhc";
	156	reg = <0x50020000 0x4000>;
	157	interrupts = <3>;
6650d6db LS	158	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
	159	<&clks IMX5_CLK_DUMMY>,
	160	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
64972acd GU	161	clock-names = "ipg", "ahb", "per";
	162	bus-width = <4>;
	163	status = "disabled";
	164	};
	165
	166	esdhc4: esdhc@50024000 {
	167	compatible = "fsl,imx50-esdhc";
	168	reg = <0x50024000 0x4000>;
	169	interrupts = <4>;
6650d6db LS	170	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
	171	<&clks IMX5_CLK_DUMMY>,
	172	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
64972acd GU	173	clock-names = "ipg", "ahb", "per";
	174	bus-width = <4>;
	175	status = "disabled";
	176	};
	177	};
	178
	179	usbotg: usb@53f80000 {
	180	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	181	reg = <0x53f80000 0x0200>;
	182	interrupts = <18>;
6650d6db	183	clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
64972acd GU	184	status = "disabled";
	185	};
	186
	187	usbh1: usb@53f80200 {
	188	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	189	reg = <0x53f80200 0x0200>;
	190	interrupts = <14>;
6650d6db	191	clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
64972acd GU	192	status = "disabled";
	193	};
	194
	195	usbh2: usb@53f80400 {
	196	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	197	reg = <0x53f80400 0x0200>;
	198	interrupts = <16>;
6650d6db	199	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
64972acd GU	200	status = "disabled";
	201	};
	202
	203	usbh3: usb@53f80600 {
	204	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	205	reg = <0x53f80600 0x0200>;
	206	interrupts = <17>;
6650d6db	207	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
64972acd GU	208	status = "disabled";
	209	};
	210
	211	gpio1: gpio@53f84000 {
	212	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	213	reg = <0x53f84000 0x4000>;
	214	interrupts = <50 51>;
	215	gpio-controller;
	216	#gpio-cells = <2>;
	217	interrupt-controller;
	218	#interrupt-cells = <2>;
	219	};
	220
	221	gpio2: gpio@53f88000 {
	222	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	223	reg = <0x53f88000 0x4000>;
	224	interrupts = <52 53>;
	225	gpio-controller;
	226	#gpio-cells = <2>;
	227	interrupt-controller;
	228	#interrupt-cells = <2>;
	229	};
	230
	231	gpio3: gpio@53f8c000 {
	232	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	233	reg = <0x53f8c000 0x4000>;
	234	interrupts = <54 55>;
	235	gpio-controller;
	236	#gpio-cells = <2>;
	237	interrupt-controller;
	238	#interrupt-cells = <2>;
	239	};
	240
	241	gpio4: gpio@53f90000 {
	242	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	243	reg = <0x53f90000 0x4000>;
	244	interrupts = <56 57>;
	245	gpio-controller;
	246	#gpio-cells = <2>;
	247	interrupt-controller;
	248	#interrupt-cells = <2>;
	249	};
	250
	251	wdog1: wdog@53f98000 {
	252	compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
	253	reg = <0x53f98000 0x4000>;
	254	interrupts = <58>;
6650d6db	255	clocks = <&clks IMX5_CLK_DUMMY>;
64972acd GU	256	};
	257
	258	gpt: timer@53fa0000 {
	259	compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
	260	reg = <0x53fa0000 0x4000>;
	261	interrupts = <39>;
6650d6db LS	262	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
6650d6db LS	263	<&clks IMX5_CLK_GPT_HF_GATE>;
64972acd GU	264	clock-names = "ipg", "per";
	265	};
	266
	267	iomuxc: iomuxc@53fa8000 {
	268	compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
	269	reg = <0x53fa8000 0x4000>;
	270	};
	271
	272	gpr: iomuxc-gpr@53fa8000 {
	273	compatible = "fsl,imx50-iomuxc-gpr", "syscon";
	274	reg = <0x53fa8000 0xc>;
	275	};
	276
	277	pwm1: pwm@53fb4000 {
	278	#pwm-cells = <2>;
	279	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	280	reg = <0x53fb4000 0x4000>;
6650d6db LS	281	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
6650d6db LS	282	<&clks IMX5_CLK_PWM1_HF_GATE>;
64972acd GU	283	clock-names = "ipg", "per";
	284	interrupts = <61>;
	285	};
	286
	287	pwm2: pwm@53fb8000 {
	288	#pwm-cells = <2>;
	289	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	290	reg = <0x53fb8000 0x4000>;
6650d6db LS	291	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
6650d6db LS	292	<&clks IMX5_CLK_PWM2_HF_GATE>;
64972acd GU	293	clock-names = "ipg", "per";
	294	interrupts = <94>;
	295	};
	296
	297	uart1: serial@53fbc000 {
	298	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	299	reg = <0x53fbc000 0x4000>;
	300	interrupts = <31>;
6650d6db LS	301	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
6650d6db LS	302	<&clks IMX5_CLK_UART1_PER_GATE>;
64972acd GU	303	clock-names = "ipg", "per";
	304	status = "disabled";
	305	};
	306
	307	uart2: serial@53fc0000 {
	308	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	309	reg = <0x53fc0000 0x4000>;
	310	interrupts = <32>;
6650d6db LS	311	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
6650d6db LS	312	<&clks IMX5_CLK_UART2_PER_GATE>;
64972acd GU	313	clock-names = "ipg", "per";
	314	status = "disabled";
	315	};
	316
	317	src: src@53fd0000 {
	318	compatible = "fsl,imx50-src", "fsl,imx51-src";
	319	reg = <0x53fd0000 0x4000>;
	320	#reset-cells = <1>;
	321	};
	322
	323	clks: ccm@53fd4000{
	324	compatible = "fsl,imx50-ccm";
	325	reg = <0x53fd4000 0x4000>;
	326	interrupts = <0 71 0x04 0 72 0x04>;
	327	#clock-cells = <1>;
	328	};
	329
	330	gpio5: gpio@53fdc000 {
	331	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	332	reg = <0x53fdc000 0x4000>;
	333	interrupts = <103 104>;
	334	gpio-controller;
	335	#gpio-cells = <2>;
	336	interrupt-controller;
	337	#interrupt-cells = <2>;
	338	};
	339
	340	gpio6: gpio@53fe0000 {
	341	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	342	reg = <0x53fe0000 0x4000>;
	343	interrupts = <105 106>;
	344	gpio-controller;
	345	#gpio-cells = <2>;
	346	interrupt-controller;
	347	#interrupt-cells = <2>;
	348	};
	349
	350	i2c3: i2c@53fec000 {
	351	#address-cells = <1>;
	352	#size-cells = <0>;
	353	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	354	reg = <0x53fec000 0x4000>;
	355	interrupts = <64>;
6650d6db	356	clocks = <&clks IMX5_CLK_I2C3_GATE>;
64972acd GU	357	status = "disabled";
	358	};
	359
	360	uart4: serial@53ff0000 {
	361	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	362	reg = <0x53ff0000 0x4000>;
	363	interrupts = <13>;
6650d6db LS	364	clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
6650d6db LS	365	<&clks IMX5_CLK_UART4_PER_GATE>;
64972acd GU	366	clock-names = "ipg", "per";
	367	status = "disabled";
	368	};
	369	};
	370
	371	aips@60000000 { /* AIPS2 */
	372	compatible = "fsl,aips-bus", "simple-bus";
	373	#address-cells = <1>;
	374	#size-cells = <1>;
	375	reg = <0x60000000 0x10000000>;
	376	ranges;
	377
	378	uart5: serial@63f90000 {
	379	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	380	reg = <0x63f90000 0x4000>;
	381	interrupts = <86>;
6650d6db LS	382	clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
6650d6db LS	383	<&clks IMX5_CLK_UART5_PER_GATE>;
64972acd GU	384	clock-names = "ipg", "per";
	385	status = "disabled";
	386	};
	387
	388	owire: owire@63fa4000 {
	389	compatible = "fsl,imx50-owire", "fsl,imx21-owire";
	390	reg = <0x63fa4000 0x4000>;
6650d6db	391	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
64972acd GU	392	status = "disabled";
	393	};
	394
	395	ecspi2: ecspi@63fac000 {
	396	#address-cells = <1>;
	397	#size-cells = <0>;
	398	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	399	reg = <0x63fac000 0x4000>;
	400	interrupts = <37>;
6650d6db LS	401	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
6650d6db LS	402	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
64972acd GU	403	clock-names = "ipg", "per";
	404	status = "disabled";
	405	};
	406
	407	sdma: sdma@63fb0000 {
	408	compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
	409	reg = <0x63fb0000 0x4000>;
	410	interrupts = <6>;
6650d6db LS	411	clocks = <&clks IMX5_CLK_SDMA_GATE>,
6650d6db LS	412	<&clks IMX5_CLK_SDMA_GATE>;
64972acd GU	413	clock-names = "ipg", "ahb";
	414	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
	415	};
	416
	417	cspi: cspi@63fc0000 {
	418	#address-cells = <1>;
	419	#size-cells = <0>;
	420	compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
	421	reg = <0x63fc0000 0x4000>;
	422	interrupts = <38>;
6650d6db LS	423	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
6650d6db LS	424	<&clks IMX5_CLK_CSPI_IPG_GATE>;
64972acd GU	425	clock-names = "ipg", "per";
	426	status = "disabled";
	427	};
	428
	429	i2c2: i2c@63fc4000 {
	430	#address-cells = <1>;
	431	#size-cells = <0>;
	432	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	433	reg = <0x63fc4000 0x4000>;
	434	interrupts = <63>;
6650d6db	435	clocks = <&clks IMX5_CLK_I2C2_GATE>;
64972acd GU	436	status = "disabled";
	437	};
	438
	439	i2c1: i2c@63fc8000 {
	440	#address-cells = <1>;
	441	#size-cells = <0>;
	442	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	443	reg = <0x63fc8000 0x4000>;
	444	interrupts = <62>;
6650d6db	445	clocks = <&clks IMX5_CLK_I2C1_GATE>;
64972acd GU	446	status = "disabled";
	447	};
	448
	449	ssi1: ssi@63fcc000 {
28f93d0b MP	450	compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
28f93d0b MP	451	"fsl,imx21-ssi";
64972acd GU	452	reg = <0x63fcc000 0x4000>;
64972acd GU	453	interrupts = <29>;
6650d6db	454	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
64972acd GU	455	fsl,fifo-depth = <15>;
	456	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	457	status = "disabled";
	458	};
	459
	460	audmux: audmux@63fd0000 {
	461	compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
	462	reg = <0x63fd0000 0x4000>;
	463	status = "disabled";
	464	};
	465
	466	fec: ethernet@63fec000 {
	467	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	468	reg = <0x63fec000 0x4000>;
	469	interrupts = <87>;
6650d6db LS	470	clocks = <&clks IMX5_CLK_FEC_GATE>,
	471	<&clks IMX5_CLK_FEC_GATE>,
	472	<&clks IMX5_CLK_FEC_GATE>;
64972acd GU	473	clock-names = "ipg", "ahb", "ptp";
	474	status = "disabled";
	475	};
	476	};
	477	};
	478	};