projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: cfa10049: Add the DH2228FV DAC to the DTS
[linux-2.6-block.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
ce4c6f9b
SG		 17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
530f1d41
SG		 23 saif0 = &saif0;
24 saif1 = &saif1;
80d969e4
FE		 25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
8c41d573
MV		 30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
ce4c6f9b
SG		 32 };
33
bc3a59c1
DA		 34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 apb@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x80000>;
45 ranges;
46
47 apbh@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x3c900>;
52 ranges;
53
54 icoll: interrupt-controller@80000000 {
83a84efc 55 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0x80000000 0x2000>;
59 };
60
61 hsadc@80002000 {
0f06cde7 62 reg = <0x80002000 0x2000>;
bc3a59c1
DA		 63 interrupts = <13 87>;
64 status = "disabled";
65 };
66
67 dma-apbh@80004000 {
84f3570a 68 compatible = "fsl,imx28-dma-apbh";
0f06cde7 69 reg = <0x80004000 0x2000>;
b598b9f3 70 clocks = <&clks 25>;
bc3a59c1
DA		 71 };
72
73 perfmon@80006000 {
0f06cde7 74 reg = <0x80006000 0x800>;
bc3a59c1
DA		 75 interrupts = <27>;
76 status = "disabled";
77 };
78
7a8e5149
HS		 79 gpmi-nand@8000c000 {
80 compatible = "fsl,imx28-gpmi-nand";
81 #address-cells = <1>;
82 #size-cells = <1>;
0f06cde7 83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149
HS		 84 reg-names = "gpmi-nand", "bch";
85 interrupts = <88>, <41>;
86 interrupt-names = "gpmi-dma", "bch";
b598b9f3 87 clocks = <&clks 50>;
7a8e5149 88 fsl,gpmi-dma-channel = <4>;
bc3a59c1
DA		 89 status = "disabled";
90 };
91
92 ssp0: ssp@80010000 {
41bf5706
MR		 93 #address-cells = <1>;
94 #size-cells = <0>;
0f06cde7 95 reg = <0x80010000 0x2000>;
bc3a59c1 96 interrupts = <96 82>;
b598b9f3 97 clocks = <&clks 46>;
35d23047 98 fsl,ssp-dma-channel = <0>;
bc3a59c1
DA		 99 status = "disabled";
100 };
101
102 ssp1: ssp@80012000 {
41bf5706
MR		 103 #address-cells = <1>;
104 #size-cells = <0>;
0f06cde7 105 reg = <0x80012000 0x2000>;
bc3a59c1 106 interrupts = <97 83>;
b598b9f3 107 clocks = <&clks 47>;
35d23047 108 fsl,ssp-dma-channel = <1>;
bc3a59c1
DA		 109 status = "disabled";
110 };
111
112 ssp2: ssp@80014000 {
41bf5706
MR		 113 #address-cells = <1>;
114 #size-cells = <0>;
0f06cde7 115 reg = <0x80014000 0x2000>;
bc3a59c1 116 interrupts = <98 84>;
b598b9f3 117 clocks = <&clks 48>;
35d23047 118 fsl,ssp-dma-channel = <2>;
bc3a59c1
DA		 119 status = "disabled";
120 };
121
122 ssp3: ssp@80016000 {
41bf5706
MR		 123 #address-cells = <1>;
124 #size-cells = <0>;
0f06cde7 125 reg = <0x80016000 0x2000>;
bc3a59c1 126 interrupts = <99 85>;
b598b9f3 127 clocks = <&clks 49>;
35d23047 128 fsl,ssp-dma-channel = <3>;
bc3a59c1
DA		 129 status = "disabled";
130 };
131
132 pinctrl@80018000 {
133 #address-cells = <1>;
134 #size-cells = <0>;
ce4c6f9b 135 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 136 reg = <0x80018000 0x2000>;
bc3a59c1 137
ce4c6f9b
SG		 138 gpio0: gpio@0 {
139 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
140 interrupts = <127>;
141 gpio-controller;
142 #gpio-cells = <2>;
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 };
146
147 gpio1: gpio@1 {
148 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
149 interrupts = <126>;
150 gpio-controller;
151 #gpio-cells = <2>;
152 interrupt-controller;
153 #interrupt-cells = <2>;
154 };
155
156 gpio2: gpio@2 {
157 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
158 interrupts = <125>;
159 gpio-controller;
160 #gpio-cells = <2>;
161 interrupt-controller;
162 #interrupt-cells = <2>;
163 };
164
165 gpio3: gpio@3 {
166 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
167 interrupts = <124>;
168 gpio-controller;
169 #gpio-cells = <2>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 };
173
174 gpio4: gpio@4 {
175 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
176 interrupts = <123>;
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 };
182
bc3a59c1
DA		 183 duart_pins_a: duart@0 {
184 reg = <0>;
f14da767
SG		 185 fsl,pinmux-ids = <
186 0x3102 /* MX28_PAD_PWM0__DUART_RX */
187 0x3112 /* MX28_PAD_PWM1__DUART_TX */
188 >;
bc3a59c1
DA		 189 fsl,drive-strength = <0>;
190 fsl,voltage = <1>;
191 fsl,pull-up = <0>;
192 };
193
8385e7c1
MR		 194 duart_pins_b: duart@1 {
195 reg = <1>;
f14da767
SG		 196 fsl,pinmux-ids = <
197 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
198 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
199 >;
8385e7c1
MR		 200 fsl,drive-strength = <0>;
201 fsl,voltage = <1>;
202 fsl,pull-up = <0>;
203 };
204
e1a4d18f
SG		 205 duart_4pins_a: duart-4pins@0 {
206 reg = <0>;
207 fsl,pinmux-ids = <
208 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
209 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
210 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
211 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
212 >;
213 fsl,drive-strength = <0>;
214 fsl,voltage = <1>;
215 fsl,pull-up = <0>;
216 };
217
7a8e5149
HS		 218 gpmi_pins_a: gpmi-nand@0 {
219 reg = <0>;
f14da767
SG		 220 fsl,pinmux-ids = <
221 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
222 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
223 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
224 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
225 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
226 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
227 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
228 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
229 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
f14da767 230 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
f14da767
SG		 231 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
232 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
233 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
234 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
235 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
236 >;
7a8e5149
HS		 237 fsl,drive-strength = <0>;
238 fsl,voltage = <1>;
239 fsl,pull-up = <0>;
240 };
241
242 gpmi_status_cfg: gpmi-status-cfg {
f14da767
SG		 243 fsl,pinmux-ids = <
244 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
245 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
246 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
247 >;
7a8e5149
HS		 248 fsl,drive-strength = <2>;
249 };
250
80d969e4
FE		 251 auart0_pins_a: auart0@0 {
252 reg = <0>;
f14da767
SG		 253 fsl,pinmux-ids = <
254 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
255 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
256 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
257 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
258 >;
80d969e4 259 fsl,drive-strength = <0>;
8fa62e11
MV		 260 fsl,voltage = <1>;
261 fsl,pull-up = <0>;
262 };
263
264 auart0_2pins_a: auart0-2pins@0 {
265 reg = <0>;
266 fsl,pinmux-ids = <
267 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
268 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
269 >;
270 fsl,drive-strength = <0>;
80d969e4
FE		 271 fsl,voltage = <1>;
272 fsl,pull-up = <0>;
273 };
274
e1a4d18f
SG		 275 auart1_pins_a: auart1@0 {
276 reg = <0>;
277 fsl,pinmux-ids = <
278 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
279 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
280 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
281 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
282 >;
283 fsl,drive-strength = <0>;
284 fsl,voltage = <1>;
285 fsl,pull-up = <0>;
286 };
287
3143bbb4
SG		 288 auart1_2pins_a: auart1-2pins@0 {
289 reg = <0>;
290 fsl,pinmux-ids = <
291 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
292 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
293 >;
294 fsl,drive-strength = <0>;
295 fsl,voltage = <1>;
296 fsl,pull-up = <0>;
297 };
298
299 auart2_2pins_a: auart2-2pins@0 {
300 reg = <0>;
301 fsl,pinmux-ids = <
302 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
303 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
304 >;
305 fsl,drive-strength = <0>;
306 fsl,voltage = <1>;
307 fsl,pull-up = <0>;
308 };
309
80d969e4
FE		 310 auart3_pins_a: auart3@0 {
311 reg = <0>;
f14da767
SG		 312 fsl,pinmux-ids = <
313 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
314 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
315 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
316 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
317 >;
80d969e4
FE		 318 fsl,drive-strength = <0>;
319 fsl,voltage = <1>;
320 fsl,pull-up = <0>;
321 };
322
3143bbb4
SG		 323 auart3_2pins_a: auart3-2pins@0 {
324 reg = <0>;
325 fsl,pinmux-ids = <
326 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
327 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
328 >;
329 fsl,drive-strength = <0>;
330 fsl,voltage = <1>;
331 fsl,pull-up = <0>;
332 };
333
bc3a59c1
DA		 334 mac0_pins_a: mac0@0 {
335 reg = <0>;
f14da767
SG		 336 fsl,pinmux-ids = <
337 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
338 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
339 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
340 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
341 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
342 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
343 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
344 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
345 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
346 >;
bc3a59c1
DA		 347 fsl,drive-strength = <1>;
348 fsl,voltage = <1>;
349 fsl,pull-up = <1>;
350 };
351
352 mac1_pins_a: mac1@0 {
353 reg = <0>;
f14da767
SG		 354 fsl,pinmux-ids = <
355 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
356 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
357 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
358 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
359 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
360 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
361 >;
bc3a59c1
DA		 362 fsl,drive-strength = <1>;
363 fsl,voltage = <1>;
364 fsl,pull-up = <1>;
365 };
35d23047
SG		 366
367 mmc0_8bit_pins_a: mmc0-8bit@0 {
368 reg = <0>;
f14da767
SG		 369 fsl,pinmux-ids = <
370 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
371 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
372 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
373 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
374 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
375 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
376 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
377 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
378 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
379 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
380 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
381 >;
35d23047
SG		 382 fsl,drive-strength = <1>;
383 fsl,voltage = <1>;
384 fsl,pull-up = <1>;
385 };
386
8385e7c1
MR		 387 mmc0_4bit_pins_a: mmc0-4bit@0 {
388 reg = <0>;
f14da767
SG		 389 fsl,pinmux-ids = <
390 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
391 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
392 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
393 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
394 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
395 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
396 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
397 >;
8385e7c1
MR		 398 fsl,drive-strength = <1>;
399 fsl,voltage = <1>;
400 fsl,pull-up = <1>;
401 };
402
35d23047 403 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767
SG		 404 fsl,pinmux-ids = <
405 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
406 >;
35d23047
SG		 407 fsl,pull-up = <0>;
408 };
409
410 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767
SG		 411 fsl,pinmux-ids = <
412 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
413 >;
35d23047
SG		 414 fsl,drive-strength = <2>;
415 fsl,pull-up = <0>;
416 };
2a96e391
SG		 417
418 i2c0_pins_a: i2c0@0 {
419 reg = <0>;
f14da767
SG		 420 fsl,pinmux-ids = <
421 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
422 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
423 >;
2a96e391
SG		 424 fsl,drive-strength = <1>;
425 fsl,voltage = <1>;
426 fsl,pull-up = <1>;
427 };
530f1d41 428
5c697ea2
MR		 429 i2c0_pins_b: i2c0@1 {
430 reg = <1>;
431 fsl,pinmux-ids = <
432 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
433 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
434 >;
435 fsl,drive-strength = <1>;
436 fsl,voltage = <1>;
437 fsl,pull-up = <1>;
438 };
439
de7e934f
MR		 440 i2c1_pins_a: i2c1@0 {
441 reg = <0>;
442 fsl,pinmux-ids = <
443 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
444 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
445 >;
446 fsl,drive-strength = <1>;
447 fsl,voltage = <1>;
448 fsl,pull-up = <1>;
449 };
450
530f1d41
SG		 451 saif0_pins_a: saif0@0 {
452 reg = <0>;
f14da767
SG		 453 fsl,pinmux-ids = <
454 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
455 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
456 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
457 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
458 >;
530f1d41
SG		 459 fsl,drive-strength = <2>;
460 fsl,voltage = <1>;
461 fsl,pull-up = <1>;
462 };
463
464 saif1_pins_a: saif1@0 {
465 reg = <0>;
f14da767
SG		 466 fsl,pinmux-ids = <
467 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
468 >;
530f1d41
SG		 469 fsl,drive-strength = <2>;
470 fsl,voltage = <1>;
471 fsl,pull-up = <1>;
472 };
52f7176b 473
e1a4d18f
SG		 474 pwm0_pins_a: pwm0@0 {
475 reg = <0>;
476 fsl,pinmux-ids = <
477 0x3100 /* MX28_PAD_PWM0__PWM_0 */
478 >;
479 fsl,drive-strength = <0>;
480 fsl,voltage = <1>;
481 fsl,pull-up = <0>;
482 };
483
52f7176b
SG		 484 pwm2_pins_a: pwm2@0 {
485 reg = <0>;
486 fsl,pinmux-ids = <
487 0x3120 /* MX28_PAD_PWM2__PWM_2 */
488 >;
489 fsl,drive-strength = <0>;
490 fsl,voltage = <1>;
491 fsl,pull-up = <0>;
492 };
a915ee42 493
2bde51cb
JB		 494 pwm3_pins_a: pwm3@0 {
495 reg = <0>;
496 fsl,pinmux-ids = <
497 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
498 >;
499 fsl,drive-strength = <0>;
500 fsl,voltage = <1>;
501 fsl,pull-up = <0>;
502 };
503
2f44211f
MR		 504 pwm4_pins_a: pwm4@0 {
505 reg = <0>;
506 fsl,pinmux-ids = <
507 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
508 >;
509 fsl,drive-strength = <0>;
510 fsl,voltage = <1>;
511 fsl,pull-up = <0>;
512 };
513
a915ee42
SG		 514 lcdif_24bit_pins_a: lcdif-24bit@0 {
515 reg = <0>;
516 fsl,pinmux-ids = <
517 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
518 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
519 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
520 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
521 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
522 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
523 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
524 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
525 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
526 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
527 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
528 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
529 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
530 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
531 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
532 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
533 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
534 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
535 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
536 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
537 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
538 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
539 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
540 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
a915ee42
SG		 541 >;
542 fsl,drive-strength = <0>;
543 fsl,voltage = <1>;
544 fsl,pull-up = <0>;
545 };
6ca44acf
SG		 546
547 can0_pins_a: can0@0 {
548 reg = <0>;
549 fsl,pinmux-ids = <
550 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
551 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
552 >;
553 fsl,drive-strength = <0>;
554 fsl,voltage = <1>;
555 fsl,pull-up = <0>;
556 };
557
558 can1_pins_a: can1@0 {
559 reg = <0>;
560 fsl,pinmux-ids = <
561 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
562 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
563 >;
564 fsl,drive-strength = <0>;
565 fsl,voltage = <1>;
566 fsl,pull-up = <0>;
567 };
7f122213
MV		 568
569 spi2_pins_a: spi2@0 {
570 reg = <0>;
571 fsl,pinmux-ids = <
572 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
573 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
574 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
575 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
576 >;
577 fsl,drive-strength = <1>;
578 fsl,voltage = <1>;
579 fsl,pull-up = <1>;
580 };
bb2f1261
MV		 581
582 usbphy0_pins_a: usbphy0@0 {
583 reg = <0>;
584 fsl,pinmux-ids = <
585 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
586 >;
587 fsl,drive-strength = <2>;
588 fsl,voltage = <1>;
589 fsl,pull-up = <0>;
590 };
591
592 usbphy0_pins_b: usbphy0@1 {
593 reg = <1>;
594 fsl,pinmux-ids = <
595 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
596 >;
597 fsl,drive-strength = <2>;
598 fsl,voltage = <1>;
599 fsl,pull-up = <0>;
600 };
601
602 usbphy1_pins_a: usbphy1@0 {
603 reg = <0>;
604 fsl,pinmux-ids = <
605 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
606 >;
607 fsl,drive-strength = <2>;
608 fsl,voltage = <1>;
609 fsl,pull-up = <0>;
610 };
bc3a59c1
DA		 611 };
612
613 digctl@8001c000 {
0f06cde7 614 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 615 interrupts = <89>;
616 status = "disabled";
617 };
618
619 etm@80022000 {
0f06cde7 620 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 621 status = "disabled";
622 };
623
624 dma-apbx@80024000 {
84f3570a 625 compatible = "fsl,imx28-dma-apbx";
0f06cde7 626 reg = <0x80024000 0x2000>;
b598b9f3 627 clocks = <&clks 26>;
bc3a59c1
DA		 628 };
629
630 dcp@80028000 {
0f06cde7 631 reg = <0x80028000 0x2000>;
bc3a59c1
DA		 632 interrupts = <52 53 54>;
633 status = "disabled";
634 };
635
636 pxp@8002a000 {
0f06cde7 637 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 638 interrupts = <39>;
639 status = "disabled";
640 };
641
642 ocotp@8002c000 {
0f06cde7 643 reg = <0x8002c000 0x2000>;
bc3a59c1
DA		 644 status = "disabled";
645 };
646
647 axi-ahb@8002e000 {
0f06cde7 648 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 649 status = "disabled";
650 };
651
652 lcdif@80030000 {
a915ee42 653 compatible = "fsl,imx28-lcdif";
0f06cde7 654 reg = <0x80030000 0x2000>;
bc3a59c1 655 interrupts = <38 86>;
b598b9f3 656 clocks = <&clks 55>;
bc3a59c1
DA		 657 status = "disabled";
658 };
659
660 can0: can@80032000 {
6ca44acf 661 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 662 reg = <0x80032000 0x2000>;
bc3a59c1 663 interrupts = <8>;
b598b9f3
SG		 664 clocks = <&clks 58>, <&clks 58>;
665 clock-names = "ipg", "per";
bc3a59c1
DA		 666 status = "disabled";
667 };
668
669 can1: can@80034000 {
6ca44acf 670 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 671 reg = <0x80034000 0x2000>;
bc3a59c1 672 interrupts = <9>;
b598b9f3
SG		 673 clocks = <&clks 59>, <&clks 59>;
674 clock-names = "ipg", "per";
bc3a59c1
DA		 675 status = "disabled";
676 };
677
678 simdbg@8003c000 {
0f06cde7 679 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 680 status = "disabled";
681 };
682
683 simgpmisel@8003c200 {
0f06cde7 684 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 685 status = "disabled";
686 };
687
688 simsspsel@8003c300 {
0f06cde7 689 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 690 status = "disabled";
691 };
692
693 simmemsel@8003c400 {
0f06cde7 694 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 695 status = "disabled";
696 };
697
698 gpiomon@8003c500 {
0f06cde7 699 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 700 status = "disabled";
701 };
702
703 simenet@8003c700 {
0f06cde7 704 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 705 status = "disabled";
706 };
707
708 armjtag@8003c800 {
0f06cde7 709 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 710 status = "disabled";
711 };
712 };
713
714 apbx@80040000 {
715 compatible = "simple-bus";
716 #address-cells = <1>;
717 #size-cells = <1>;
718 reg = <0x80040000 0x40000>;
719 ranges;
720
b598b9f3
SG		 721 clks: clkctrl@80040000 {
722 compatible = "fsl,imx28-clkctrl";
0f06cde7 723 reg = <0x80040000 0x2000>;
b598b9f3 724 #clock-cells = <1>;
bc3a59c1
DA		 725 };
726
727 saif0: saif@80042000 {
530f1d41 728 compatible = "fsl,imx28-saif";
0f06cde7 729 reg = <0x80042000 0x2000>;
bc3a59c1 730 interrupts = <59 80>;
b598b9f3 731 clocks = <&clks 53>;
530f1d41 732 fsl,saif-dma-channel = <4>;
bc3a59c1
DA		 733 status = "disabled";
734 };
735
736 power@80044000 {
0f06cde7 737 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 738 status = "disabled";
739 };
740
741 saif1: saif@80046000 {
530f1d41 742 compatible = "fsl,imx28-saif";
0f06cde7 743 reg = <0x80046000 0x2000>;
bc3a59c1 744 interrupts = <58 81>;
b598b9f3 745 clocks = <&clks 54>;
530f1d41 746 fsl,saif-dma-channel = <5>;
bc3a59c1
DA		 747 status = "disabled";
748 };
749
750 lradc@80050000 {
aef35104 751 compatible = "fsl,imx28-lradc";
0f06cde7 752 reg = <0x80050000 0x2000>;
aef35104
MV		 753 interrupts = <10 14 15 16 17 18 19
754 20 21 22 23 24 25>;
bc3a59c1
DA		 755 status = "disabled";
756 };
757
758 spdif@80054000 {
0f06cde7 759 reg = <0x80054000 0x2000>;
bc3a59c1
DA		 760 interrupts = <45 66>;
761 status = "disabled";
762 };
763
764 rtc@80056000 {
f98c990c 765 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 766 reg = <0x80056000 0x2000>;
f98c990c 767 interrupts = <29>;
bc3a59c1
DA		 768 };
769
770 i2c0: i2c@80058000 {
2a96e391
SG		 771 #address-cells = <1>;
772 #size-cells = <0>;
773 compatible = "fsl,imx28-i2c";
0f06cde7 774 reg = <0x80058000 0x2000>;
bc3a59c1 775 interrupts = <111 68>;
cd4f2d4a 776 clock-frequency = <100000>;
62885f59 777 fsl,i2c-dma-channel = <6>;
bc3a59c1
DA		 778 status = "disabled";
779 };
780
781 i2c1: i2c@8005a000 {
2a96e391
SG		 782 #address-cells = <1>;
783 #size-cells = <0>;
784 compatible = "fsl,imx28-i2c";
0f06cde7 785 reg = <0x8005a000 0x2000>;
bc3a59c1 786 interrupts = <110 69>;
cd4f2d4a 787 clock-frequency = <100000>;
62885f59 788 fsl,i2c-dma-channel = <7>;
bc3a59c1
DA		 789 status = "disabled";
790 };
791
52f7176b
SG		 792 pwm: pwm@80064000 {
793 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 794 reg = <0x80064000 0x2000>;
b598b9f3 795 clocks = <&clks 44>;
52f7176b
SG		 796 #pwm-cells = <2>;
797 fsl,pwm-number = <8>;
bc3a59c1
DA		 798 status = "disabled";
799 };
800
801 timrot@80068000 {
eeca6e60 802 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 803 reg = <0x80068000 0x2000>;
eeca6e60 804 interrupts = <48 49 50 51>;
bc3a59c1
DA		 805 };
806
807 auart0: serial@8006a000 {
80d969e4 808 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 809 reg = <0x8006a000 0x2000>;
810 interrupts = <112 70 71>;
b598b9f3 811 clocks = <&clks 45>;
bc3a59c1
DA		 812 status = "disabled";
813 };
814
815 auart1: serial@8006c000 {
80d969e4 816 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 817 reg = <0x8006c000 0x2000>;
818 interrupts = <113 72 73>;
b598b9f3 819 clocks = <&clks 45>;
bc3a59c1
DA		 820 status = "disabled";
821 };
822
823 auart2: serial@8006e000 {
80d969e4 824 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 825 reg = <0x8006e000 0x2000>;
826 interrupts = <114 74 75>;
b598b9f3 827 clocks = <&clks 45>;
bc3a59c1
DA		 828 status = "disabled";
829 };
830
831 auart3: serial@80070000 {
80d969e4 832 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 833 reg = <0x80070000 0x2000>;
834 interrupts = <115 76 77>;
b598b9f3 835 clocks = <&clks 45>;
bc3a59c1
DA		 836 status = "disabled";
837 };
838
839 auart4: serial@80072000 {
80d969e4 840 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 841 reg = <0x80072000 0x2000>;
842 interrupts = <116 78 79>;
b598b9f3 843 clocks = <&clks 45>;
bc3a59c1
DA		 844 status = "disabled";
845 };
846
847 duart: serial@80074000 {
848 compatible = "arm,pl011", "arm,primecell";
849 reg = <0x80074000 0x1000>;
850 interrupts = <47>;
b598b9f3
SG		 851 clocks = <&clks 45>, <&clks 26>;
852 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 853 status = "disabled";
854 };
855
856 usbphy0: usbphy@8007c000 {
5da01270 857 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 858 reg = <0x8007c000 0x2000>;
b598b9f3 859 clocks = <&clks 62>;
bc3a59c1
DA		 860 status = "disabled";
861 };
862
863 usbphy1: usbphy@8007e000 {
5da01270 864 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 865 reg = <0x8007e000 0x2000>;
b598b9f3 866 clocks = <&clks 63>;
bc3a59c1
DA		 867 status = "disabled";
868 };
869 };
870 };
871
872 ahb@80080000 {
873 compatible = "simple-bus";
874 #address-cells = <1>;
875 #size-cells = <1>;
876 reg = <0x80080000 0x80000>;
877 ranges;
878
5da01270
RZ		 879 usb0: usb@80080000 {
880 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 881 reg = <0x80080000 0x10000>;
5da01270 882 interrupts = <93>;
b598b9f3 883 clocks = <&clks 60>;
5da01270 884 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 885 status = "disabled";
886 };
887
5da01270
RZ		 888 usb1: usb@80090000 {
889 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 890 reg = <0x80090000 0x10000>;
5da01270 891 interrupts = <92>;
b598b9f3 892 clocks = <&clks 61>;
5da01270 893 fsl,usbphy = <&usbphy1>;
bc3a59c1
DA		 894 status = "disabled";
895 };
896
897 dflpt@800c0000 {
898 reg = <0x800c0000 0x10000>;
899 status = "disabled";
900 };
901
902 mac0: ethernet@800f0000 {
903 compatible = "fsl,imx28-fec";
904 reg = <0x800f0000 0x4000>;
905 interrupts = <101>;
b598b9f3
SG		 906 clocks = <&clks 57>, <&clks 57>;
907 clock-names = "ipg", "ahb";
bc3a59c1
DA		 908 status = "disabled";
909 };
910
911 mac1: ethernet@800f4000 {
912 compatible = "fsl,imx28-fec";
913 reg = <0x800f4000 0x4000>;
914 interrupts = <102>;
b598b9f3
SG		 915 clocks = <&clks 57>, <&clks 57>;
916 clock-names = "ipg", "ahb";
bc3a59c1
DA		 917 status = "disabled";
918 };
919
920 switch@800f8000 {
921 reg = <0x800f8000 0x8000>;
922 status = "disabled";
923 };
924
925 };
926};
Linux 6.x block layer and io_uring tree(s)