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Merge tag 'amlogic-dt-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman...
[linux-2.6-block.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
241f76b2
FE		 1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
bc3a59c1 4
25fc228e 5#include <dt-bindings/gpio/gpio.h>
bc3875f1 6#include "imx28-pinfunc.h"
bc3a59c1
DA		 7
8/ {
7f107887
FE		 9 #address-cells = <1>;
10 #size-cells = <1>;
11
bc3a59c1 12 interrupt-parent = <&icoll>;
a971c554
FE		 13 /*
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
17 * Also for U-Boot there must be a pre-existing /memory node.
18 */
19 chosen {};
7f08e6aa 20 memory { device_type = "memory"; };
bc3a59c1 21
ce4c6f9b 22 aliases {
6bf6eb09
FE		 23 ethernet0 = &mac0;
24 ethernet1 = &mac1;
ce4c6f9b
SG		 25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 gpio2 = &gpio2;
28 gpio3 = &gpio3;
29 gpio4 = &gpio4;
530f1d41
SG		 30 saif0 = &saif0;
31 saif1 = &saif1;
80d969e4
FE		 32 serial0 = &auart0;
33 serial1 = &auart1;
34 serial2 = &auart2;
35 serial3 = &auart3;
36 serial4 = &auart4;
6bf6eb09
FE		 37 spi0 = &ssp1;
38 spi1 = &ssp2;
1f35cc6a
PC		 39 usbphy0 = &usbphy0;
40 usbphy1 = &usbphy1;
ce4c6f9b
SG		 41 };
42
bc3a59c1 43 cpus {
d447dd88 44 #address-cells = <1>;
7925e89f
LP		 45 #size-cells = <0>;
46
d447dd88 47 cpu@0 {
7925e89f
LP		 48 compatible = "arm,arm926ej-s";
49 device_type = "cpu";
d447dd88 50 reg = <0>;
bc3a59c1
DA		 51 };
52 };
53
54 apb@80000000 {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 reg = <0x80000000 0x80000>;
59 ranges;
60
61 apbh@80000000 {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x80000000 0x3c900>;
66 ranges;
67
68 icoll: interrupt-controller@80000000 {
83a84efc 69 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 70 interrupt-controller;
71 #interrupt-cells = <1>;
72 reg = <0x80000000 0x2000>;
73 };
74
296f8cd3 75 hsadc: hsadc@80002000 {
0f06cde7 76 reg = <0x80002000 0x2000>;
7f2b9288 77 interrupts = <13>;
f30fb03d
SG		 78 dmas = <&dma_apbh 12>;
79 dma-names = "rx";
bc3a59c1
DA		 80 status = "disabled";
81 };
82
f30fb03d 83 dma_apbh: dma-apbh@80004000 {
84f3570a 84 compatible = "fsl,imx28-dma-apbh";
0f06cde7 85 reg = <0x80004000 0x2000>;
f30fb03d
SG		 86 interrupts = <82 83 84 85
87 88 88 88 88
88 88 88 88 88
89 87 86 0 0>;
90 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
91 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
92 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
93 "hsadc", "lcdif", "empty", "empty";
94 #dma-cells = <1>;
95 dma-channels = <16>;
b598b9f3 96 clocks = <&clks 25>;
bc3a59c1
DA		 97 };
98
296f8cd3 99 perfmon: perfmon@80006000 {
0f06cde7 100 reg = <0x80006000 0x800>;
bc3a59c1
DA		 101 interrupts = <27>;
102 status = "disabled";
103 };
104
296f8cd3 105 gpmi: gpmi-nand@8000c000 {
7a8e5149
HS		 106 compatible = "fsl,imx28-gpmi-nand";
107 #address-cells = <1>;
108 #size-cells = <1>;
0f06cde7 109 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149 110 reg-names = "gpmi-nand", "bch";
7f2b9288
SG		 111 interrupts = <41>;
112 interrupt-names = "bch";
b598b9f3 113 clocks = <&clks 50>;
b6442559 114 clock-names = "gpmi_io";
f30fb03d
SG		 115 dmas = <&dma_apbh 4>;
116 dma-names = "rx-tx";
bc3a59c1
DA		 117 status = "disabled";
118 };
119
120 ssp0: ssp@80010000 {
41bf5706
MR		 121 #address-cells = <1>;
122 #size-cells = <0>;
0f06cde7 123 reg = <0x80010000 0x2000>;
7f2b9288 124 interrupts = <96>;
b598b9f3 125 clocks = <&clks 46>;
f30fb03d
SG		 126 dmas = <&dma_apbh 0>;
127 dma-names = "rx-tx";
bc3a59c1
DA		 128 status = "disabled";
129 };
130
131 ssp1: ssp@80012000 {
41bf5706
MR		 132 #address-cells = <1>;
133 #size-cells = <0>;
0f06cde7 134 reg = <0x80012000 0x2000>;
7f2b9288 135 interrupts = <97>;
b598b9f3 136 clocks = <&clks 47>;
f30fb03d
SG		 137 dmas = <&dma_apbh 1>;
138 dma-names = "rx-tx";
bc3a59c1
DA		 139 status = "disabled";
140 };
141
142 ssp2: ssp@80014000 {
41bf5706
MR		 143 #address-cells = <1>;
144 #size-cells = <0>;
0f06cde7 145 reg = <0x80014000 0x2000>;
7f2b9288 146 interrupts = <98>;
b598b9f3 147 clocks = <&clks 48>;
f30fb03d
SG		 148 dmas = <&dma_apbh 2>;
149 dma-names = "rx-tx";
bc3a59c1
DA		 150 status = "disabled";
151 };
152
153 ssp3: ssp@80016000 {
41bf5706
MR		 154 #address-cells = <1>;
155 #size-cells = <0>;
0f06cde7 156 reg = <0x80016000 0x2000>;
7f2b9288 157 interrupts = <99>;
b598b9f3 158 clocks = <&clks 49>;
f30fb03d
SG		 159 dmas = <&dma_apbh 3>;
160 dma-names = "rx-tx";
bc3a59c1
DA		 161 status = "disabled";
162 };
163
296f8cd3 164 pinctrl: pinctrl@80018000 {
bc3a59c1
DA		 165 #address-cells = <1>;
166 #size-cells = <0>;
ce4c6f9b 167 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 168 reg = <0x80018000 0x2000>;
bc3a59c1 169
ce4c6f9b
SG		 170 gpio0: gpio@0 {
171 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 172 reg = <0>;
ce4c6f9b
SG		 173 interrupts = <127>;
174 gpio-controller;
175 #gpio-cells = <2>;
176 interrupt-controller;
177 #interrupt-cells = <2>;
178 };
179
180 gpio1: gpio@1 {
181 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 182 reg = <1>;
ce4c6f9b
SG		 183 interrupts = <126>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 };
189
190 gpio2: gpio@2 {
191 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 192 reg = <2>;
ce4c6f9b
SG		 193 interrupts = <125>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
198 };
199
200 gpio3: gpio@3 {
201 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 202 reg = <3>;
ce4c6f9b
SG		 203 interrupts = <124>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
208 };
209
210 gpio4: gpio@4 {
211 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 212 reg = <4>;
ce4c6f9b
SG		 213 interrupts = <123>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 };
219
bc3a59c1
DA		 220 duart_pins_a: duart@0 {
221 reg = <0>;
f14da767 222 fsl,pinmux-ids = <
bc3875f1
LW		 223 MX28_PAD_PWM0__DUART_RX
224 MX28_PAD_PWM1__DUART_TX
f14da767 225 >;
4191c340
LW		 226 fsl,drive-strength = <MXS_DRIVE_4mA>;
227 fsl,voltage = <MXS_VOLTAGE_HIGH>;
228 fsl,pull-up = <MXS_PULL_DISABLE>;
bc3a59c1
DA		 229 };
230
8385e7c1
MR		 231 duart_pins_b: duart@1 {
232 reg = <1>;
f14da767 233 fsl,pinmux-ids = <
bc3875f1
LW		 234 MX28_PAD_AUART0_CTS__DUART_RX
235 MX28_PAD_AUART0_RTS__DUART_TX
f14da767 236 >;
4191c340
LW		 237 fsl,drive-strength = <MXS_DRIVE_4mA>;
238 fsl,voltage = <MXS_VOLTAGE_HIGH>;
239 fsl,pull-up = <MXS_PULL_DISABLE>;
8385e7c1
MR		 240 };
241
e1a4d18f
SG		 242 duart_4pins_a: duart-4pins@0 {
243 reg = <0>;
244 fsl,pinmux-ids = <
bc3875f1
LW		 245 MX28_PAD_AUART0_CTS__DUART_RX
246 MX28_PAD_AUART0_RTS__DUART_TX
247 MX28_PAD_AUART0_RX__DUART_CTS
248 MX28_PAD_AUART0_TX__DUART_RTS
e1a4d18f 249 >;
4191c340
LW		 250 fsl,drive-strength = <MXS_DRIVE_4mA>;
251 fsl,voltage = <MXS_VOLTAGE_HIGH>;
252 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 253 };
254
7a8e5149
HS		 255 gpmi_pins_a: gpmi-nand@0 {
256 reg = <0>;
f14da767 257 fsl,pinmux-ids = <
bc3875f1
LW		 258 MX28_PAD_GPMI_D00__GPMI_D0
259 MX28_PAD_GPMI_D01__GPMI_D1
260 MX28_PAD_GPMI_D02__GPMI_D2
261 MX28_PAD_GPMI_D03__GPMI_D3
262 MX28_PAD_GPMI_D04__GPMI_D4
263 MX28_PAD_GPMI_D05__GPMI_D5
264 MX28_PAD_GPMI_D06__GPMI_D6
265 MX28_PAD_GPMI_D07__GPMI_D7
266 MX28_PAD_GPMI_CE0N__GPMI_CE0N
267 MX28_PAD_GPMI_RDY0__GPMI_READY0
268 MX28_PAD_GPMI_RDN__GPMI_RDN
269 MX28_PAD_GPMI_WRN__GPMI_WRN
270 MX28_PAD_GPMI_ALE__GPMI_ALE
271 MX28_PAD_GPMI_CLE__GPMI_CLE
272 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 273 >;
4191c340
LW		 274 fsl,drive-strength = <MXS_DRIVE_4mA>;
275 fsl,voltage = <MXS_VOLTAGE_HIGH>;
276 fsl,pull-up = <MXS_PULL_DISABLE>;
7a8e5149
HS		 277 };
278
497b90db
FE		 279 gpmi_status_cfg: gpmi-status-cfg@0 {
280 reg = <0>;
f14da767 281 fsl,pinmux-ids = <
bc3875f1
LW		 282 MX28_PAD_GPMI_RDN__GPMI_RDN
283 MX28_PAD_GPMI_WRN__GPMI_WRN
284 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 285 >;
4191c340 286 fsl,drive-strength = <MXS_DRIVE_12mA>;
7a8e5149
HS		 287 };
288
80d969e4
FE		 289 auart0_pins_a: auart0@0 {
290 reg = <0>;
f14da767 291 fsl,pinmux-ids = <
bc3875f1
LW		 292 MX28_PAD_AUART0_RX__AUART0_RX
293 MX28_PAD_AUART0_TX__AUART0_TX
294 MX28_PAD_AUART0_CTS__AUART0_CTS
295 MX28_PAD_AUART0_RTS__AUART0_RTS
f14da767 296 >;
4191c340
LW		 297 fsl,drive-strength = <MXS_DRIVE_4mA>;
298 fsl,voltage = <MXS_VOLTAGE_HIGH>;
299 fsl,pull-up = <MXS_PULL_DISABLE>;
8fa62e11
MV		 300 };
301
302 auart0_2pins_a: auart0-2pins@0 {
303 reg = <0>;
304 fsl,pinmux-ids = <
bc3875f1
LW		 305 MX28_PAD_AUART0_RX__AUART0_RX
306 MX28_PAD_AUART0_TX__AUART0_TX
8fa62e11 307 >;
4191c340
LW		 308 fsl,drive-strength = <MXS_DRIVE_4mA>;
309 fsl,voltage = <MXS_VOLTAGE_HIGH>;
310 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 311 };
312
e1a4d18f
SG		 313 auart1_pins_a: auart1@0 {
314 reg = <0>;
315 fsl,pinmux-ids = <
bc3875f1
LW		 316 MX28_PAD_AUART1_RX__AUART1_RX
317 MX28_PAD_AUART1_TX__AUART1_TX
318 MX28_PAD_AUART1_CTS__AUART1_CTS
319 MX28_PAD_AUART1_RTS__AUART1_RTS
e1a4d18f 320 >;
4191c340
LW		 321 fsl,drive-strength = <MXS_DRIVE_4mA>;
322 fsl,voltage = <MXS_VOLTAGE_HIGH>;
323 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 324 };
325
3143bbb4
SG		 326 auart1_2pins_a: auart1-2pins@0 {
327 reg = <0>;
328 fsl,pinmux-ids = <
bc3875f1
LW		 329 MX28_PAD_AUART1_RX__AUART1_RX
330 MX28_PAD_AUART1_TX__AUART1_TX
3143bbb4 331 >;
4191c340
LW		 332 fsl,drive-strength = <MXS_DRIVE_4mA>;
333 fsl,voltage = <MXS_VOLTAGE_HIGH>;
334 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 335 };
336
337 auart2_2pins_a: auart2-2pins@0 {
338 reg = <0>;
339 fsl,pinmux-ids = <
bc3875f1
LW		 340 MX28_PAD_SSP2_SCK__AUART2_RX
341 MX28_PAD_SSP2_MOSI__AUART2_TX
3143bbb4 342 >;
4191c340
LW		 343 fsl,drive-strength = <MXS_DRIVE_4mA>;
344 fsl,voltage = <MXS_VOLTAGE_HIGH>;
345 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 346 };
347
f8040cf5
EB		 348 auart2_2pins_b: auart2-2pins@1 {
349 reg = <1>;
350 fsl,pinmux-ids = <
bc3875f1
LW		 351 MX28_PAD_AUART2_RX__AUART2_RX
352 MX28_PAD_AUART2_TX__AUART2_TX
f8040cf5 353 >;
4191c340
LW		 354 fsl,drive-strength = <MXS_DRIVE_4mA>;
355 fsl,voltage = <MXS_VOLTAGE_HIGH>;
356 fsl,pull-up = <MXS_PULL_DISABLE>;
f8040cf5
EB		 357 };
358
cd0214c3
AM		 359 auart2_pins_a: auart2-pins@0 {
360 reg = <0>;
361 fsl,pinmux-ids = <
362 MX28_PAD_AUART2_RX__AUART2_RX
363 MX28_PAD_AUART2_TX__AUART2_TX
364 MX28_PAD_AUART2_CTS__AUART2_CTS
365 MX28_PAD_AUART2_RTS__AUART2_RTS
366 >;
367 fsl,drive-strength = <MXS_DRIVE_4mA>;
368 fsl,voltage = <MXS_VOLTAGE_HIGH>;
369 fsl,pull-up = <MXS_PULL_DISABLE>;
370 };
371
80d969e4
FE		 372 auart3_pins_a: auart3@0 {
373 reg = <0>;
f14da767 374 fsl,pinmux-ids = <
bc3875f1
LW		 375 MX28_PAD_AUART3_RX__AUART3_RX
376 MX28_PAD_AUART3_TX__AUART3_TX
377 MX28_PAD_AUART3_CTS__AUART3_CTS
378 MX28_PAD_AUART3_RTS__AUART3_RTS
f14da767 379 >;
4191c340
LW		 380 fsl,drive-strength = <MXS_DRIVE_4mA>;
381 fsl,voltage = <MXS_VOLTAGE_HIGH>;
382 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 383 };
384
3143bbb4
SG		 385 auart3_2pins_a: auart3-2pins@0 {
386 reg = <0>;
387 fsl,pinmux-ids = <
bc3875f1
LW		 388 MX28_PAD_SSP2_MISO__AUART3_RX
389 MX28_PAD_SSP2_SS0__AUART3_TX
3143bbb4 390 >;
4191c340
LW		 391 fsl,drive-strength = <MXS_DRIVE_4mA>;
392 fsl,voltage = <MXS_VOLTAGE_HIGH>;
393 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 394 };
395
4812e746
EB		 396 auart3_2pins_b: auart3-2pins@1 {
397 reg = <1>;
398 fsl,pinmux-ids = <
bc3875f1
LW		 399 MX28_PAD_AUART3_RX__AUART3_RX
400 MX28_PAD_AUART3_TX__AUART3_TX
4812e746 401 >;
4191c340
LW		 402 fsl,drive-strength = <MXS_DRIVE_4mA>;
403 fsl,voltage = <MXS_VOLTAGE_HIGH>;
404 fsl,pull-up = <MXS_PULL_DISABLE>;
4812e746
EB		 405 };
406
33678d12
EB		 407 auart4_2pins_a: auart4@0 {
408 reg = <0>;
409 fsl,pinmux-ids = <
bc3875f1
LW		 410 MX28_PAD_SSP3_SCK__AUART4_TX
411 MX28_PAD_SSP3_MOSI__AUART4_RX
33678d12 412 >;
4191c340
LW		 413 fsl,drive-strength = <MXS_DRIVE_4mA>;
414 fsl,voltage = <MXS_VOLTAGE_HIGH>;
415 fsl,pull-up = <MXS_PULL_DISABLE>;
33678d12
EB		 416 };
417
cfa1dd99
MR		 418 auart4_2pins_b: auart4@1 {
419 reg = <1>;
420 fsl,pinmux-ids = <
421 MX28_PAD_AUART0_CTS__AUART4_RX
422 MX28_PAD_AUART0_RTS__AUART4_TX
423 >;
424 fsl,drive-strength = <MXS_DRIVE_4mA>;
425 fsl,voltage = <MXS_VOLTAGE_HIGH>;
426 fsl,pull-up = <MXS_PULL_DISABLE>;
427 };
428
bc3a59c1
DA		 429 mac0_pins_a: mac0@0 {
430 reg = <0>;
f14da767 431 fsl,pinmux-ids = <
bc3875f1
LW		 432 MX28_PAD_ENET0_MDC__ENET0_MDC
433 MX28_PAD_ENET0_MDIO__ENET0_MDIO
434 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
435 MX28_PAD_ENET0_RXD0__ENET0_RXD0
436 MX28_PAD_ENET0_RXD1__ENET0_RXD1
437 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
438 MX28_PAD_ENET0_TXD0__ENET0_TXD0
439 MX28_PAD_ENET0_TXD1__ENET0_TXD1
440 MX28_PAD_ENET_CLK__CLKCTRL_ENET
f14da767 441 >;
4191c340
LW		 442 fsl,drive-strength = <MXS_DRIVE_8mA>;
443 fsl,voltage = <MXS_VOLTAGE_HIGH>;
444 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1
DA		 445 };
446
9eb7db1c
UKK		 447 mac0_pins_b: mac0@1 {
448 reg = <1>;
449 fsl,pinmux-ids = <
450 MX28_PAD_ENET0_MDC__ENET0_MDC
451 MX28_PAD_ENET0_MDIO__ENET0_MDIO
452 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
453 MX28_PAD_ENET0_RXD0__ENET0_RXD0
454 MX28_PAD_ENET0_RXD1__ENET0_RXD1
455 MX28_PAD_ENET0_RXD2__ENET0_RXD2
456 MX28_PAD_ENET0_RXD3__ENET0_RXD3
457 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
458 MX28_PAD_ENET0_TXD0__ENET0_TXD0
459 MX28_PAD_ENET0_TXD1__ENET0_TXD1
460 MX28_PAD_ENET0_TXD2__ENET0_TXD2
461 MX28_PAD_ENET0_TXD3__ENET0_TXD3
462 MX28_PAD_ENET_CLK__CLKCTRL_ENET
463 MX28_PAD_ENET0_COL__ENET0_COL
464 MX28_PAD_ENET0_CRS__ENET0_CRS
465 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
466 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
467 >;
468 fsl,drive-strength = <MXS_DRIVE_8mA>;
469 fsl,voltage = <MXS_VOLTAGE_HIGH>;
470 fsl,pull-up = <MXS_PULL_ENABLE>;
471 };
472
bc3a59c1
DA		 473 mac1_pins_a: mac1@0 {
474 reg = <0>;
f14da767 475 fsl,pinmux-ids = <
bc3875f1
LW		 476 MX28_PAD_ENET0_CRS__ENET1_RX_EN
477 MX28_PAD_ENET0_RXD2__ENET1_RXD0
478 MX28_PAD_ENET0_RXD3__ENET1_RXD1
479 MX28_PAD_ENET0_COL__ENET1_TX_EN
480 MX28_PAD_ENET0_TXD2__ENET1_TXD0
481 MX28_PAD_ENET0_TXD3__ENET1_TXD1
f14da767 482 >;
4191c340
LW		 483 fsl,drive-strength = <MXS_DRIVE_8mA>;
484 fsl,voltage = <MXS_VOLTAGE_HIGH>;
485 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1 486 };
35d23047
SG		 487
488 mmc0_8bit_pins_a: mmc0-8bit@0 {
489 reg = <0>;
f14da767 490 fsl,pinmux-ids = <
bc3875f1
LW		 491 MX28_PAD_SSP0_DATA0__SSP0_D0
492 MX28_PAD_SSP0_DATA1__SSP0_D1
493 MX28_PAD_SSP0_DATA2__SSP0_D2
494 MX28_PAD_SSP0_DATA3__SSP0_D3
495 MX28_PAD_SSP0_DATA4__SSP0_D4
496 MX28_PAD_SSP0_DATA5__SSP0_D5
497 MX28_PAD_SSP0_DATA6__SSP0_D6
498 MX28_PAD_SSP0_DATA7__SSP0_D7
499 MX28_PAD_SSP0_CMD__SSP0_CMD
500 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
501 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 502 >;
4191c340
LW		 503 fsl,drive-strength = <MXS_DRIVE_8mA>;
504 fsl,voltage = <MXS_VOLTAGE_HIGH>;
505 fsl,pull-up = <MXS_PULL_ENABLE>;
35d23047
SG		 506 };
507
8385e7c1
MR		 508 mmc0_4bit_pins_a: mmc0-4bit@0 {
509 reg = <0>;
f14da767 510 fsl,pinmux-ids = <
bc3875f1
LW		 511 MX28_PAD_SSP0_DATA0__SSP0_D0
512 MX28_PAD_SSP0_DATA1__SSP0_D1
513 MX28_PAD_SSP0_DATA2__SSP0_D2
514 MX28_PAD_SSP0_DATA3__SSP0_D3
515 MX28_PAD_SSP0_CMD__SSP0_CMD
516 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
517 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 518 >;
4191c340
LW		 519 fsl,drive-strength = <MXS_DRIVE_8mA>;
520 fsl,voltage = <MXS_VOLTAGE_HIGH>;
521 fsl,pull-up = <MXS_PULL_ENABLE>;
8385e7c1
MR		 522 };
523
497b90db
FE		 524 mmc0_cd_cfg: mmc0-cd-cfg@0 {
525 reg = <0>;
f14da767 526 fsl,pinmux-ids = <
bc3875f1 527 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
f14da767 528 >;
4191c340 529 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047
SG		 530 };
531
497b90db
FE		 532 mmc0_sck_cfg: mmc0-sck-cfg@0 {
533 reg = <0>;
f14da767 534 fsl,pinmux-ids = <
bc3875f1 535 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 536 >;
4191c340
LW		 537 fsl,drive-strength = <MXS_DRIVE_12mA>;
538 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 539 };
2a96e391 540
77d6386b
MKB		 541 mmc1_4bit_pins_a: mmc1-4bit@0 {
542 reg = <0>;
543 fsl,pinmux-ids = <
544 MX28_PAD_GPMI_D00__SSP1_D0
545 MX28_PAD_GPMI_D01__SSP1_D1
546 MX28_PAD_GPMI_D02__SSP1_D2
547 MX28_PAD_GPMI_D03__SSP1_D3
548 MX28_PAD_GPMI_RDY1__SSP1_CMD
549 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
550 MX28_PAD_GPMI_WRN__SSP1_SCK
551 >;
552 fsl,drive-strength = <MXS_DRIVE_8mA>;
553 fsl,voltage = <MXS_VOLTAGE_HIGH>;
554 fsl,pull-up = <MXS_PULL_ENABLE>;
555 };
556
497b90db
FE		 557 mmc1_cd_cfg: mmc1-cd-cfg@0 {
558 reg = <0>;
77d6386b
MKB		 559 fsl,pinmux-ids = <
560 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
561 >;
562 fsl,pull-up = <MXS_PULL_DISABLE>;
563 };
564
497b90db
FE		 565 mmc1_sck_cfg: mmc1-sck-cfg@0 {
566 reg = <0>;
77d6386b
MKB		 567 fsl,pinmux-ids = <
568 MX28_PAD_GPMI_WRN__SSP1_SCK
569 >;
570 fsl,drive-strength = <MXS_DRIVE_12mA>;
571 fsl,pull-up = <MXS_PULL_DISABLE>;
572 };
573
574
5550e8e9
MV		 575 mmc2_4bit_pins_a: mmc2-4bit@0 {
576 reg = <0>;
577 fsl,pinmux-ids = <
578 MX28_PAD_SSP0_DATA4__SSP2_D0
579 MX28_PAD_SSP1_SCK__SSP2_D1
580 MX28_PAD_SSP1_CMD__SSP2_D2
581 MX28_PAD_SSP0_DATA5__SSP2_D3
582 MX28_PAD_SSP0_DATA6__SSP2_CMD
583 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
584 MX28_PAD_SSP0_DATA7__SSP2_SCK
585 >;
586 fsl,drive-strength = <MXS_DRIVE_8mA>;
587 fsl,voltage = <MXS_VOLTAGE_HIGH>;
588 fsl,pull-up = <MXS_PULL_ENABLE>;
589 };
590
df93726b
MH		 591 mmc2_4bit_pins_b: mmc2-4bit@1 {
592 reg = <1>;
593 fsl,pinmux-ids = <
594 MX28_PAD_SSP2_SCK__SSP2_SCK
595 MX28_PAD_SSP2_MOSI__SSP2_CMD
596 MX28_PAD_SSP2_MISO__SSP2_D0
597 MX28_PAD_SSP2_SS0__SSP2_D3
598 MX28_PAD_SSP2_SS1__SSP2_D1
599 MX28_PAD_SSP2_SS2__SSP2_D2
600 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
601 >;
602 fsl,drive-strength = <MXS_DRIVE_8mA>;
603 fsl,voltage = <MXS_VOLTAGE_HIGH>;
604 fsl,pull-up = <MXS_PULL_ENABLE>;
605 };
606
497b90db
FE		 607 mmc2_cd_cfg: mmc2-cd-cfg@0 {
608 reg = <0>;
5550e8e9
MV		 609 fsl,pinmux-ids = <
610 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
611 >;
612 fsl,pull-up = <MXS_PULL_DISABLE>;
613 };
614
45e89549
MH		 615 mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
616 reg = <0>;
5550e8e9
MV		 617 fsl,pinmux-ids = <
618 MX28_PAD_SSP0_DATA7__SSP2_SCK
619 >;
620 fsl,drive-strength = <MXS_DRIVE_12mA>;
621 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 622 };
2a96e391 623
620885e8
MH		 624 mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
625 reg = <1>;
626 fsl,pinmux-ids = <
627 MX28_PAD_SSP2_SCK__SSP2_SCK
628 >;
629 fsl,drive-strength = <MXS_DRIVE_12mA>;
630 fsl,pull-up = <MXS_PULL_DISABLE>;
631 };
632
2a96e391
SG		 633 i2c0_pins_a: i2c0@0 {
634 reg = <0>;
f14da767 635 fsl,pinmux-ids = <
bc3875f1
LW		 636 MX28_PAD_I2C0_SCL__I2C0_SCL
637 MX28_PAD_I2C0_SDA__I2C0_SDA
f14da767 638 >;
4191c340
LW		 639 fsl,drive-strength = <MXS_DRIVE_8mA>;
640 fsl,voltage = <MXS_VOLTAGE_HIGH>;
641 fsl,pull-up = <MXS_PULL_ENABLE>;
2a96e391 642 };
530f1d41 643
5c697ea2
MR		 644 i2c0_pins_b: i2c0@1 {
645 reg = <1>;
646 fsl,pinmux-ids = <
bc3875f1
LW		 647 MX28_PAD_AUART0_RX__I2C0_SCL
648 MX28_PAD_AUART0_TX__I2C0_SDA
5c697ea2 649 >;
4191c340
LW		 650 fsl,drive-strength = <MXS_DRIVE_8mA>;
651 fsl,voltage = <MXS_VOLTAGE_HIGH>;
652 fsl,pull-up = <MXS_PULL_ENABLE>;
5c697ea2
MR		 653 };
654
de7e934f
MR		 655 i2c1_pins_a: i2c1@0 {
656 reg = <0>;
657 fsl,pinmux-ids = <
bc3875f1
LW		 658 MX28_PAD_PWM0__I2C1_SCL
659 MX28_PAD_PWM1__I2C1_SDA
de7e934f 660 >;
4191c340
LW		 661 fsl,drive-strength = <MXS_DRIVE_8mA>;
662 fsl,voltage = <MXS_VOLTAGE_HIGH>;
663 fsl,pull-up = <MXS_PULL_ENABLE>;
de7e934f
MR		 664 };
665
17c63dd0
UKK		 666 i2c1_pins_b: i2c1@1 {
667 reg = <1>;
668 fsl,pinmux-ids = <
669 MX28_PAD_AUART2_CTS__I2C1_SCL
670 MX28_PAD_AUART2_RTS__I2C1_SDA
671 >;
672 fsl,drive-strength = <MXS_DRIVE_8mA>;
673 fsl,voltage = <MXS_VOLTAGE_HIGH>;
674 fsl,pull-up = <MXS_PULL_ENABLE>;
675 };
676
530f1d41
SG		 677 saif0_pins_a: saif0@0 {
678 reg = <0>;
f14da767 679 fsl,pinmux-ids = <
bc3875f1
LW		 680 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
681 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
682 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
683 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
f14da767 684 >;
4191c340
LW		 685 fsl,drive-strength = <MXS_DRIVE_12mA>;
686 fsl,voltage = <MXS_VOLTAGE_HIGH>;
687 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41
SG		 688 };
689
2e1dd9fc
LW		 690 saif0_pins_b: saif0@1 {
691 reg = <1>;
692 fsl,pinmux-ids = <
bc3875f1
LW		 693 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
694 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
695 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2e1dd9fc 696 >;
4191c340
LW		 697 fsl,drive-strength = <MXS_DRIVE_12mA>;
698 fsl,voltage = <MXS_VOLTAGE_HIGH>;
699 fsl,pull-up = <MXS_PULL_ENABLE>;
2e1dd9fc
LW		 700 };
701
530f1d41
SG		 702 saif1_pins_a: saif1@0 {
703 reg = <0>;
f14da767 704 fsl,pinmux-ids = <
bc3875f1 705 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
f14da767 706 >;
4191c340
LW		 707 fsl,drive-strength = <MXS_DRIVE_12mA>;
708 fsl,voltage = <MXS_VOLTAGE_HIGH>;
709 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41 710 };
52f7176b 711
e1a4d18f
SG		 712 pwm0_pins_a: pwm0@0 {
713 reg = <0>;
714 fsl,pinmux-ids = <
bc3875f1 715 MX28_PAD_PWM0__PWM_0
e1a4d18f 716 >;
4191c340
LW		 717 fsl,drive-strength = <MXS_DRIVE_4mA>;
718 fsl,voltage = <MXS_VOLTAGE_HIGH>;
719 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 720 };
721
52f7176b
SG		 722 pwm2_pins_a: pwm2@0 {
723 reg = <0>;
724 fsl,pinmux-ids = <
bc3875f1 725 MX28_PAD_PWM2__PWM_2
52f7176b 726 >;
4191c340
LW		 727 fsl,drive-strength = <MXS_DRIVE_4mA>;
728 fsl,voltage = <MXS_VOLTAGE_HIGH>;
729 fsl,pull-up = <MXS_PULL_DISABLE>;
52f7176b 730 };
a915ee42 731
2bde51cb
JB		 732 pwm3_pins_a: pwm3@0 {
733 reg = <0>;
734 fsl,pinmux-ids = <
bc3875f1 735 MX28_PAD_PWM3__PWM_3
2bde51cb 736 >;
4191c340
LW		 737 fsl,drive-strength = <MXS_DRIVE_4mA>;
738 fsl,voltage = <MXS_VOLTAGE_HIGH>;
739 fsl,pull-up = <MXS_PULL_DISABLE>;
2bde51cb
JB		 740 };
741
d248620c
MR		 742 pwm3_pins_b: pwm3@1 {
743 reg = <1>;
744 fsl,pinmux-ids = <
bc3875f1 745 MX28_PAD_SAIF0_MCLK__PWM_3
d248620c 746 >;
4191c340
LW		 747 fsl,drive-strength = <MXS_DRIVE_4mA>;
748 fsl,voltage = <MXS_VOLTAGE_HIGH>;
749 fsl,pull-up = <MXS_PULL_DISABLE>;
d248620c
MR		 750 };
751
2f44211f
MR		 752 pwm4_pins_a: pwm4@0 {
753 reg = <0>;
754 fsl,pinmux-ids = <
bc3875f1 755 MX28_PAD_PWM4__PWM_4
2f44211f 756 >;
4191c340
LW		 757 fsl,drive-strength = <MXS_DRIVE_4mA>;
758 fsl,voltage = <MXS_VOLTAGE_HIGH>;
759 fsl,pull-up = <MXS_PULL_DISABLE>;
2f44211f
MR		 760 };
761
a915ee42
SG		 762 lcdif_24bit_pins_a: lcdif-24bit@0 {
763 reg = <0>;
764 fsl,pinmux-ids = <
bc3875f1
LW		 765 MX28_PAD_LCD_D00__LCD_D0
766 MX28_PAD_LCD_D01__LCD_D1
767 MX28_PAD_LCD_D02__LCD_D2
768 MX28_PAD_LCD_D03__LCD_D3
769 MX28_PAD_LCD_D04__LCD_D4
770 MX28_PAD_LCD_D05__LCD_D5
771 MX28_PAD_LCD_D06__LCD_D6
772 MX28_PAD_LCD_D07__LCD_D7
773 MX28_PAD_LCD_D08__LCD_D8
774 MX28_PAD_LCD_D09__LCD_D9
775 MX28_PAD_LCD_D10__LCD_D10
776 MX28_PAD_LCD_D11__LCD_D11
777 MX28_PAD_LCD_D12__LCD_D12
778 MX28_PAD_LCD_D13__LCD_D13
779 MX28_PAD_LCD_D14__LCD_D14
780 MX28_PAD_LCD_D15__LCD_D15
781 MX28_PAD_LCD_D16__LCD_D16
782 MX28_PAD_LCD_D17__LCD_D17
783 MX28_PAD_LCD_D18__LCD_D18
784 MX28_PAD_LCD_D19__LCD_D19
785 MX28_PAD_LCD_D20__LCD_D20
786 MX28_PAD_LCD_D21__LCD_D21
787 MX28_PAD_LCD_D22__LCD_D22
788 MX28_PAD_LCD_D23__LCD_D23
a915ee42 789 >;
4191c340
LW		 790 fsl,drive-strength = <MXS_DRIVE_4mA>;
791 fsl,voltage = <MXS_VOLTAGE_HIGH>;
792 fsl,pull-up = <MXS_PULL_DISABLE>;
a915ee42 793 };
6ca44acf 794
ec985eb2
DC		 795 lcdif_18bit_pins_a: lcdif-18bit@0 {
796 reg = <0>;
797 fsl,pinmux-ids = <
798 MX28_PAD_LCD_D00__LCD_D0
799 MX28_PAD_LCD_D01__LCD_D1
800 MX28_PAD_LCD_D02__LCD_D2
801 MX28_PAD_LCD_D03__LCD_D3
802 MX28_PAD_LCD_D04__LCD_D4
803 MX28_PAD_LCD_D05__LCD_D5
804 MX28_PAD_LCD_D06__LCD_D6
805 MX28_PAD_LCD_D07__LCD_D7
806 MX28_PAD_LCD_D08__LCD_D8
807 MX28_PAD_LCD_D09__LCD_D9
808 MX28_PAD_LCD_D10__LCD_D10
809 MX28_PAD_LCD_D11__LCD_D11
810 MX28_PAD_LCD_D12__LCD_D12
811 MX28_PAD_LCD_D13__LCD_D13
812 MX28_PAD_LCD_D14__LCD_D14
813 MX28_PAD_LCD_D15__LCD_D15
814 MX28_PAD_LCD_D16__LCD_D16
815 MX28_PAD_LCD_D17__LCD_D17
816 >;
817 fsl,drive-strength = <MXS_DRIVE_4mA>;
818 fsl,voltage = <MXS_VOLTAGE_HIGH>;
819 fsl,pull-up = <MXS_PULL_DISABLE>;
820 };
821
4ced2a40
GGM		 822 lcdif_16bit_pins_a: lcdif-16bit@0 {
823 reg = <0>;
824 fsl,pinmux-ids = <
bc3875f1
LW		 825 MX28_PAD_LCD_D00__LCD_D0
826 MX28_PAD_LCD_D01__LCD_D1
827 MX28_PAD_LCD_D02__LCD_D2
828 MX28_PAD_LCD_D03__LCD_D3
829 MX28_PAD_LCD_D04__LCD_D4
830 MX28_PAD_LCD_D05__LCD_D5
831 MX28_PAD_LCD_D06__LCD_D6
832 MX28_PAD_LCD_D07__LCD_D7
833 MX28_PAD_LCD_D08__LCD_D8
834 MX28_PAD_LCD_D09__LCD_D9
835 MX28_PAD_LCD_D10__LCD_D10
836 MX28_PAD_LCD_D11__LCD_D11
837 MX28_PAD_LCD_D12__LCD_D12
838 MX28_PAD_LCD_D13__LCD_D13
839 MX28_PAD_LCD_D14__LCD_D14
840 MX28_PAD_LCD_D15__LCD_D15
4ced2a40 841 >;
4191c340
LW		 842 fsl,drive-strength = <MXS_DRIVE_4mA>;
843 fsl,voltage = <MXS_VOLTAGE_HIGH>;
844 fsl,pull-up = <MXS_PULL_DISABLE>;
4ced2a40
GGM		 845 };
846
23ad6f65
LW		 847 lcdif_sync_pins_a: lcdif-sync@0 {
848 reg = <0>;
849 fsl,pinmux-ids = <
bc3875f1
LW		 850 MX28_PAD_LCD_RS__LCD_DOTCLK
851 MX28_PAD_LCD_CS__LCD_ENABLE
852 MX28_PAD_LCD_RD_E__LCD_VSYNC
853 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
23ad6f65 854 >;
4191c340
LW		 855 fsl,drive-strength = <MXS_DRIVE_4mA>;
856 fsl,voltage = <MXS_VOLTAGE_HIGH>;
857 fsl,pull-up = <MXS_PULL_DISABLE>;
23ad6f65
LW		 858 };
859
6ca44acf
SG		 860 can0_pins_a: can0@0 {
861 reg = <0>;
862 fsl,pinmux-ids = <
bc3875f1
LW		 863 MX28_PAD_GPMI_RDY2__CAN0_TX
864 MX28_PAD_GPMI_RDY3__CAN0_RX
6ca44acf 865 >;
4191c340
LW		 866 fsl,drive-strength = <MXS_DRIVE_4mA>;
867 fsl,voltage = <MXS_VOLTAGE_HIGH>;
868 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf
SG		 869 };
870
871 can1_pins_a: can1@0 {
872 reg = <0>;
873 fsl,pinmux-ids = <
bc3875f1
LW		 874 MX28_PAD_GPMI_CE2N__CAN1_TX
875 MX28_PAD_GPMI_CE3N__CAN1_RX
6ca44acf 876 >;
4191c340
LW		 877 fsl,drive-strength = <MXS_DRIVE_4mA>;
878 fsl,voltage = <MXS_VOLTAGE_HIGH>;
879 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf 880 };
7f122213
MV		 881
882 spi2_pins_a: spi2@0 {
883 reg = <0>;
884 fsl,pinmux-ids = <
bc3875f1
LW		 885 MX28_PAD_SSP2_SCK__SSP2_SCK
886 MX28_PAD_SSP2_MOSI__SSP2_CMD
887 MX28_PAD_SSP2_MISO__SSP2_D0
888 MX28_PAD_SSP2_SS0__SSP2_D3
7f122213 889 >;
4191c340
LW		 890 fsl,drive-strength = <MXS_DRIVE_8mA>;
891 fsl,voltage = <MXS_VOLTAGE_HIGH>;
892 fsl,pull-up = <MXS_PULL_ENABLE>;
7f122213 893 };
bb2f1261 894
3314d2be
LW		 895 spi3_pins_a: spi3@0 {
896 reg = <0>;
897 fsl,pinmux-ids = <
bc3875f1
LW		 898 MX28_PAD_AUART2_RX__SSP3_D4
899 MX28_PAD_AUART2_TX__SSP3_D5
900 MX28_PAD_SSP3_SCK__SSP3_SCK
901 MX28_PAD_SSP3_MOSI__SSP3_CMD
902 MX28_PAD_SSP3_MISO__SSP3_D0
903 MX28_PAD_SSP3_SS0__SSP3_D3
3314d2be 904 >;
4191c340
LW		 905 fsl,drive-strength = <MXS_DRIVE_8mA>;
906 fsl,voltage = <MXS_VOLTAGE_HIGH>;
907 fsl,pull-up = <MXS_PULL_DISABLE>;
3314d2be
LW		 908 };
909
8f0b07a4
UKK		 910 spi3_pins_b: spi3@1 {
911 reg = <1>;
912 fsl,pinmux-ids = <
913 MX28_PAD_SSP3_SCK__SSP3_SCK
914 MX28_PAD_SSP3_MOSI__SSP3_CMD
915 MX28_PAD_SSP3_MISO__SSP3_D0
916 MX28_PAD_SSP3_SS0__SSP3_D3
917 >;
918 fsl,drive-strength = <MXS_DRIVE_8mA>;
919 fsl,voltage = <MXS_VOLTAGE_HIGH>;
920 fsl,pull-up = <MXS_PULL_ENABLE>;
921 };
922
c8e42bc9 923 usb0_pins_a: usb0@0 {
bb2f1261
MV		 924 reg = <0>;
925 fsl,pinmux-ids = <
bc3875f1 926 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
bb2f1261 927 >;
4191c340
LW		 928 fsl,drive-strength = <MXS_DRIVE_12mA>;
929 fsl,voltage = <MXS_VOLTAGE_HIGH>;
930 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 931 };
932
c8e42bc9 933 usb0_pins_b: usb0@1 {
bb2f1261
MV		 934 reg = <1>;
935 fsl,pinmux-ids = <
bc3875f1 936 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
bb2f1261 937 >;
4191c340
LW		 938 fsl,drive-strength = <MXS_DRIVE_12mA>;
939 fsl,voltage = <MXS_VOLTAGE_HIGH>;
940 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 941 };
942
c8e42bc9 943 usb1_pins_a: usb1@0 {
bb2f1261
MV		 944 reg = <0>;
945 fsl,pinmux-ids = <
bc3875f1 946 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
bb2f1261 947 >;
4191c340
LW		 948 fsl,drive-strength = <MXS_DRIVE_12mA>;
949 fsl,voltage = <MXS_VOLTAGE_HIGH>;
950 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261 951 };
69c02f95
FE		 952
953 usb0_id_pins_a: usb0id@0 {
954 reg = <0>;
955 fsl,pinmux-ids = <
e96e1782 956 MX28_PAD_AUART1_RTS__USB0_ID
bb2f1261 957 >;
e96e1782
LW		 958 fsl,drive-strength = <MXS_DRIVE_12mA>;
959 fsl,voltage = <MXS_VOLTAGE_HIGH>;
960 fsl,pull-up = <MXS_PULL_ENABLE>;
bb2f1261 961 };
bb89b8d2
DC		 962
963 usb0_id_pins_b: usb0id1@0 {
964 reg = <0>;
965 fsl,pinmux-ids = <
966 MX28_PAD_PWM2__USB0_ID
967 >;
968 fsl,drive-strength = <MXS_DRIVE_12mA>;
969 fsl,voltage = <MXS_VOLTAGE_HIGH>;
970 fsl,pull-up = <MXS_PULL_ENABLE>;
971 };
972
bc3a59c1
DA		 973 };
974
296f8cd3 975 digctl: digctl@8001c000 {
115581cf 976 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 977 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 978 interrupts = <89>;
979 status = "disabled";
980 };
981
296f8cd3 982 etm: etm@80022000 {
0f06cde7 983 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 984 status = "disabled";
985 };
986
f30fb03d 987 dma_apbx: dma-apbx@80024000 {
84f3570a 988 compatible = "fsl,imx28-dma-apbx";
0f06cde7 989 reg = <0x80024000 0x2000>;
f30fb03d
SG		 990 interrupts = <78 79 66 0
991 80 81 68 69
992 70 71 72 73
993 74 75 76 77>;
4ada77e3 994 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
f30fb03d
SG		 995 "saif0", "saif1", "i2c0", "i2c1",
996 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
997 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
998 #dma-cells = <1>;
999 dma-channels = <16>;
b598b9f3 1000 clocks = <&clks 26>;
bc3a59c1
DA		 1001 };
1002
296f8cd3 1003 dcp: dcp@80028000 {
7d56a28f 1004 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
0f06cde7 1005 reg = <0x80028000 0x2000>;
bc3a59c1 1006 interrupts = <52 53 54>;
7d56a28f 1007 status = "okay";
bc3a59c1
DA		 1008 };
1009
296f8cd3 1010 pxp: pxp@8002a000 {
0f06cde7 1011 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 1012 interrupts = <39>;
1013 status = "disabled";
1014 };
1015
296f8cd3 1016 ocotp: ocotp@8002c000 {
a7be1e68
SW		 1017 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
1018 #address-cells = <1>;
1019 #size-cells = <1>;
0f06cde7 1020 reg = <0x8002c000 0x2000>;
a7be1e68 1021 clocks = <&clks 25>;
bc3a59c1
DA		 1022 };
1023
1024 axi-ahb@8002e000 {
0f06cde7 1025 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 1026 status = "disabled";
1027 };
1028
296f8cd3 1029 lcdif: lcdif@80030000 {
a915ee42 1030 compatible = "fsl,imx28-lcdif";
0f06cde7 1031 reg = <0x80030000 0x2000>;
7f2b9288 1032 interrupts = <38>;
b598b9f3 1033 clocks = <&clks 55>;
f30fb03d
SG		 1034 dmas = <&dma_apbh 13>;
1035 dma-names = "rx";
bc3a59c1
DA		 1036 status = "disabled";
1037 };
1038
1039 can0: can@80032000 {
d50f4630 1040 compatible = "fsl,imx28-flexcan";
0f06cde7 1041 reg = <0x80032000 0x2000>;
bc3a59c1 1042 interrupts = <8>;
b598b9f3
SG		 1043 clocks = <&clks 58>, <&clks 58>;
1044 clock-names = "ipg", "per";
bc3a59c1
DA		 1045 status = "disabled";
1046 };
1047
1048 can1: can@80034000 {
d50f4630 1049 compatible = "fsl,imx28-flexcan";
0f06cde7 1050 reg = <0x80034000 0x2000>;
bc3a59c1 1051 interrupts = <9>;
b598b9f3
SG		 1052 clocks = <&clks 59>, <&clks 59>;
1053 clock-names = "ipg", "per";
bc3a59c1
DA		 1054 status = "disabled";
1055 };
1056
296f8cd3 1057 simdbg: simdbg@8003c000 {
0f06cde7 1058 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 1059 status = "disabled";
1060 };
1061
296f8cd3 1062 simgpmisel: simgpmisel@8003c200 {
0f06cde7 1063 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 1064 status = "disabled";
1065 };
1066
296f8cd3 1067 simsspsel: simsspsel@8003c300 {
0f06cde7 1068 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 1069 status = "disabled";
1070 };
1071
296f8cd3 1072 simmemsel: simmemsel@8003c400 {
0f06cde7 1073 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 1074 status = "disabled";
1075 };
1076
296f8cd3 1077 gpiomon: gpiomon@8003c500 {
0f06cde7 1078 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 1079 status = "disabled";
1080 };
1081
296f8cd3 1082 simenet: simenet@8003c700 {
0f06cde7 1083 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 1084 status = "disabled";
1085 };
1086
296f8cd3 1087 armjtag: armjtag@8003c800 {
0f06cde7 1088 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 1089 status = "disabled";
1090 };
07a3ce7f 1091 };
bc3a59c1
DA		 1092
1093 apbx@80040000 {
1094 compatible = "simple-bus";
1095 #address-cells = <1>;
1096 #size-cells = <1>;
1097 reg = <0x80040000 0x40000>;
1098 ranges;
1099
b598b9f3 1100 clks: clkctrl@80040000 {
8f7cf881 1101 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 1102 reg = <0x80040000 0x2000>;
b598b9f3 1103 #clock-cells = <1>;
bc3a59c1
DA		 1104 };
1105
1106 saif0: saif@80042000 {
27767d68 1107 #sound-dai-cells = <0>;
530f1d41 1108 compatible = "fsl,imx28-saif";
0f06cde7 1109 reg = <0x80042000 0x2000>;
7f2b9288 1110 interrupts = <59>;
66acaf3f 1111 #clock-cells = <0>;
b598b9f3 1112 clocks = <&clks 53>;
f30fb03d
SG		 1113 dmas = <&dma_apbx 4>;
1114 dma-names = "rx-tx";
bc3a59c1
DA		 1115 status = "disabled";
1116 };
1117
296f8cd3 1118 power: power@80044000 {
0f06cde7 1119 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 1120 status = "disabled";
1121 };
1122
1123 saif1: saif@80046000 {
27767d68 1124 #sound-dai-cells = <0>;
530f1d41 1125 compatible = "fsl,imx28-saif";
0f06cde7 1126 reg = <0x80046000 0x2000>;
7f2b9288 1127 interrupts = <58>;
b598b9f3 1128 clocks = <&clks 54>;
f30fb03d
SG		 1129 dmas = <&dma_apbx 5>;
1130 dma-names = "rx-tx";
bc3a59c1
DA		 1131 status = "disabled";
1132 };
1133
296f8cd3 1134 lradc: lradc@80050000 {
aef35104 1135 compatible = "fsl,imx28-lradc";
0f06cde7 1136 reg = <0x80050000 0x2000>;
aef35104
MV		 1137 interrupts = <10 14 15 16 17 18 19
1138 20 21 22 23 24 25>;
bc3a59c1 1139 status = "disabled";
18da755d 1140 clocks = <&clks 41>;
40dde681 1141 #io-channel-cells = <1>;
bc3a59c1
DA		 1142 };
1143
296f8cd3 1144 spdif: spdif@80054000 {
0f06cde7 1145 reg = <0x80054000 0x2000>;
7f2b9288 1146 interrupts = <45>;
f30fb03d
SG		 1147 dmas = <&dma_apbx 2>;
1148 dma-names = "tx";
bc3a59c1
DA		 1149 status = "disabled";
1150 };
1151
296f8cd3 1152 mxs_rtc: rtc@80056000 {
f98c990c 1153 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 1154 reg = <0x80056000 0x2000>;
f98c990c 1155 interrupts = <29>;
bc3a59c1
DA		 1156 };
1157
1158 i2c0: i2c@80058000 {
2a96e391
SG		 1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161 compatible = "fsl,imx28-i2c";
0f06cde7 1162 reg = <0x80058000 0x2000>;
7f2b9288 1163 interrupts = <111>;
cd4f2d4a 1164 clock-frequency = <100000>;
f30fb03d
SG		 1165 dmas = <&dma_apbx 6>;
1166 dma-names = "rx-tx";
bc3a59c1
DA		 1167 status = "disabled";
1168 };
1169
1170 i2c1: i2c@8005a000 {
2a96e391
SG		 1171 #address-cells = <1>;
1172 #size-cells = <0>;
1173 compatible = "fsl,imx28-i2c";
0f06cde7 1174 reg = <0x8005a000 0x2000>;
7f2b9288 1175 interrupts = <110>;
cd4f2d4a 1176 clock-frequency = <100000>;
f30fb03d
SG		 1177 dmas = <&dma_apbx 7>;
1178 dma-names = "rx-tx";
bc3a59c1
DA		 1179 status = "disabled";
1180 };
1181
52f7176b
SG		 1182 pwm: pwm@80064000 {
1183 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 1184 reg = <0x80064000 0x2000>;
b598b9f3 1185 clocks = <&clks 44>;
52f7176b
SG		 1186 #pwm-cells = <2>;
1187 fsl,pwm-number = <8>;
bc3a59c1
DA		 1188 status = "disabled";
1189 };
1190
296f8cd3 1191 timer: timrot@80068000 {
eeca6e60 1192 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 1193 reg = <0x80068000 0x2000>;
eeca6e60 1194 interrupts = <48 49 50 51>;
2efb9504 1195 clocks = <&clks 26>;
bc3a59c1
DA		 1196 };
1197
1198 auart0: serial@8006a000 {
80d969e4 1199 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1200 reg = <0x8006a000 0x2000>;
7f2b9288 1201 interrupts = <112>;
f30fb03d
SG		 1202 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1203 dma-names = "rx", "tx";
b598b9f3 1204 clocks = <&clks 45>;
bc3a59c1
DA		 1205 status = "disabled";
1206 };
1207
1208 auart1: serial@8006c000 {
80d969e4 1209 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1210 reg = <0x8006c000 0x2000>;
7f2b9288 1211 interrupts = <113>;
f30fb03d
SG		 1212 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1213 dma-names = "rx", "tx";
b598b9f3 1214 clocks = <&clks 45>;
bc3a59c1
DA		 1215 status = "disabled";
1216 };
1217
1218 auart2: serial@8006e000 {
80d969e4 1219 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1220 reg = <0x8006e000 0x2000>;
7f2b9288 1221 interrupts = <114>;
f30fb03d
SG		 1222 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1223 dma-names = "rx", "tx";
b598b9f3 1224 clocks = <&clks 45>;
bc3a59c1
DA		 1225 status = "disabled";
1226 };
1227
1228 auart3: serial@80070000 {
80d969e4 1229 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1230 reg = <0x80070000 0x2000>;
7f2b9288 1231 interrupts = <115>;
f30fb03d
SG		 1232 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1233 dma-names = "rx", "tx";
b598b9f3 1234 clocks = <&clks 45>;
bc3a59c1
DA		 1235 status = "disabled";
1236 };
1237
1238 auart4: serial@80072000 {
80d969e4 1239 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1240 reg = <0x80072000 0x2000>;
7f2b9288 1241 interrupts = <116>;
f30fb03d
SG		 1242 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1243 dma-names = "rx", "tx";
b598b9f3 1244 clocks = <&clks 45>;
bc3a59c1
DA		 1245 status = "disabled";
1246 };
1247
1248 duart: serial@80074000 {
1249 compatible = "arm,pl011", "arm,primecell";
1250 reg = <0x80074000 0x1000>;
1251 interrupts = <47>;
b598b9f3
SG		 1252 clocks = <&clks 45>, <&clks 26>;
1253 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 1254 status = "disabled";
1255 };
1256
1257 usbphy0: usbphy@8007c000 {
5da01270 1258 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1259 reg = <0x8007c000 0x2000>;
b598b9f3 1260 clocks = <&clks 62>;
bc3a59c1
DA		 1261 status = "disabled";
1262 };
1263
1264 usbphy1: usbphy@8007e000 {
5da01270 1265 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1266 reg = <0x8007e000 0x2000>;
b598b9f3 1267 clocks = <&clks 63>;
bc3a59c1
DA		 1268 status = "disabled";
1269 };
1270 };
1271 };
1272
1273 ahb@80080000 {
1274 compatible = "simple-bus";
1275 #address-cells = <1>;
1276 #size-cells = <1>;
1277 reg = <0x80080000 0x80000>;
1278 ranges;
1279
5da01270
RZ		 1280 usb0: usb@80080000 {
1281 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1282 reg = <0x80080000 0x10000>;
5da01270 1283 interrupts = <93>;
b598b9f3 1284 clocks = <&clks 60>;
5da01270 1285 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1286 status = "disabled";
1287 };
1288
5da01270
RZ		 1289 usb1: usb@80090000 {
1290 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1291 reg = <0x80090000 0x10000>;
5da01270 1292 interrupts = <92>;
b598b9f3 1293 clocks = <&clks 61>;
5da01270 1294 fsl,usbphy = <&usbphy1>;
3ec481ed 1295 dr_mode = "host";
bc3a59c1
DA		 1296 status = "disabled";
1297 };
1298
296f8cd3 1299 dflpt: dflpt@800c0000 {
bc3a59c1
DA		 1300 reg = <0x800c0000 0x10000>;
1301 status = "disabled";
1302 };
1303
1304 mac0: ethernet@800f0000 {
1305 compatible = "fsl,imx28-fec";
1306 reg = <0x800f0000 0x4000>;
1307 interrupts = <101>;
f231a9fe
WS		 1308 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1309 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1310 status = "disabled";
1311 };
1312
1313 mac1: ethernet@800f4000 {
1314 compatible = "fsl,imx28-fec";
1315 reg = <0x800f4000 0x4000>;
1316 interrupts = <102>;
b598b9f3
SG		 1317 clocks = <&clks 57>, <&clks 57>;
1318 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1319 status = "disabled";
1320 };
1321
296f8cd3 1322 etn_switch: switch@800f8000 {
bc3a59c1
DA		 1323 reg = <0x800f8000 0x8000>;
1324 status = "disabled";
1325 };
bc3a59c1 1326 };
f92dfb02 1327
0b452ccc 1328 iio-hwmon {
f92dfb02
AB		 1329 compatible = "iio-hwmon";
1330 io-channels = <&lradc 8>;
1331 };
bc3a59c1 1332};
Linux 6.x block layer and io_uring tree(s)