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ARM: dts: imx28-duckbill: fix mmc settings
[linux-2.6-block.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
bc3875f1
LW		 12#include "skeleton.dtsi"
13#include "imx28-pinfunc.h"
bc3a59c1
DA		 14
15/ {
16 interrupt-parent = <&icoll>;
17
ce4c6f9b 18 aliases {
6bf6eb09
FE		 19 ethernet0 = &mac0;
20 ethernet1 = &mac1;
ce4c6f9b
SG		 21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
530f1d41
SG		 26 saif0 = &saif0;
27 saif1 = &saif1;
80d969e4
FE		 28 serial0 = &auart0;
29 serial1 = &auart1;
30 serial2 = &auart2;
31 serial3 = &auart3;
32 serial4 = &auart4;
6bf6eb09
FE		 33 spi0 = &ssp1;
34 spi1 = &ssp2;
1f35cc6a
PC		 35 usbphy0 = &usbphy0;
36 usbphy1 = &usbphy1;
ce4c6f9b
SG		 37 };
38
bc3a59c1 39 cpus {
7925e89f
LP		 40 #address-cells = <0>;
41 #size-cells = <0>;
42
43 cpu {
44 compatible = "arm,arm926ej-s";
45 device_type = "cpu";
bc3a59c1
DA		 46 };
47 };
48
49 apb@80000000 {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 reg = <0x80000000 0x80000>;
54 ranges;
55
56 apbh@80000000 {
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
60 reg = <0x80000000 0x3c900>;
61 ranges;
62
63 icoll: interrupt-controller@80000000 {
83a84efc 64 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 65 interrupt-controller;
66 #interrupt-cells = <1>;
67 reg = <0x80000000 0x2000>;
68 };
69
296f8cd3 70 hsadc: hsadc@80002000 {
0f06cde7 71 reg = <0x80002000 0x2000>;
7f2b9288 72 interrupts = <13>;
f30fb03d
SG		 73 dmas = <&dma_apbh 12>;
74 dma-names = "rx";
bc3a59c1
DA		 75 status = "disabled";
76 };
77
f30fb03d 78 dma_apbh: dma-apbh@80004000 {
84f3570a 79 compatible = "fsl,imx28-dma-apbh";
0f06cde7 80 reg = <0x80004000 0x2000>;
f30fb03d
SG		 81 interrupts = <82 83 84 85
82 88 88 88 88
83 88 88 88 88
84 87 86 0 0>;
85 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
86 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
87 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
88 "hsadc", "lcdif", "empty", "empty";
89 #dma-cells = <1>;
90 dma-channels = <16>;
b598b9f3 91 clocks = <&clks 25>;
bc3a59c1
DA		 92 };
93
296f8cd3 94 perfmon: perfmon@80006000 {
0f06cde7 95 reg = <0x80006000 0x800>;
bc3a59c1
DA		 96 interrupts = <27>;
97 status = "disabled";
98 };
99
296f8cd3 100 gpmi: gpmi-nand@8000c000 {
7a8e5149
HS		 101 compatible = "fsl,imx28-gpmi-nand";
102 #address-cells = <1>;
103 #size-cells = <1>;
0f06cde7 104 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149 105 reg-names = "gpmi-nand", "bch";
7f2b9288
SG		 106 interrupts = <41>;
107 interrupt-names = "bch";
b598b9f3 108 clocks = <&clks 50>;
b6442559 109 clock-names = "gpmi_io";
f30fb03d
SG		 110 dmas = <&dma_apbh 4>;
111 dma-names = "rx-tx";
bc3a59c1
DA		 112 status = "disabled";
113 };
114
115 ssp0: ssp@80010000 {
41bf5706
MR		 116 #address-cells = <1>;
117 #size-cells = <0>;
0f06cde7 118 reg = <0x80010000 0x2000>;
7f2b9288 119 interrupts = <96>;
b598b9f3 120 clocks = <&clks 46>;
f30fb03d
SG		 121 dmas = <&dma_apbh 0>;
122 dma-names = "rx-tx";
bc3a59c1
DA		 123 status = "disabled";
124 };
125
126 ssp1: ssp@80012000 {
41bf5706
MR		 127 #address-cells = <1>;
128 #size-cells = <0>;
0f06cde7 129 reg = <0x80012000 0x2000>;
7f2b9288 130 interrupts = <97>;
b598b9f3 131 clocks = <&clks 47>;
f30fb03d
SG		 132 dmas = <&dma_apbh 1>;
133 dma-names = "rx-tx";
bc3a59c1
DA		 134 status = "disabled";
135 };
136
137 ssp2: ssp@80014000 {
41bf5706
MR		 138 #address-cells = <1>;
139 #size-cells = <0>;
0f06cde7 140 reg = <0x80014000 0x2000>;
7f2b9288 141 interrupts = <98>;
b598b9f3 142 clocks = <&clks 48>;
f30fb03d
SG		 143 dmas = <&dma_apbh 2>;
144 dma-names = "rx-tx";
bc3a59c1
DA		 145 status = "disabled";
146 };
147
148 ssp3: ssp@80016000 {
41bf5706
MR		 149 #address-cells = <1>;
150 #size-cells = <0>;
0f06cde7 151 reg = <0x80016000 0x2000>;
7f2b9288 152 interrupts = <99>;
b598b9f3 153 clocks = <&clks 49>;
f30fb03d
SG		 154 dmas = <&dma_apbh 3>;
155 dma-names = "rx-tx";
bc3a59c1
DA		 156 status = "disabled";
157 };
158
296f8cd3 159 pinctrl: pinctrl@80018000 {
bc3a59c1
DA		 160 #address-cells = <1>;
161 #size-cells = <0>;
ce4c6f9b 162 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 163 reg = <0x80018000 0x2000>;
bc3a59c1 164
ce4c6f9b
SG		 165 gpio0: gpio@0 {
166 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
167 interrupts = <127>;
168 gpio-controller;
169 #gpio-cells = <2>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 };
173
174 gpio1: gpio@1 {
175 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
176 interrupts = <126>;
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 };
182
183 gpio2: gpio@2 {
184 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
185 interrupts = <125>;
186 gpio-controller;
187 #gpio-cells = <2>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 };
191
192 gpio3: gpio@3 {
193 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
194 interrupts = <124>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 };
200
201 gpio4: gpio@4 {
202 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
203 interrupts = <123>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
208 };
209
bc3a59c1
DA		 210 duart_pins_a: duart@0 {
211 reg = <0>;
f14da767 212 fsl,pinmux-ids = <
bc3875f1
LW		 213 MX28_PAD_PWM0__DUART_RX
214 MX28_PAD_PWM1__DUART_TX
f14da767 215 >;
4191c340
LW		 216 fsl,drive-strength = <MXS_DRIVE_4mA>;
217 fsl,voltage = <MXS_VOLTAGE_HIGH>;
218 fsl,pull-up = <MXS_PULL_DISABLE>;
bc3a59c1
DA		 219 };
220
8385e7c1
MR		 221 duart_pins_b: duart@1 {
222 reg = <1>;
f14da767 223 fsl,pinmux-ids = <
bc3875f1
LW		 224 MX28_PAD_AUART0_CTS__DUART_RX
225 MX28_PAD_AUART0_RTS__DUART_TX
f14da767 226 >;
4191c340
LW		 227 fsl,drive-strength = <MXS_DRIVE_4mA>;
228 fsl,voltage = <MXS_VOLTAGE_HIGH>;
229 fsl,pull-up = <MXS_PULL_DISABLE>;
8385e7c1
MR		 230 };
231
e1a4d18f
SG		 232 duart_4pins_a: duart-4pins@0 {
233 reg = <0>;
234 fsl,pinmux-ids = <
bc3875f1
LW		 235 MX28_PAD_AUART0_CTS__DUART_RX
236 MX28_PAD_AUART0_RTS__DUART_TX
237 MX28_PAD_AUART0_RX__DUART_CTS
238 MX28_PAD_AUART0_TX__DUART_RTS
e1a4d18f 239 >;
4191c340
LW		 240 fsl,drive-strength = <MXS_DRIVE_4mA>;
241 fsl,voltage = <MXS_VOLTAGE_HIGH>;
242 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 243 };
244
7a8e5149
HS		 245 gpmi_pins_a: gpmi-nand@0 {
246 reg = <0>;
f14da767 247 fsl,pinmux-ids = <
bc3875f1
LW		 248 MX28_PAD_GPMI_D00__GPMI_D0
249 MX28_PAD_GPMI_D01__GPMI_D1
250 MX28_PAD_GPMI_D02__GPMI_D2
251 MX28_PAD_GPMI_D03__GPMI_D3
252 MX28_PAD_GPMI_D04__GPMI_D4
253 MX28_PAD_GPMI_D05__GPMI_D5
254 MX28_PAD_GPMI_D06__GPMI_D6
255 MX28_PAD_GPMI_D07__GPMI_D7
256 MX28_PAD_GPMI_CE0N__GPMI_CE0N
257 MX28_PAD_GPMI_RDY0__GPMI_READY0
258 MX28_PAD_GPMI_RDN__GPMI_RDN
259 MX28_PAD_GPMI_WRN__GPMI_WRN
260 MX28_PAD_GPMI_ALE__GPMI_ALE
261 MX28_PAD_GPMI_CLE__GPMI_CLE
262 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 263 >;
4191c340
LW		 264 fsl,drive-strength = <MXS_DRIVE_4mA>;
265 fsl,voltage = <MXS_VOLTAGE_HIGH>;
266 fsl,pull-up = <MXS_PULL_DISABLE>;
7a8e5149
HS		 267 };
268
269 gpmi_status_cfg: gpmi-status-cfg {
f14da767 270 fsl,pinmux-ids = <
bc3875f1
LW		 271 MX28_PAD_GPMI_RDN__GPMI_RDN
272 MX28_PAD_GPMI_WRN__GPMI_WRN
273 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 274 >;
4191c340 275 fsl,drive-strength = <MXS_DRIVE_12mA>;
7a8e5149
HS		 276 };
277
80d969e4
FE		 278 auart0_pins_a: auart0@0 {
279 reg = <0>;
f14da767 280 fsl,pinmux-ids = <
bc3875f1
LW		 281 MX28_PAD_AUART0_RX__AUART0_RX
282 MX28_PAD_AUART0_TX__AUART0_TX
283 MX28_PAD_AUART0_CTS__AUART0_CTS
284 MX28_PAD_AUART0_RTS__AUART0_RTS
f14da767 285 >;
4191c340
LW		 286 fsl,drive-strength = <MXS_DRIVE_4mA>;
287 fsl,voltage = <MXS_VOLTAGE_HIGH>;
288 fsl,pull-up = <MXS_PULL_DISABLE>;
8fa62e11
MV		 289 };
290
291 auart0_2pins_a: auart0-2pins@0 {
292 reg = <0>;
293 fsl,pinmux-ids = <
bc3875f1
LW		 294 MX28_PAD_AUART0_RX__AUART0_RX
295 MX28_PAD_AUART0_TX__AUART0_TX
8fa62e11 296 >;
4191c340
LW		 297 fsl,drive-strength = <MXS_DRIVE_4mA>;
298 fsl,voltage = <MXS_VOLTAGE_HIGH>;
299 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 300 };
301
e1a4d18f
SG		 302 auart1_pins_a: auart1@0 {
303 reg = <0>;
304 fsl,pinmux-ids = <
bc3875f1
LW		 305 MX28_PAD_AUART1_RX__AUART1_RX
306 MX28_PAD_AUART1_TX__AUART1_TX
307 MX28_PAD_AUART1_CTS__AUART1_CTS
308 MX28_PAD_AUART1_RTS__AUART1_RTS
e1a4d18f 309 >;
4191c340
LW		 310 fsl,drive-strength = <MXS_DRIVE_4mA>;
311 fsl,voltage = <MXS_VOLTAGE_HIGH>;
312 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 313 };
314
3143bbb4
SG		 315 auart1_2pins_a: auart1-2pins@0 {
316 reg = <0>;
317 fsl,pinmux-ids = <
bc3875f1
LW		 318 MX28_PAD_AUART1_RX__AUART1_RX
319 MX28_PAD_AUART1_TX__AUART1_TX
3143bbb4 320 >;
4191c340
LW		 321 fsl,drive-strength = <MXS_DRIVE_4mA>;
322 fsl,voltage = <MXS_VOLTAGE_HIGH>;
323 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 324 };
325
326 auart2_2pins_a: auart2-2pins@0 {
327 reg = <0>;
328 fsl,pinmux-ids = <
bc3875f1
LW		 329 MX28_PAD_SSP2_SCK__AUART2_RX
330 MX28_PAD_SSP2_MOSI__AUART2_TX
3143bbb4 331 >;
4191c340
LW		 332 fsl,drive-strength = <MXS_DRIVE_4mA>;
333 fsl,voltage = <MXS_VOLTAGE_HIGH>;
334 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 335 };
336
f8040cf5
EB		 337 auart2_2pins_b: auart2-2pins@1 {
338 reg = <1>;
339 fsl,pinmux-ids = <
bc3875f1
LW		 340 MX28_PAD_AUART2_RX__AUART2_RX
341 MX28_PAD_AUART2_TX__AUART2_TX
f8040cf5 342 >;
4191c340
LW		 343 fsl,drive-strength = <MXS_DRIVE_4mA>;
344 fsl,voltage = <MXS_VOLTAGE_HIGH>;
345 fsl,pull-up = <MXS_PULL_DISABLE>;
f8040cf5
EB		 346 };
347
cd0214c3
AM		 348 auart2_pins_a: auart2-pins@0 {
349 reg = <0>;
350 fsl,pinmux-ids = <
351 MX28_PAD_AUART2_RX__AUART2_RX
352 MX28_PAD_AUART2_TX__AUART2_TX
353 MX28_PAD_AUART2_CTS__AUART2_CTS
354 MX28_PAD_AUART2_RTS__AUART2_RTS
355 >;
356 fsl,drive-strength = <MXS_DRIVE_4mA>;
357 fsl,voltage = <MXS_VOLTAGE_HIGH>;
358 fsl,pull-up = <MXS_PULL_DISABLE>;
359 };
360
80d969e4
FE		 361 auart3_pins_a: auart3@0 {
362 reg = <0>;
f14da767 363 fsl,pinmux-ids = <
bc3875f1
LW		 364 MX28_PAD_AUART3_RX__AUART3_RX
365 MX28_PAD_AUART3_TX__AUART3_TX
366 MX28_PAD_AUART3_CTS__AUART3_CTS
367 MX28_PAD_AUART3_RTS__AUART3_RTS
f14da767 368 >;
4191c340
LW		 369 fsl,drive-strength = <MXS_DRIVE_4mA>;
370 fsl,voltage = <MXS_VOLTAGE_HIGH>;
371 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 372 };
373
3143bbb4
SG		 374 auart3_2pins_a: auart3-2pins@0 {
375 reg = <0>;
376 fsl,pinmux-ids = <
bc3875f1
LW		 377 MX28_PAD_SSP2_MISO__AUART3_RX
378 MX28_PAD_SSP2_SS0__AUART3_TX
3143bbb4 379 >;
4191c340
LW		 380 fsl,drive-strength = <MXS_DRIVE_4mA>;
381 fsl,voltage = <MXS_VOLTAGE_HIGH>;
382 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 383 };
384
4812e746
EB		 385 auart3_2pins_b: auart3-2pins@1 {
386 reg = <1>;
387 fsl,pinmux-ids = <
bc3875f1
LW		 388 MX28_PAD_AUART3_RX__AUART3_RX
389 MX28_PAD_AUART3_TX__AUART3_TX
4812e746 390 >;
4191c340
LW		 391 fsl,drive-strength = <MXS_DRIVE_4mA>;
392 fsl,voltage = <MXS_VOLTAGE_HIGH>;
393 fsl,pull-up = <MXS_PULL_DISABLE>;
4812e746
EB		 394 };
395
33678d12
EB		 396 auart4_2pins_a: auart4@0 {
397 reg = <0>;
398 fsl,pinmux-ids = <
bc3875f1
LW		 399 MX28_PAD_SSP3_SCK__AUART4_TX
400 MX28_PAD_SSP3_MOSI__AUART4_RX
33678d12 401 >;
4191c340
LW		 402 fsl,drive-strength = <MXS_DRIVE_4mA>;
403 fsl,voltage = <MXS_VOLTAGE_HIGH>;
404 fsl,pull-up = <MXS_PULL_DISABLE>;
33678d12
EB		 405 };
406
bc3a59c1
DA		 407 mac0_pins_a: mac0@0 {
408 reg = <0>;
f14da767 409 fsl,pinmux-ids = <
bc3875f1
LW		 410 MX28_PAD_ENET0_MDC__ENET0_MDC
411 MX28_PAD_ENET0_MDIO__ENET0_MDIO
412 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
413 MX28_PAD_ENET0_RXD0__ENET0_RXD0
414 MX28_PAD_ENET0_RXD1__ENET0_RXD1
415 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
416 MX28_PAD_ENET0_TXD0__ENET0_TXD0
417 MX28_PAD_ENET0_TXD1__ENET0_TXD1
418 MX28_PAD_ENET_CLK__CLKCTRL_ENET
f14da767 419 >;
4191c340
LW		 420 fsl,drive-strength = <MXS_DRIVE_8mA>;
421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
422 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1
DA		 423 };
424
425 mac1_pins_a: mac1@0 {
426 reg = <0>;
f14da767 427 fsl,pinmux-ids = <
bc3875f1
LW		 428 MX28_PAD_ENET0_CRS__ENET1_RX_EN
429 MX28_PAD_ENET0_RXD2__ENET1_RXD0
430 MX28_PAD_ENET0_RXD3__ENET1_RXD1
431 MX28_PAD_ENET0_COL__ENET1_TX_EN
432 MX28_PAD_ENET0_TXD2__ENET1_TXD0
433 MX28_PAD_ENET0_TXD3__ENET1_TXD1
f14da767 434 >;
4191c340
LW		 435 fsl,drive-strength = <MXS_DRIVE_8mA>;
436 fsl,voltage = <MXS_VOLTAGE_HIGH>;
437 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1 438 };
35d23047
SG		 439
440 mmc0_8bit_pins_a: mmc0-8bit@0 {
441 reg = <0>;
f14da767 442 fsl,pinmux-ids = <
bc3875f1
LW		 443 MX28_PAD_SSP0_DATA0__SSP0_D0
444 MX28_PAD_SSP0_DATA1__SSP0_D1
445 MX28_PAD_SSP0_DATA2__SSP0_D2
446 MX28_PAD_SSP0_DATA3__SSP0_D3
447 MX28_PAD_SSP0_DATA4__SSP0_D4
448 MX28_PAD_SSP0_DATA5__SSP0_D5
449 MX28_PAD_SSP0_DATA6__SSP0_D6
450 MX28_PAD_SSP0_DATA7__SSP0_D7
451 MX28_PAD_SSP0_CMD__SSP0_CMD
452 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
453 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 454 >;
4191c340
LW		 455 fsl,drive-strength = <MXS_DRIVE_8mA>;
456 fsl,voltage = <MXS_VOLTAGE_HIGH>;
457 fsl,pull-up = <MXS_PULL_ENABLE>;
35d23047
SG		 458 };
459
8385e7c1
MR		 460 mmc0_4bit_pins_a: mmc0-4bit@0 {
461 reg = <0>;
f14da767 462 fsl,pinmux-ids = <
bc3875f1
LW		 463 MX28_PAD_SSP0_DATA0__SSP0_D0
464 MX28_PAD_SSP0_DATA1__SSP0_D1
465 MX28_PAD_SSP0_DATA2__SSP0_D2
466 MX28_PAD_SSP0_DATA3__SSP0_D3
467 MX28_PAD_SSP0_CMD__SSP0_CMD
468 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
469 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 470 >;
4191c340
LW		 471 fsl,drive-strength = <MXS_DRIVE_8mA>;
472 fsl,voltage = <MXS_VOLTAGE_HIGH>;
473 fsl,pull-up = <MXS_PULL_ENABLE>;
8385e7c1
MR		 474 };
475
35d23047 476 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767 477 fsl,pinmux-ids = <
bc3875f1 478 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
f14da767 479 >;
4191c340 480 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047
SG		 481 };
482
483 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767 484 fsl,pinmux-ids = <
bc3875f1 485 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 486 >;
4191c340
LW		 487 fsl,drive-strength = <MXS_DRIVE_12mA>;
488 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 489 };
2a96e391 490
5550e8e9
MV		 491 mmc2_4bit_pins_a: mmc2-4bit@0 {
492 reg = <0>;
493 fsl,pinmux-ids = <
494 MX28_PAD_SSP0_DATA4__SSP2_D0
495 MX28_PAD_SSP1_SCK__SSP2_D1
496 MX28_PAD_SSP1_CMD__SSP2_D2
497 MX28_PAD_SSP0_DATA5__SSP2_D3
498 MX28_PAD_SSP0_DATA6__SSP2_CMD
499 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
500 MX28_PAD_SSP0_DATA7__SSP2_SCK
501 >;
502 fsl,drive-strength = <MXS_DRIVE_8mA>;
503 fsl,voltage = <MXS_VOLTAGE_HIGH>;
504 fsl,pull-up = <MXS_PULL_ENABLE>;
505 };
506
507 mmc2_cd_cfg: mmc2-cd-cfg {
508 fsl,pinmux-ids = <
509 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
510 >;
511 fsl,pull-up = <MXS_PULL_DISABLE>;
512 };
513
514 mmc2_sck_cfg: mmc2-sck-cfg {
515 fsl,pinmux-ids = <
516 MX28_PAD_SSP0_DATA7__SSP2_SCK
517 >;
518 fsl,drive-strength = <MXS_DRIVE_12mA>;
519 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 520 };
2a96e391
SG		 521
522 i2c0_pins_a: i2c0@0 {
523 reg = <0>;
f14da767 524 fsl,pinmux-ids = <
bc3875f1
LW		 525 MX28_PAD_I2C0_SCL__I2C0_SCL
526 MX28_PAD_I2C0_SDA__I2C0_SDA
f14da767 527 >;
4191c340
LW		 528 fsl,drive-strength = <MXS_DRIVE_8mA>;
529 fsl,voltage = <MXS_VOLTAGE_HIGH>;
530 fsl,pull-up = <MXS_PULL_ENABLE>;
2a96e391 531 };
530f1d41 532
5c697ea2
MR		 533 i2c0_pins_b: i2c0@1 {
534 reg = <1>;
535 fsl,pinmux-ids = <
bc3875f1
LW		 536 MX28_PAD_AUART0_RX__I2C0_SCL
537 MX28_PAD_AUART0_TX__I2C0_SDA
5c697ea2 538 >;
4191c340
LW		 539 fsl,drive-strength = <MXS_DRIVE_8mA>;
540 fsl,voltage = <MXS_VOLTAGE_HIGH>;
541 fsl,pull-up = <MXS_PULL_ENABLE>;
5c697ea2
MR		 542 };
543
de7e934f
MR		 544 i2c1_pins_a: i2c1@0 {
545 reg = <0>;
546 fsl,pinmux-ids = <
bc3875f1
LW		 547 MX28_PAD_PWM0__I2C1_SCL
548 MX28_PAD_PWM1__I2C1_SDA
de7e934f 549 >;
4191c340
LW		 550 fsl,drive-strength = <MXS_DRIVE_8mA>;
551 fsl,voltage = <MXS_VOLTAGE_HIGH>;
552 fsl,pull-up = <MXS_PULL_ENABLE>;
de7e934f
MR		 553 };
554
530f1d41
SG		 555 saif0_pins_a: saif0@0 {
556 reg = <0>;
f14da767 557 fsl,pinmux-ids = <
bc3875f1
LW		 558 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
559 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
560 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
561 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
f14da767 562 >;
4191c340
LW		 563 fsl,drive-strength = <MXS_DRIVE_12mA>;
564 fsl,voltage = <MXS_VOLTAGE_HIGH>;
565 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41
SG		 566 };
567
2e1dd9fc
LW		 568 saif0_pins_b: saif0@1 {
569 reg = <1>;
570 fsl,pinmux-ids = <
bc3875f1
LW		 571 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
572 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
573 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2e1dd9fc 574 >;
4191c340
LW		 575 fsl,drive-strength = <MXS_DRIVE_12mA>;
576 fsl,voltage = <MXS_VOLTAGE_HIGH>;
577 fsl,pull-up = <MXS_PULL_ENABLE>;
2e1dd9fc
LW		 578 };
579
530f1d41
SG		 580 saif1_pins_a: saif1@0 {
581 reg = <0>;
f14da767 582 fsl,pinmux-ids = <
bc3875f1 583 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
f14da767 584 >;
4191c340
LW		 585 fsl,drive-strength = <MXS_DRIVE_12mA>;
586 fsl,voltage = <MXS_VOLTAGE_HIGH>;
587 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41 588 };
52f7176b 589
e1a4d18f
SG		 590 pwm0_pins_a: pwm0@0 {
591 reg = <0>;
592 fsl,pinmux-ids = <
bc3875f1 593 MX28_PAD_PWM0__PWM_0
e1a4d18f 594 >;
4191c340
LW		 595 fsl,drive-strength = <MXS_DRIVE_4mA>;
596 fsl,voltage = <MXS_VOLTAGE_HIGH>;
597 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 598 };
599
52f7176b
SG		 600 pwm2_pins_a: pwm2@0 {
601 reg = <0>;
602 fsl,pinmux-ids = <
bc3875f1 603 MX28_PAD_PWM2__PWM_2
52f7176b 604 >;
4191c340
LW		 605 fsl,drive-strength = <MXS_DRIVE_4mA>;
606 fsl,voltage = <MXS_VOLTAGE_HIGH>;
607 fsl,pull-up = <MXS_PULL_DISABLE>;
52f7176b 608 };
a915ee42 609
2bde51cb
JB		 610 pwm3_pins_a: pwm3@0 {
611 reg = <0>;
612 fsl,pinmux-ids = <
bc3875f1 613 MX28_PAD_PWM3__PWM_3
2bde51cb 614 >;
4191c340
LW		 615 fsl,drive-strength = <MXS_DRIVE_4mA>;
616 fsl,voltage = <MXS_VOLTAGE_HIGH>;
617 fsl,pull-up = <MXS_PULL_DISABLE>;
2bde51cb
JB		 618 };
619
d248620c
MR		 620 pwm3_pins_b: pwm3@1 {
621 reg = <1>;
622 fsl,pinmux-ids = <
bc3875f1 623 MX28_PAD_SAIF0_MCLK__PWM_3
d248620c 624 >;
4191c340
LW		 625 fsl,drive-strength = <MXS_DRIVE_4mA>;
626 fsl,voltage = <MXS_VOLTAGE_HIGH>;
627 fsl,pull-up = <MXS_PULL_DISABLE>;
d248620c
MR		 628 };
629
2f44211f
MR		 630 pwm4_pins_a: pwm4@0 {
631 reg = <0>;
632 fsl,pinmux-ids = <
bc3875f1 633 MX28_PAD_PWM4__PWM_4
2f44211f 634 >;
4191c340
LW		 635 fsl,drive-strength = <MXS_DRIVE_4mA>;
636 fsl,voltage = <MXS_VOLTAGE_HIGH>;
637 fsl,pull-up = <MXS_PULL_DISABLE>;
2f44211f
MR		 638 };
639
a915ee42
SG		 640 lcdif_24bit_pins_a: lcdif-24bit@0 {
641 reg = <0>;
642 fsl,pinmux-ids = <
bc3875f1
LW		 643 MX28_PAD_LCD_D00__LCD_D0
644 MX28_PAD_LCD_D01__LCD_D1
645 MX28_PAD_LCD_D02__LCD_D2
646 MX28_PAD_LCD_D03__LCD_D3
647 MX28_PAD_LCD_D04__LCD_D4
648 MX28_PAD_LCD_D05__LCD_D5
649 MX28_PAD_LCD_D06__LCD_D6
650 MX28_PAD_LCD_D07__LCD_D7
651 MX28_PAD_LCD_D08__LCD_D8
652 MX28_PAD_LCD_D09__LCD_D9
653 MX28_PAD_LCD_D10__LCD_D10
654 MX28_PAD_LCD_D11__LCD_D11
655 MX28_PAD_LCD_D12__LCD_D12
656 MX28_PAD_LCD_D13__LCD_D13
657 MX28_PAD_LCD_D14__LCD_D14
658 MX28_PAD_LCD_D15__LCD_D15
659 MX28_PAD_LCD_D16__LCD_D16
660 MX28_PAD_LCD_D17__LCD_D17
661 MX28_PAD_LCD_D18__LCD_D18
662 MX28_PAD_LCD_D19__LCD_D19
663 MX28_PAD_LCD_D20__LCD_D20
664 MX28_PAD_LCD_D21__LCD_D21
665 MX28_PAD_LCD_D22__LCD_D22
666 MX28_PAD_LCD_D23__LCD_D23
a915ee42 667 >;
4191c340
LW		 668 fsl,drive-strength = <MXS_DRIVE_4mA>;
669 fsl,voltage = <MXS_VOLTAGE_HIGH>;
670 fsl,pull-up = <MXS_PULL_DISABLE>;
a915ee42 671 };
6ca44acf 672
ec985eb2
DC		 673 lcdif_18bit_pins_a: lcdif-18bit@0 {
674 reg = <0>;
675 fsl,pinmux-ids = <
676 MX28_PAD_LCD_D00__LCD_D0
677 MX28_PAD_LCD_D01__LCD_D1
678 MX28_PAD_LCD_D02__LCD_D2
679 MX28_PAD_LCD_D03__LCD_D3
680 MX28_PAD_LCD_D04__LCD_D4
681 MX28_PAD_LCD_D05__LCD_D5
682 MX28_PAD_LCD_D06__LCD_D6
683 MX28_PAD_LCD_D07__LCD_D7
684 MX28_PAD_LCD_D08__LCD_D8
685 MX28_PAD_LCD_D09__LCD_D9
686 MX28_PAD_LCD_D10__LCD_D10
687 MX28_PAD_LCD_D11__LCD_D11
688 MX28_PAD_LCD_D12__LCD_D12
689 MX28_PAD_LCD_D13__LCD_D13
690 MX28_PAD_LCD_D14__LCD_D14
691 MX28_PAD_LCD_D15__LCD_D15
692 MX28_PAD_LCD_D16__LCD_D16
693 MX28_PAD_LCD_D17__LCD_D17
694 >;
695 fsl,drive-strength = <MXS_DRIVE_4mA>;
696 fsl,voltage = <MXS_VOLTAGE_HIGH>;
697 fsl,pull-up = <MXS_PULL_DISABLE>;
698 };
699
4ced2a40
GGM		 700 lcdif_16bit_pins_a: lcdif-16bit@0 {
701 reg = <0>;
702 fsl,pinmux-ids = <
bc3875f1
LW		 703 MX28_PAD_LCD_D00__LCD_D0
704 MX28_PAD_LCD_D01__LCD_D1
705 MX28_PAD_LCD_D02__LCD_D2
706 MX28_PAD_LCD_D03__LCD_D3
707 MX28_PAD_LCD_D04__LCD_D4
708 MX28_PAD_LCD_D05__LCD_D5
709 MX28_PAD_LCD_D06__LCD_D6
710 MX28_PAD_LCD_D07__LCD_D7
711 MX28_PAD_LCD_D08__LCD_D8
712 MX28_PAD_LCD_D09__LCD_D9
713 MX28_PAD_LCD_D10__LCD_D10
714 MX28_PAD_LCD_D11__LCD_D11
715 MX28_PAD_LCD_D12__LCD_D12
716 MX28_PAD_LCD_D13__LCD_D13
717 MX28_PAD_LCD_D14__LCD_D14
718 MX28_PAD_LCD_D15__LCD_D15
4ced2a40 719 >;
4191c340
LW		 720 fsl,drive-strength = <MXS_DRIVE_4mA>;
721 fsl,voltage = <MXS_VOLTAGE_HIGH>;
722 fsl,pull-up = <MXS_PULL_DISABLE>;
4ced2a40
GGM		 723 };
724
23ad6f65
LW		 725 lcdif_sync_pins_a: lcdif-sync@0 {
726 reg = <0>;
727 fsl,pinmux-ids = <
bc3875f1
LW		 728 MX28_PAD_LCD_RS__LCD_DOTCLK
729 MX28_PAD_LCD_CS__LCD_ENABLE
730 MX28_PAD_LCD_RD_E__LCD_VSYNC
731 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
23ad6f65 732 >;
4191c340
LW		 733 fsl,drive-strength = <MXS_DRIVE_4mA>;
734 fsl,voltage = <MXS_VOLTAGE_HIGH>;
735 fsl,pull-up = <MXS_PULL_DISABLE>;
23ad6f65
LW		 736 };
737
6ca44acf
SG		 738 can0_pins_a: can0@0 {
739 reg = <0>;
740 fsl,pinmux-ids = <
bc3875f1
LW		 741 MX28_PAD_GPMI_RDY2__CAN0_TX
742 MX28_PAD_GPMI_RDY3__CAN0_RX
6ca44acf 743 >;
4191c340
LW		 744 fsl,drive-strength = <MXS_DRIVE_4mA>;
745 fsl,voltage = <MXS_VOLTAGE_HIGH>;
746 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf
SG		 747 };
748
749 can1_pins_a: can1@0 {
750 reg = <0>;
751 fsl,pinmux-ids = <
bc3875f1
LW		 752 MX28_PAD_GPMI_CE2N__CAN1_TX
753 MX28_PAD_GPMI_CE3N__CAN1_RX
6ca44acf 754 >;
4191c340
LW		 755 fsl,drive-strength = <MXS_DRIVE_4mA>;
756 fsl,voltage = <MXS_VOLTAGE_HIGH>;
757 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf 758 };
7f122213
MV		 759
760 spi2_pins_a: spi2@0 {
761 reg = <0>;
762 fsl,pinmux-ids = <
bc3875f1
LW		 763 MX28_PAD_SSP2_SCK__SSP2_SCK
764 MX28_PAD_SSP2_MOSI__SSP2_CMD
765 MX28_PAD_SSP2_MISO__SSP2_D0
766 MX28_PAD_SSP2_SS0__SSP2_D3
7f122213 767 >;
4191c340
LW		 768 fsl,drive-strength = <MXS_DRIVE_8mA>;
769 fsl,voltage = <MXS_VOLTAGE_HIGH>;
770 fsl,pull-up = <MXS_PULL_ENABLE>;
7f122213 771 };
bb2f1261 772
3314d2be
LW		 773 spi3_pins_a: spi3@0 {
774 reg = <0>;
775 fsl,pinmux-ids = <
bc3875f1
LW		 776 MX28_PAD_AUART2_RX__SSP3_D4
777 MX28_PAD_AUART2_TX__SSP3_D5
778 MX28_PAD_SSP3_SCK__SSP3_SCK
779 MX28_PAD_SSP3_MOSI__SSP3_CMD
780 MX28_PAD_SSP3_MISO__SSP3_D0
781 MX28_PAD_SSP3_SS0__SSP3_D3
3314d2be 782 >;
4191c340
LW		 783 fsl,drive-strength = <MXS_DRIVE_8mA>;
784 fsl,voltage = <MXS_VOLTAGE_HIGH>;
785 fsl,pull-up = <MXS_PULL_DISABLE>;
3314d2be
LW		 786 };
787
c8e42bc9 788 usb0_pins_a: usb0@0 {
bb2f1261
MV		 789 reg = <0>;
790 fsl,pinmux-ids = <
bc3875f1 791 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
bb2f1261 792 >;
4191c340
LW		 793 fsl,drive-strength = <MXS_DRIVE_12mA>;
794 fsl,voltage = <MXS_VOLTAGE_HIGH>;
795 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 796 };
797
c8e42bc9 798 usb0_pins_b: usb0@1 {
bb2f1261
MV		 799 reg = <1>;
800 fsl,pinmux-ids = <
bc3875f1 801 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
bb2f1261 802 >;
4191c340
LW		 803 fsl,drive-strength = <MXS_DRIVE_12mA>;
804 fsl,voltage = <MXS_VOLTAGE_HIGH>;
805 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 806 };
807
c8e42bc9 808 usb1_pins_a: usb1@0 {
bb2f1261
MV		 809 reg = <0>;
810 fsl,pinmux-ids = <
bc3875f1 811 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
bb2f1261 812 >;
4191c340
LW		 813 fsl,drive-strength = <MXS_DRIVE_12mA>;
814 fsl,voltage = <MXS_VOLTAGE_HIGH>;
815 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261 816 };
69c02f95
FE		 817
818 usb0_id_pins_a: usb0id@0 {
819 reg = <0>;
820 fsl,pinmux-ids = <
e96e1782 821 MX28_PAD_AUART1_RTS__USB0_ID
bb2f1261 822 >;
e96e1782
LW		 823 fsl,drive-strength = <MXS_DRIVE_12mA>;
824 fsl,voltage = <MXS_VOLTAGE_HIGH>;
825 fsl,pull-up = <MXS_PULL_ENABLE>;
bb2f1261 826 };
bb89b8d2
DC		 827
828 usb0_id_pins_b: usb0id1@0 {
829 reg = <0>;
830 fsl,pinmux-ids = <
831 MX28_PAD_PWM2__USB0_ID
832 >;
833 fsl,drive-strength = <MXS_DRIVE_12mA>;
834 fsl,voltage = <MXS_VOLTAGE_HIGH>;
835 fsl,pull-up = <MXS_PULL_ENABLE>;
836 };
837
bc3a59c1
DA		 838 };
839
296f8cd3 840 digctl: digctl@8001c000 {
115581cf 841 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 842 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 843 interrupts = <89>;
844 status = "disabled";
845 };
846
296f8cd3 847 etm: etm@80022000 {
0f06cde7 848 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 849 status = "disabled";
850 };
851
f30fb03d 852 dma_apbx: dma-apbx@80024000 {
84f3570a 853 compatible = "fsl,imx28-dma-apbx";
0f06cde7 854 reg = <0x80024000 0x2000>;
f30fb03d
SG		 855 interrupts = <78 79 66 0
856 80 81 68 69
857 70 71 72 73
858 74 75 76 77>;
859 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
860 "saif0", "saif1", "i2c0", "i2c1",
861 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
862 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
863 #dma-cells = <1>;
864 dma-channels = <16>;
b598b9f3 865 clocks = <&clks 26>;
bc3a59c1
DA		 866 };
867
296f8cd3 868 dcp: dcp@80028000 {
7d56a28f 869 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
0f06cde7 870 reg = <0x80028000 0x2000>;
bc3a59c1 871 interrupts = <52 53 54>;
7d56a28f 872 status = "okay";
bc3a59c1
DA		 873 };
874
296f8cd3 875 pxp: pxp@8002a000 {
0f06cde7 876 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 877 interrupts = <39>;
878 status = "disabled";
879 };
880
296f8cd3 881 ocotp: ocotp@8002c000 {
69d75a02 882 compatible = "fsl,ocotp";
0f06cde7 883 reg = <0x8002c000 0x2000>;
bc3a59c1
DA		 884 status = "disabled";
885 };
886
887 axi-ahb@8002e000 {
0f06cde7 888 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 889 status = "disabled";
890 };
891
296f8cd3 892 lcdif: lcdif@80030000 {
a915ee42 893 compatible = "fsl,imx28-lcdif";
0f06cde7 894 reg = <0x80030000 0x2000>;
7f2b9288 895 interrupts = <38>;
b598b9f3 896 clocks = <&clks 55>;
f30fb03d
SG		 897 dmas = <&dma_apbh 13>;
898 dma-names = "rx";
bc3a59c1
DA		 899 status = "disabled";
900 };
901
902 can0: can@80032000 {
6ca44acf 903 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 904 reg = <0x80032000 0x2000>;
bc3a59c1 905 interrupts = <8>;
b598b9f3
SG		 906 clocks = <&clks 58>, <&clks 58>;
907 clock-names = "ipg", "per";
bc3a59c1
DA		 908 status = "disabled";
909 };
910
911 can1: can@80034000 {
6ca44acf 912 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 913 reg = <0x80034000 0x2000>;
bc3a59c1 914 interrupts = <9>;
b598b9f3
SG		 915 clocks = <&clks 59>, <&clks 59>;
916 clock-names = "ipg", "per";
bc3a59c1
DA		 917 status = "disabled";
918 };
919
296f8cd3 920 simdbg: simdbg@8003c000 {
0f06cde7 921 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 922 status = "disabled";
923 };
924
296f8cd3 925 simgpmisel: simgpmisel@8003c200 {
0f06cde7 926 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 927 status = "disabled";
928 };
929
296f8cd3 930 simsspsel: simsspsel@8003c300 {
0f06cde7 931 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 932 status = "disabled";
933 };
934
296f8cd3 935 simmemsel: simmemsel@8003c400 {
0f06cde7 936 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 937 status = "disabled";
938 };
939
296f8cd3 940 gpiomon: gpiomon@8003c500 {
0f06cde7 941 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 942 status = "disabled";
943 };
944
296f8cd3 945 simenet: simenet@8003c700 {
0f06cde7 946 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 947 status = "disabled";
948 };
949
296f8cd3 950 armjtag: armjtag@8003c800 {
0f06cde7 951 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 952 status = "disabled";
953 };
07a3ce7f 954 };
bc3a59c1
DA		 955
956 apbx@80040000 {
957 compatible = "simple-bus";
958 #address-cells = <1>;
959 #size-cells = <1>;
960 reg = <0x80040000 0x40000>;
961 ranges;
962
b598b9f3 963 clks: clkctrl@80040000 {
8f7cf881 964 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 965 reg = <0x80040000 0x2000>;
b598b9f3 966 #clock-cells = <1>;
bc3a59c1
DA		 967 };
968
969 saif0: saif@80042000 {
530f1d41 970 compatible = "fsl,imx28-saif";
0f06cde7 971 reg = <0x80042000 0x2000>;
7f2b9288 972 interrupts = <59>;
66acaf3f 973 #clock-cells = <0>;
b598b9f3 974 clocks = <&clks 53>;
f30fb03d
SG		 975 dmas = <&dma_apbx 4>;
976 dma-names = "rx-tx";
bc3a59c1
DA		 977 status = "disabled";
978 };
979
296f8cd3 980 power: power@80044000 {
0f06cde7 981 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 982 status = "disabled";
983 };
984
985 saif1: saif@80046000 {
530f1d41 986 compatible = "fsl,imx28-saif";
0f06cde7 987 reg = <0x80046000 0x2000>;
7f2b9288 988 interrupts = <58>;
b598b9f3 989 clocks = <&clks 54>;
f30fb03d
SG		 990 dmas = <&dma_apbx 5>;
991 dma-names = "rx-tx";
bc3a59c1
DA		 992 status = "disabled";
993 };
994
296f8cd3 995 lradc: lradc@80050000 {
aef35104 996 compatible = "fsl,imx28-lradc";
0f06cde7 997 reg = <0x80050000 0x2000>;
aef35104
MV		 998 interrupts = <10 14 15 16 17 18 19
999 20 21 22 23 24 25>;
bc3a59c1 1000 status = "disabled";
18da755d 1001 clocks = <&clks 41>;
40dde681 1002 #io-channel-cells = <1>;
bc3a59c1
DA		 1003 };
1004
296f8cd3 1005 spdif: spdif@80054000 {
0f06cde7 1006 reg = <0x80054000 0x2000>;
7f2b9288 1007 interrupts = <45>;
f30fb03d
SG		 1008 dmas = <&dma_apbx 2>;
1009 dma-names = "tx";
bc3a59c1
DA		 1010 status = "disabled";
1011 };
1012
296f8cd3 1013 mxs_rtc: rtc@80056000 {
f98c990c 1014 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 1015 reg = <0x80056000 0x2000>;
f98c990c 1016 interrupts = <29>;
bc3a59c1
DA		 1017 };
1018
1019 i2c0: i2c@80058000 {
2a96e391
SG		 1020 #address-cells = <1>;
1021 #size-cells = <0>;
1022 compatible = "fsl,imx28-i2c";
0f06cde7 1023 reg = <0x80058000 0x2000>;
7f2b9288 1024 interrupts = <111>;
cd4f2d4a 1025 clock-frequency = <100000>;
f30fb03d
SG		 1026 dmas = <&dma_apbx 6>;
1027 dma-names = "rx-tx";
bc3a59c1
DA		 1028 status = "disabled";
1029 };
1030
1031 i2c1: i2c@8005a000 {
2a96e391
SG		 1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034 compatible = "fsl,imx28-i2c";
0f06cde7 1035 reg = <0x8005a000 0x2000>;
7f2b9288 1036 interrupts = <110>;
cd4f2d4a 1037 clock-frequency = <100000>;
f30fb03d
SG		 1038 dmas = <&dma_apbx 7>;
1039 dma-names = "rx-tx";
bc3a59c1
DA		 1040 status = "disabled";
1041 };
1042
52f7176b
SG		 1043 pwm: pwm@80064000 {
1044 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 1045 reg = <0x80064000 0x2000>;
b598b9f3 1046 clocks = <&clks 44>;
52f7176b
SG		 1047 #pwm-cells = <2>;
1048 fsl,pwm-number = <8>;
bc3a59c1
DA		 1049 status = "disabled";
1050 };
1051
296f8cd3 1052 timer: timrot@80068000 {
eeca6e60 1053 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 1054 reg = <0x80068000 0x2000>;
eeca6e60 1055 interrupts = <48 49 50 51>;
2efb9504 1056 clocks = <&clks 26>;
bc3a59c1
DA		 1057 };
1058
1059 auart0: serial@8006a000 {
80d969e4 1060 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1061 reg = <0x8006a000 0x2000>;
7f2b9288 1062 interrupts = <112>;
f30fb03d
SG		 1063 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1064 dma-names = "rx", "tx";
b598b9f3 1065 clocks = <&clks 45>;
bc3a59c1
DA		 1066 status = "disabled";
1067 };
1068
1069 auart1: serial@8006c000 {
80d969e4 1070 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1071 reg = <0x8006c000 0x2000>;
7f2b9288 1072 interrupts = <113>;
f30fb03d
SG		 1073 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1074 dma-names = "rx", "tx";
b598b9f3 1075 clocks = <&clks 45>;
bc3a59c1
DA		 1076 status = "disabled";
1077 };
1078
1079 auart2: serial@8006e000 {
80d969e4 1080 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1081 reg = <0x8006e000 0x2000>;
7f2b9288 1082 interrupts = <114>;
f30fb03d
SG		 1083 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1084 dma-names = "rx", "tx";
b598b9f3 1085 clocks = <&clks 45>;
bc3a59c1
DA		 1086 status = "disabled";
1087 };
1088
1089 auart3: serial@80070000 {
80d969e4 1090 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1091 reg = <0x80070000 0x2000>;
7f2b9288 1092 interrupts = <115>;
f30fb03d
SG		 1093 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1094 dma-names = "rx", "tx";
b598b9f3 1095 clocks = <&clks 45>;
bc3a59c1
DA		 1096 status = "disabled";
1097 };
1098
1099 auart4: serial@80072000 {
80d969e4 1100 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1101 reg = <0x80072000 0x2000>;
7f2b9288 1102 interrupts = <116>;
f30fb03d
SG		 1103 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1104 dma-names = "rx", "tx";
b598b9f3 1105 clocks = <&clks 45>;
bc3a59c1
DA		 1106 status = "disabled";
1107 };
1108
1109 duart: serial@80074000 {
1110 compatible = "arm,pl011", "arm,primecell";
1111 reg = <0x80074000 0x1000>;
1112 interrupts = <47>;
b598b9f3
SG		 1113 clocks = <&clks 45>, <&clks 26>;
1114 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 1115 status = "disabled";
1116 };
1117
1118 usbphy0: usbphy@8007c000 {
5da01270 1119 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1120 reg = <0x8007c000 0x2000>;
b598b9f3 1121 clocks = <&clks 62>;
bc3a59c1
DA		 1122 status = "disabled";
1123 };
1124
1125 usbphy1: usbphy@8007e000 {
5da01270 1126 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1127 reg = <0x8007e000 0x2000>;
b598b9f3 1128 clocks = <&clks 63>;
bc3a59c1
DA		 1129 status = "disabled";
1130 };
1131 };
1132 };
1133
1134 ahb@80080000 {
1135 compatible = "simple-bus";
1136 #address-cells = <1>;
1137 #size-cells = <1>;
1138 reg = <0x80080000 0x80000>;
1139 ranges;
1140
5da01270
RZ		 1141 usb0: usb@80080000 {
1142 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1143 reg = <0x80080000 0x10000>;
5da01270 1144 interrupts = <93>;
b598b9f3 1145 clocks = <&clks 60>;
5da01270 1146 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1147 status = "disabled";
1148 };
1149
5da01270
RZ		 1150 usb1: usb@80090000 {
1151 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1152 reg = <0x80090000 0x10000>;
5da01270 1153 interrupts = <92>;
b598b9f3 1154 clocks = <&clks 61>;
5da01270 1155 fsl,usbphy = <&usbphy1>;
bc3a59c1
DA		 1156 status = "disabled";
1157 };
1158
296f8cd3 1159 dflpt: dflpt@800c0000 {
bc3a59c1
DA		 1160 reg = <0x800c0000 0x10000>;
1161 status = "disabled";
1162 };
1163
1164 mac0: ethernet@800f0000 {
1165 compatible = "fsl,imx28-fec";
1166 reg = <0x800f0000 0x4000>;
1167 interrupts = <101>;
f231a9fe
WS		 1168 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1169 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1170 status = "disabled";
1171 };
1172
1173 mac1: ethernet@800f4000 {
1174 compatible = "fsl,imx28-fec";
1175 reg = <0x800f4000 0x4000>;
1176 interrupts = <102>;
b598b9f3
SG		 1177 clocks = <&clks 57>, <&clks 57>;
1178 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1179 status = "disabled";
1180 };
1181
296f8cd3 1182 etn_switch: switch@800f8000 {
bc3a59c1
DA		 1183 reg = <0x800f8000 0x8000>;
1184 status = "disabled";
1185 };
bc3a59c1 1186 };
f92dfb02
AB		 1187
1188 iio_hwmon {
1189 compatible = "iio-hwmon";
1190 io-channels = <&lradc 8>;
1191 };
bc3a59c1 1192};
Linux 6.x block layer and io_uring tree(s)