Commit | Line | Data |
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9f0749e3 SH |
1 | /* |
2 | * Copyright 2012 Sascha Hauer, Pengutronix | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
36dffd8f | 12 | #include "skeleton.dtsi" |
61664d0b | 13 | #include "imx27-pinfunc.h" |
ea336fa8 AS |
14 | |
15 | #include <dt-bindings/clock/imx27-clock.h> | |
16 | #include <dt-bindings/gpio/gpio.h> | |
f6bd3f30 | 17 | #include <dt-bindings/input/input.h> |
6ece55b3 | 18 | #include <dt-bindings/interrupt-controller/irq.h> |
9f0749e3 SH |
19 | |
20 | / { | |
21 | aliases { | |
22970070 | 22 | ethernet0 = &fec; |
5230f8fe SG |
23 | gpio0 = &gpio1; |
24 | gpio1 = &gpio2; | |
25 | gpio2 = &gpio3; | |
26 | gpio3 = &gpio4; | |
27 | gpio4 = &gpio5; | |
28 | gpio5 = &gpio6; | |
6a3c0b39 SH |
29 | i2c0 = &i2c1; |
30 | i2c1 = &i2c2; | |
31 | serial0 = &uart1; | |
32 | serial1 = &uart2; | |
33 | serial2 = &uart3; | |
34 | serial3 = &uart4; | |
35 | serial4 = &uart5; | |
36 | serial5 = &uart6; | |
a5a641a1 AS |
37 | spi0 = &cspi1; |
38 | spi1 = &cspi2; | |
39 | spi2 = &cspi3; | |
9f0749e3 SH |
40 | }; |
41 | ||
6189bc34 FE |
42 | aitc: aitc-interrupt-controller@e0000000 { |
43 | compatible = "fsl,imx27-aitc", "fsl,avic"; | |
9f0749e3 SH |
44 | interrupt-controller; |
45 | #interrupt-cells = <1>; | |
46 | reg = <0x10040000 0x1000>; | |
47 | }; | |
48 | ||
49 | clocks { | |
50 | #address-cells = <1>; | |
51 | #size-cells = <0>; | |
52 | ||
53 | osc26m { | |
54 | compatible = "fsl,imx-osc26m", "fixed-clock"; | |
4b2b4043 | 55 | #clock-cells = <0>; |
9f0749e3 SH |
56 | clock-frequency = <26000000>; |
57 | }; | |
58 | }; | |
59 | ||
dc1d0f91 MP |
60 | cpus { |
61 | #size-cells = <0>; | |
62 | #address-cells = <1>; | |
63 | ||
48568be6 | 64 | cpu: cpu@0 { |
dc1d0f91 MP |
65 | device_type = "cpu"; |
66 | compatible = "arm,arm926ej-s"; | |
67 | operating-points = < | |
98a3e804 AS |
68 | /* kHz uV */ |
69 | 266000 1300000 | |
70 | 399000 1450000 | |
dc1d0f91 | 71 | >; |
8defcb53 | 72 | clock-latency = <62500>; |
ea336fa8 | 73 | clocks = <&clks IMX27_CLK_CPU_DIV>; |
98a3e804 | 74 | voltage-tolerance = <5>; |
dc1d0f91 MP |
75 | }; |
76 | }; | |
77 | ||
9f0749e3 SH |
78 | soc { |
79 | #address-cells = <1>; | |
80 | #size-cells = <1>; | |
81 | compatible = "simple-bus"; | |
6189bc34 | 82 | interrupt-parent = <&aitc>; |
9f0749e3 SH |
83 | ranges; |
84 | ||
85 | aipi@10000000 { /* AIPI1 */ | |
86 | compatible = "fsl,aipi-bus", "simple-bus"; | |
87 | #address-cells = <1>; | |
88 | #size-cells = <1>; | |
3e24b05b | 89 | reg = <0x10000000 0x20000>; |
9f0749e3 SH |
90 | ranges; |
91 | ||
b858c34f AS |
92 | dma: dma@10001000 { |
93 | compatible = "fsl,imx27-dma"; | |
94 | reg = <0x10001000 0x1000>; | |
95 | interrupts = <32>; | |
ea336fa8 AS |
96 | clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, |
97 | <&clks IMX27_CLK_DMA_AHB_GATE>; | |
b858c34f AS |
98 | clock-names = "ipg", "ahb"; |
99 | #dma-cells = <1>; | |
100 | #dma-channels = <16>; | |
101 | }; | |
102 | ||
7b7d6727 | 103 | wdog: wdog@10002000 { |
9f0749e3 | 104 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
ca26d041 | 105 | reg = <0x10002000 0x1000>; |
9f0749e3 | 106 | interrupts = <27>; |
ea336fa8 | 107 | clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; |
9f0749e3 SH |
108 | }; |
109 | ||
ca26d041 | 110 | gpt1: timer@10003000 { |
afde1312 | 111 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
112 | reg = <0x10003000 0x1000>; |
113 | interrupts = <26>; | |
ea336fa8 AS |
114 | clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, |
115 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 116 | clock-names = "ipg", "per"; |
ca26d041 SH |
117 | }; |
118 | ||
119 | gpt2: timer@10004000 { | |
afde1312 | 120 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
121 | reg = <0x10004000 0x1000>; |
122 | interrupts = <25>; | |
ea336fa8 AS |
123 | clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, |
124 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 125 | clock-names = "ipg", "per"; |
ca26d041 SH |
126 | }; |
127 | ||
128 | gpt3: timer@10005000 { | |
afde1312 | 129 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
130 | reg = <0x10005000 0x1000>; |
131 | interrupts = <24>; | |
ea336fa8 AS |
132 | clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, |
133 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 134 | clock-names = "ipg", "per"; |
ca26d041 SH |
135 | }; |
136 | ||
a392d044 | 137 | pwm: pwm@10006000 { |
443b6585 | 138 | #pwm-cells = <2>; |
08f4881a GGM |
139 | compatible = "fsl,imx27-pwm"; |
140 | reg = <0x10006000 0x1000>; | |
141 | interrupts = <23>; | |
ea336fa8 AS |
142 | clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, |
143 | <&clks IMX27_CLK_PER1_GATE>; | |
08f4881a GGM |
144 | clock-names = "ipg", "per"; |
145 | }; | |
146 | ||
6c04ad22 AS |
147 | kpp: kpp@10008000 { |
148 | compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; | |
149 | reg = <0x10008000 0x1000>; | |
150 | interrupts = <21>; | |
ea336fa8 | 151 | clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; |
6c04ad22 AS |
152 | status = "disabled"; |
153 | }; | |
154 | ||
6a486b7e MP |
155 | owire: owire@10009000 { |
156 | compatible = "fsl,imx27-owire", "fsl,imx21-owire"; | |
157 | reg = <0x10009000 0x1000>; | |
ea336fa8 | 158 | clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; |
6a486b7e MP |
159 | status = "disabled"; |
160 | }; | |
161 | ||
0c456cfa | 162 | uart1: serial@1000a000 { |
9f0749e3 SH |
163 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
164 | reg = <0x1000a000 0x1000>; | |
165 | interrupts = <20>; | |
ea336fa8 AS |
166 | clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, |
167 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 168 | clock-names = "ipg", "per"; |
9f0749e3 SH |
169 | status = "disabled"; |
170 | }; | |
171 | ||
0c456cfa | 172 | uart2: serial@1000b000 { |
9f0749e3 SH |
173 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
174 | reg = <0x1000b000 0x1000>; | |
175 | interrupts = <19>; | |
ea336fa8 AS |
176 | clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, |
177 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 178 | clock-names = "ipg", "per"; |
9f0749e3 SH |
179 | status = "disabled"; |
180 | }; | |
181 | ||
0c456cfa | 182 | uart3: serial@1000c000 { |
9f0749e3 SH |
183 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
184 | reg = <0x1000c000 0x1000>; | |
185 | interrupts = <18>; | |
ea336fa8 AS |
186 | clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, |
187 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 188 | clock-names = "ipg", "per"; |
9f0749e3 SH |
189 | status = "disabled"; |
190 | }; | |
191 | ||
0c456cfa | 192 | uart4: serial@1000d000 { |
9f0749e3 SH |
193 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
194 | reg = <0x1000d000 0x1000>; | |
195 | interrupts = <17>; | |
ea336fa8 AS |
196 | clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, |
197 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 198 | clock-names = "ipg", "per"; |
9f0749e3 SH |
199 | status = "disabled"; |
200 | }; | |
201 | ||
202 | cspi1: cspi@1000e000 { | |
203 | #address-cells = <1>; | |
204 | #size-cells = <0>; | |
205 | compatible = "fsl,imx27-cspi"; | |
206 | reg = <0x1000e000 0x1000>; | |
207 | interrupts = <16>; | |
ea336fa8 AS |
208 | clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, |
209 | <&clks IMX27_CLK_PER2_GATE>; | |
c20736f1 | 210 | clock-names = "ipg", "per"; |
9f0749e3 SH |
211 | status = "disabled"; |
212 | }; | |
213 | ||
214 | cspi2: cspi@1000f000 { | |
215 | #address-cells = <1>; | |
216 | #size-cells = <0>; | |
217 | compatible = "fsl,imx27-cspi"; | |
218 | reg = <0x1000f000 0x1000>; | |
219 | interrupts = <15>; | |
ea336fa8 AS |
220 | clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, |
221 | <&clks IMX27_CLK_PER2_GATE>; | |
c20736f1 | 222 | clock-names = "ipg", "per"; |
9f0749e3 SH |
223 | status = "disabled"; |
224 | }; | |
225 | ||
ba2d1ea7 AS |
226 | ssi1: ssi@10010000 { |
227 | #sound-dai-cells = <0>; | |
228 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; | |
229 | reg = <0x10010000 0x1000>; | |
230 | interrupts = <14>; | |
ea336fa8 | 231 | clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; |
ba2d1ea7 AS |
232 | dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; |
233 | dma-names = "rx0", "tx0", "rx1", "tx1"; | |
234 | fsl,fifo-depth = <8>; | |
235 | status = "disabled"; | |
236 | }; | |
237 | ||
238 | ssi2: ssi@10011000 { | |
239 | #sound-dai-cells = <0>; | |
240 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; | |
241 | reg = <0x10011000 0x1000>; | |
242 | interrupts = <13>; | |
ea336fa8 | 243 | clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; |
ba2d1ea7 AS |
244 | dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; |
245 | dma-names = "rx0", "tx0", "rx1", "tx1"; | |
246 | fsl,fifo-depth = <8>; | |
247 | status = "disabled"; | |
248 | }; | |
249 | ||
9f0749e3 SH |
250 | i2c1: i2c@10012000 { |
251 | #address-cells = <1>; | |
252 | #size-cells = <0>; | |
5bdfba29 | 253 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
9f0749e3 SH |
254 | reg = <0x10012000 0x1000>; |
255 | interrupts = <12>; | |
ea336fa8 | 256 | clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; |
9f0749e3 SH |
257 | status = "disabled"; |
258 | }; | |
259 | ||
0e7b01aa AS |
260 | sdhci1: sdhci@10013000 { |
261 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
262 | reg = <0x10013000 0x1000>; | |
263 | interrupts = <11>; | |
ea336fa8 AS |
264 | clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, |
265 | <&clks IMX27_CLK_PER2_GATE>; | |
0e7b01aa AS |
266 | clock-names = "ipg", "per"; |
267 | dmas = <&dma 7>; | |
268 | dma-names = "rx-tx"; | |
269 | status = "disabled"; | |
270 | }; | |
271 | ||
272 | sdhci2: sdhci@10014000 { | |
273 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
274 | reg = <0x10014000 0x1000>; | |
275 | interrupts = <10>; | |
ea336fa8 AS |
276 | clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, |
277 | <&clks IMX27_CLK_PER2_GATE>; | |
0e7b01aa AS |
278 | clock-names = "ipg", "per"; |
279 | dmas = <&dma 6>; | |
280 | dma-names = "rx-tx"; | |
281 | status = "disabled"; | |
282 | }; | |
283 | ||
733f6cae MP |
284 | iomuxc: iomuxc@10015000 { |
285 | compatible = "fsl,imx27-iomuxc"; | |
286 | reg = <0x10015000 0x600>; | |
287 | #address-cells = <1>; | |
288 | #size-cells = <1>; | |
289 | ranges; | |
290 | ||
291 | gpio1: gpio@10015000 { | |
292 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
293 | reg = <0x10015000 0x100>; | |
ea336fa8 | 294 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
295 | interrupts = <8>; |
296 | gpio-controller; | |
297 | #gpio-cells = <2>; | |
298 | interrupt-controller; | |
299 | #interrupt-cells = <2>; | |
300 | }; | |
301 | ||
302 | gpio2: gpio@10015100 { | |
303 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
304 | reg = <0x10015100 0x100>; | |
ea336fa8 | 305 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
306 | interrupts = <8>; |
307 | gpio-controller; | |
308 | #gpio-cells = <2>; | |
309 | interrupt-controller; | |
310 | #interrupt-cells = <2>; | |
311 | }; | |
312 | ||
313 | gpio3: gpio@10015200 { | |
314 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
315 | reg = <0x10015200 0x100>; | |
ea336fa8 | 316 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
317 | interrupts = <8>; |
318 | gpio-controller; | |
319 | #gpio-cells = <2>; | |
320 | interrupt-controller; | |
321 | #interrupt-cells = <2>; | |
322 | }; | |
323 | ||
324 | gpio4: gpio@10015300 { | |
325 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
326 | reg = <0x10015300 0x100>; | |
ea336fa8 | 327 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
328 | interrupts = <8>; |
329 | gpio-controller; | |
330 | #gpio-cells = <2>; | |
331 | interrupt-controller; | |
332 | #interrupt-cells = <2>; | |
333 | }; | |
334 | ||
335 | gpio5: gpio@10015400 { | |
336 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
337 | reg = <0x10015400 0x100>; | |
ea336fa8 | 338 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
339 | interrupts = <8>; |
340 | gpio-controller; | |
341 | #gpio-cells = <2>; | |
342 | interrupt-controller; | |
343 | #interrupt-cells = <2>; | |
344 | }; | |
345 | ||
346 | gpio6: gpio@10015500 { | |
347 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
348 | reg = <0x10015500 0x100>; | |
ea336fa8 | 349 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
350 | interrupts = <8>; |
351 | gpio-controller; | |
352 | #gpio-cells = <2>; | |
353 | interrupt-controller; | |
354 | #interrupt-cells = <2>; | |
355 | }; | |
9f0749e3 SH |
356 | }; |
357 | ||
6e228e80 AS |
358 | audmux: audmux@10016000 { |
359 | compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; | |
360 | reg = <0x10016000 0x1000>; | |
ea336fa8 | 361 | clocks = <&clks IMX27_CLK_DUMMY>; |
6e228e80 | 362 | clock-names = "audmux"; |
1c04ab0f | 363 | status = "disabled"; |
6e228e80 AS |
364 | }; |
365 | ||
9f0749e3 SH |
366 | cspi3: cspi@10017000 { |
367 | #address-cells = <1>; | |
368 | #size-cells = <0>; | |
369 | compatible = "fsl,imx27-cspi"; | |
370 | reg = <0x10017000 0x1000>; | |
371 | interrupts = <6>; | |
ea336fa8 AS |
372 | clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, |
373 | <&clks IMX27_CLK_PER2_GATE>; | |
c20736f1 | 374 | clock-names = "ipg", "per"; |
9f0749e3 SH |
375 | status = "disabled"; |
376 | }; | |
377 | ||
ca26d041 | 378 | gpt4: timer@10019000 { |
afde1312 | 379 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
380 | reg = <0x10019000 0x1000>; |
381 | interrupts = <4>; | |
ea336fa8 AS |
382 | clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, |
383 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 384 | clock-names = "ipg", "per"; |
ca26d041 SH |
385 | }; |
386 | ||
387 | gpt5: timer@1001a000 { | |
afde1312 | 388 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
389 | reg = <0x1001a000 0x1000>; |
390 | interrupts = <3>; | |
ea336fa8 AS |
391 | clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, |
392 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 393 | clock-names = "ipg", "per"; |
ca26d041 SH |
394 | }; |
395 | ||
0c456cfa | 396 | uart5: serial@1001b000 { |
9f0749e3 SH |
397 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
398 | reg = <0x1001b000 0x1000>; | |
399 | interrupts = <49>; | |
ea336fa8 AS |
400 | clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, |
401 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 402 | clock-names = "ipg", "per"; |
9f0749e3 SH |
403 | status = "disabled"; |
404 | }; | |
405 | ||
0c456cfa | 406 | uart6: serial@1001c000 { |
9f0749e3 SH |
407 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
408 | reg = <0x1001c000 0x1000>; | |
409 | interrupts = <48>; | |
ea336fa8 AS |
410 | clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, |
411 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 412 | clock-names = "ipg", "per"; |
9f0749e3 SH |
413 | status = "disabled"; |
414 | }; | |
415 | ||
416 | i2c2: i2c@1001d000 { | |
417 | #address-cells = <1>; | |
418 | #size-cells = <0>; | |
5bdfba29 | 419 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
9f0749e3 SH |
420 | reg = <0x1001d000 0x1000>; |
421 | interrupts = <1>; | |
ea336fa8 | 422 | clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; |
9f0749e3 SH |
423 | status = "disabled"; |
424 | }; | |
425 | ||
0e7b01aa AS |
426 | sdhci3: sdhci@1001e000 { |
427 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
428 | reg = <0x1001e000 0x1000>; | |
429 | interrupts = <9>; | |
ea336fa8 AS |
430 | clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, |
431 | <&clks IMX27_CLK_PER2_GATE>; | |
0e7b01aa AS |
432 | clock-names = "ipg", "per"; |
433 | dmas = <&dma 36>; | |
434 | dma-names = "rx-tx"; | |
435 | status = "disabled"; | |
436 | }; | |
437 | ||
ca26d041 | 438 | gpt6: timer@1001f000 { |
afde1312 | 439 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
440 | reg = <0x1001f000 0x1000>; |
441 | interrupts = <2>; | |
ea336fa8 AS |
442 | clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, |
443 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 444 | clock-names = "ipg", "per"; |
ca26d041 | 445 | }; |
3e24b05b FE |
446 | }; |
447 | ||
448 | aipi@10020000 { /* AIPI2 */ | |
449 | compatible = "fsl,aipi-bus", "simple-bus"; | |
450 | #address-cells = <1>; | |
451 | #size-cells = <1>; | |
452 | reg = <0x10020000 0x20000>; | |
453 | ranges; | |
454 | ||
5e57b241 MP |
455 | fb: fb@10021000 { |
456 | compatible = "fsl,imx27-fb", "fsl,imx21-fb"; | |
457 | interrupts = <61>; | |
458 | reg = <0x10021000 0x1000>; | |
ea336fa8 AS |
459 | clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, |
460 | <&clks IMX27_CLK_LCDC_AHB_GATE>, | |
461 | <&clks IMX27_CLK_PER3_GATE>; | |
5e57b241 MP |
462 | clock-names = "ipg", "ahb", "per"; |
463 | status = "disabled"; | |
464 | }; | |
465 | ||
93b331ce | 466 | coda: coda@10023000 { |
71946619 | 467 | compatible = "fsl,imx27-vpu", "cnm,codadx6"; |
93b331ce AS |
468 | reg = <0x10023000 0x0200>; |
469 | interrupts = <53>; | |
ea336fa8 AS |
470 | clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, |
471 | <&clks IMX27_CLK_VPU_AHB_GATE>; | |
93b331ce AS |
472 | clock-names = "per", "ahb"; |
473 | iram = <&iram>; | |
474 | }; | |
475 | ||
a2e502c2 AS |
476 | usbotg: usb@10024000 { |
477 | compatible = "fsl,imx27-usb"; | |
478 | reg = <0x10024000 0x200>; | |
479 | interrupts = <56>; | |
ea336fa8 | 480 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>; |
a2e502c2 | 481 | fsl,usbmisc = <&usbmisc 0>; |
a2e502c2 AS |
482 | status = "disabled"; |
483 | }; | |
484 | ||
485 | usbh1: usb@10024200 { | |
486 | compatible = "fsl,imx27-usb"; | |
487 | reg = <0x10024200 0x200>; | |
488 | interrupts = <54>; | |
ea336fa8 | 489 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>; |
a2e502c2 | 490 | fsl,usbmisc = <&usbmisc 1>; |
3ec481ed | 491 | dr_mode = "host"; |
a2e502c2 AS |
492 | status = "disabled"; |
493 | }; | |
494 | ||
495 | usbh2: usb@10024400 { | |
496 | compatible = "fsl,imx27-usb"; | |
497 | reg = <0x10024400 0x200>; | |
498 | interrupts = <55>; | |
ea336fa8 | 499 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>; |
a2e502c2 | 500 | fsl,usbmisc = <&usbmisc 2>; |
3ec481ed | 501 | dr_mode = "host"; |
a2e502c2 AS |
502 | status = "disabled"; |
503 | }; | |
504 | ||
505 | usbmisc: usbmisc@10024600 { | |
506 | #index-cells = <1>; | |
507 | compatible = "fsl,imx27-usbmisc"; | |
508 | reg = <0x10024600 0x200>; | |
ea336fa8 | 509 | clocks = <&clks IMX27_CLK_USB_AHB_GATE>; |
a2e502c2 AS |
510 | }; |
511 | ||
e4b6a056 AS |
512 | sahara2: sahara@10025000 { |
513 | compatible = "fsl,imx27-sahara"; | |
514 | reg = <0x10025000 0x1000>; | |
515 | interrupts = <59>; | |
ea336fa8 AS |
516 | clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, |
517 | <&clks IMX27_CLK_SAHARA_AHB_GATE>; | |
e4b6a056 AS |
518 | clock-names = "ipg", "ahb"; |
519 | }; | |
520 | ||
93b331ce AS |
521 | clks: ccm@10027000{ |
522 | compatible = "fsl,imx27-ccm"; | |
523 | reg = <0x10027000 0x1000>; | |
524 | #clock-cells = <1>; | |
525 | }; | |
526 | ||
d36afcd4 AS |
527 | iim: iim@10028000 { |
528 | compatible = "fsl,imx27-iim"; | |
529 | reg = <0x10028000 0x1000>; | |
530 | interrupts = <62>; | |
ea336fa8 | 531 | clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; |
d36afcd4 AS |
532 | }; |
533 | ||
0c456cfa | 534 | fec: ethernet@1002b000 { |
9f0749e3 | 535 | compatible = "fsl,imx27-fec"; |
a29ef819 | 536 | reg = <0x1002b000 0x1000>; |
9f0749e3 | 537 | interrupts = <50>; |
ea336fa8 AS |
538 | clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, |
539 | <&clks IMX27_CLK_FEC_AHB_GATE>; | |
c0b357c0 | 540 | clock-names = "ipg", "ahb"; |
9f0749e3 SH |
541 | status = "disabled"; |
542 | }; | |
543 | }; | |
7b7d6727 SH |
544 | |
545 | nfc: nand@d8000000 { | |
37787360 UKK |
546 | #address-cells = <1>; |
547 | #size-cells = <1>; | |
37787360 UKK |
548 | compatible = "fsl,imx27-nand"; |
549 | reg = <0xd8000000 0x1000>; | |
550 | interrupts = <29>; | |
ea336fa8 | 551 | clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; |
37787360 UKK |
552 | status = "disabled"; |
553 | }; | |
ff1450f6 | 554 | |
0912f594 AS |
555 | weim: weim@d8002000 { |
556 | #address-cells = <2>; | |
557 | #size-cells = <1>; | |
558 | compatible = "fsl,imx27-weim"; | |
559 | reg = <0xd8002000 0x1000>; | |
ea336fa8 | 560 | clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; |
0912f594 AS |
561 | ranges = < |
562 | 0 0 0xc0000000 0x08000000 | |
563 | 1 0 0xc8000000 0x08000000 | |
564 | 2 0 0xd0000000 0x02000000 | |
565 | 3 0 0xd2000000 0x02000000 | |
566 | 4 0 0xd4000000 0x02000000 | |
567 | 5 0 0xd6000000 0x02000000 | |
568 | >; | |
569 | status = "disabled"; | |
570 | }; | |
571 | ||
ff1450f6 AS |
572 | iram: iram@ffff4c00 { |
573 | compatible = "mmio-sram"; | |
574 | reg = <0xffff4c00 0xb400>; | |
575 | }; | |
9f0749e3 SH |
576 | }; |
577 | }; |