[linux-2.6-block.git] / arch / arm / boot / dts / imx27-phytec-phycore-som.dtsi

/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx27.dtsi"

/ {
	model = "Phytec pcm038";
	compatible = "phytec,imx27-pcm038", "fsl,imx27";

	memory {
		reg = <0xa0000000 0x08000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_3v3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		reg_5v0: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "5V0";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
		};
	};
};

&audmux {
	status = "okay";

	/* SSI0 <=> PINS_4 (MC13783 Audio) */
	ssi0 {
		fsl,audmux-port = <0>;
		fsl,port-config = <0xcb205000>;
	};

	pins4 {
		fsl,audmux-port = <2>;
		fsl,port-config = <0x00001000>;
	};
};

&cspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_cspi1>;
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pmic: mc13783@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mc13783";
		reg = <0>;
		spi-cs-high;
		spi-max-frequency = <20000000>;
		interrupt-parent = <&gpio2>;
		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
		fsl,mc13xxx-uses-adc;
		fsl,mc13xxx-uses-rtc;

		pmicleds: leds {
			#address-cells = <1>;
			#size-cells = <0>;
			led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
		};

		regulators {
			/* SW1A and SW1B joined operation */
			sw1_reg: sw1a {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1520000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* SW2A and SW2B joined operation */
			sw2_reg: sw2a {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			sw3_reg: sw3 {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			vaudio_reg: vaudio {
				regulator-always-on;
				regulator-boot-on;
			};

			violo_reg: violo {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			viohi_reg: viohi {
				regulator-always-on;
				regulator-boot-on;
			};

			vgen_reg: vgen {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1500000>;
				regulator-always-on;
				regulator-boot-on;
			};

			vcam_reg: vcam {
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
			};

			vrf1_reg: vrf1 {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
				regulator-always-on;
				regulator-boot-on;
			};

			vrf2_reg: vrf2 {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
				regulator-always-on;
				regulator-boot-on;
			};

			vmmc1_reg: vmmc1 {
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3000000>;
			};

			gpo1_reg: gpo1 { };

			pwgt1spi_reg: pwgt1spi {
				regulator-always-on;
			};
		};
	};
};

&fec {
	phy-mode = "mii";
	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
	phy-supply = <&reg_3v3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	at24@52 {
		compatible = "at,24c32";
		pagesize = <32>;
		reg = <0x52>;
	};

	pcf8563@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};

	lm75@4a {
		compatible = "national,lm75";
		reg = <0x4a>;
	};
};

&iomuxc {
	imx27_phycore_som {
		pinctrl_cspi1: cspi1grp {
			fsl,pins = <
				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
				MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* SPI1 CS0 */
				MX27_PAD_USB_PWR__GPIO2_23	0x0 /* PMIC IRQ */
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
				MX27_PAD_ATA_DATA13__FEC_COL 0x0
				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
				MX27_PAD_SSI3_TXDAT__GPIO3_30	0x0 /* FEC RST */
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
			>;
		};

		pinctrl_nfc: nfcgrp {
			fsl,pins = <
				MX27_PAD_NFRB__NFRB 0x0
				MX27_PAD_NFCLE__NFCLE 0x0
				MX27_PAD_NFWP_B__NFWP_B 0x0
				MX27_PAD_NFCE_B__NFCE_B 0x0
				MX27_PAD_NFALE__NFALE 0x0
				MX27_PAD_NFRE_B__NFRE_B 0x0
				MX27_PAD_NFWE_B__NFWE_B 0x0
			>;
		};

		pinctrl_ssi1: ssi1grp {
			fsl,pins = <
				MX27_PAD_SSI1_FS__SSI1_FS 0x0
				MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
				MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
				MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
				MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
				MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
				MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
			>;
		};
	};
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	status = "okay";
};

&ssi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ssi1>;
	fsl,mode = "i2s-slave";
	status = "okay";
};

&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	dr_mode = "otg";
	phy_type = "ulpi";
	vbus-supply = <&sw3_reg>;
	status = "okay";
};

&usbphy0 {
	vcc-supply = <&sw3_reg>;
};

&weim {
	status = "okay";

	nor: nor@0,0 {
		compatible = "cfi-flash";
		reg = <0 0x00000000 0x02000000>;
		bank-width = <2>;
		linux,mtd-name = "physmap-flash.0";
		fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	sram: sram@1,0 {
		compatible = "mtd-ram";
		reg = <1 0x00000000 0x00800000>;
		bank-width = <2>;
		linux,mtd-name = "mtd-ram.0";
		fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};
Commit	Line	Data
10a9ba05 SH	1	/*
	2	* Copyright 2012 Sascha Hauer, Pengutronix
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	/dts-v1/;
36dffd8f	13	#include "imx27.dtsi"
10a9ba05 SH	14
	15	/ {
	16	model = "Phytec pcm038";
	17	compatible = "phytec,imx27-pcm038", "fsl,imx27";
	18
	19	memory {
999f6818	20	reg = <0xa0000000 0x08000000>;
10a9ba05	21	};
f64ba746 AS	22
	23	regulators {
	24	compatible = "simple-bus";
	25	#address-cells = <1>;
	26	#size-cells = <0>;
	27
	28	reg_3v3: regulator@0 {
	29	compatible = "regulator-fixed";
	30	reg = <0>;
	31	regulator-name = "3V3";
	32	regulator-min-microvolt = <3300000>;
	33	regulator-max-microvolt = <3300000>;
	34	};
9089ce52 AS	35
	36	reg_5v0: regulator@1 {
	37	compatible = "regulator-fixed";
	38	reg = <1>;
	39	regulator-name = "5V0";
	40	regulator-min-microvolt = <5000000>;
	41	regulator-max-microvolt = <5000000>;
	42	};
f64ba746	43	};
10a9ba05	44	};
1b45aceb	45
a919c69c AS	46	&audmux {
	47	status = "okay";
	48
	49	/* SSI0 <=> PINS_4 (MC13783 Audio) */
	50	ssi0 {
	51	fsl,audmux-port = <0>;
	52	fsl,port-config = <0xcb205000>;
	53	};
	54
	55	pins4 {
	56	fsl,audmux-port = <2>;
	57	fsl,port-config = <0x00001000>;
	58	};
	59	};
	60
5d3503cd	61	&cspi1 {
f4bdf215 AS	62	pinctrl-names = "default";
f4bdf215 AS	63	pinctrl-0 = <&pinctrl_cspi1>;
5d3503cd	64	fsl,spi-num-chipselects = <1>;
6ece55b3	65	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
5d3503cd AS	66	status = "okay";
	67
	68	pmic: mc13783@0 {
	69	#address-cells = <1>;
	70	#size-cells = <0>;
	71	compatible = "fsl,mc13783";
5d3503cd	72	reg = <0>;
986cc492 AS	73	spi-cs-high;
986cc492 AS	74	spi-max-frequency = <20000000>;
5d3503cd	75	interrupt-parent = <&gpio2>;
6ece55b3	76	interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
5d3503cd AS	77	fsl,mc13xxx-uses-adc;
	78	fsl,mc13xxx-uses-rtc;
	79
5ee49a11 AS	80	pmicleds: leds {
	81	#address-cells = <1>;
	82	#size-cells = <0>;
	83	led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
	84	};
	85
5d3503cd	86	regulators {
e9c17866 AS	87	/* SW1A and SW1B joined operation */
e9c17866 AS	88	sw1_reg: sw1a {
5d3503cd	89	regulator-min-microvolt = <1200000>;
e9c17866	90	regulator-max-microvolt = <1520000>;
5d3503cd AS	91	regulator-always-on;
	92	regulator-boot-on;
	93	};
	94
e9c17866 AS	95	/* SW2A and SW2B joined operation */
e9c17866 AS	96	sw2_reg: sw2a {
5d3503cd AS	97	regulator-min-microvolt = <1800000>;
	98	regulator-max-microvolt = <1800000>;
	99	regulator-always-on;
	100	regulator-boot-on;
	101	};
	102
	103	sw3_reg: sw3 {
	104	regulator-min-microvolt = <5000000>;
	105	regulator-max-microvolt = <5000000>;
	106	regulator-always-on;
	107	regulator-boot-on;
	108	};
	109
	110	vaudio_reg: vaudio {
	111	regulator-always-on;
	112	regulator-boot-on;
	113	};
	114
	115	violo_reg: violo {
	116	regulator-min-microvolt = <1800000>;
	117	regulator-max-microvolt = <1800000>;
	118	regulator-always-on;
	119	regulator-boot-on;
	120	};
	121
	122	viohi_reg: viohi {
	123	regulator-always-on;
	124	regulator-boot-on;
	125	};
	126
	127	vgen_reg: vgen {
	128	regulator-min-microvolt = <1500000>;
	129	regulator-max-microvolt = <1500000>;
	130	regulator-always-on;
	131	regulator-boot-on;
	132	};
	133
	134	vcam_reg: vcam {
	135	regulator-min-microvolt = <2800000>;
	136	regulator-max-microvolt = <2800000>;
	137	};
	138
	139	vrf1_reg: vrf1 {
	140	regulator-min-microvolt = <2775000>;
	141	regulator-max-microvolt = <2775000>;
	142	regulator-always-on;
	143	regulator-boot-on;
	144	};
	145
	146	vrf2_reg: vrf2 {
	147	regulator-min-microvolt = <2775000>;
	148	regulator-max-microvolt = <2775000>;
	149	regulator-always-on;
	150	regulator-boot-on;
	151	};
	152
	153	vmmc1_reg: vmmc1 {
	154	regulator-min-microvolt = <1600000>;
	155	regulator-max-microvolt = <3000000>;
	156	};
	157
	158	gpo1_reg: gpo1 { };
	159
	160	pwgt1spi_reg: pwgt1spi {
161	regulator-always-on;
162	};
163	};
164	};
165	};
166
f0d8e3f1	167	&fec {
f64ba746	168	phy-mode = "mii";
6ece55b3	169	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
f64ba746	170	phy-supply = <&reg_3v3>;
26508cb7 MP	171	pinctrl-names = "default";
26508cb7 MP	172	pinctrl-0 = <&pinctrl_fec1>;
f0d8e3f1 AS	173	status = "okay";
	174	};
	175
	176	&i2c2 {
	177	clock-frequency = <400000>;
26508cb7 MP	178	pinctrl-names = "default";
26508cb7 MP	179	pinctrl-0 = <&pinctrl_i2c2>;
f0d8e3f1 AS	180	status = "okay";
	181
	182	at24@52 {
	183	compatible = "at,24c32";
	184	pagesize = <32>;
	185	reg = <0x52>;
	186	};
	187
	188	pcf8563@51 {
	189	compatible = "nxp,pcf8563";
	190	reg = <0x51>;
	191	};
	192
	193	lm75@4a {
	194	compatible = "national,lm75";
	195	reg = <0x4a>;
	196	};
	197	};
	198
26508cb7 MP	199	&iomuxc {
26508cb7 MP	200	imx27_phycore_som {
f4bdf215 AS	201	pinctrl_cspi1: cspi1grp {
	202	fsl,pins = <
	203	MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
	204	MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
	205	MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
	206	MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
	207	MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
	208	>;
	209	};
	210
26508cb7 MP	211	pinctrl_fec1: fec1grp {
	212	fsl,pins = <
	213	MX27_PAD_SD3_CMD__FEC_TXD0 0x0
	214	MX27_PAD_SD3_CLK__FEC_TXD1 0x0
	215	MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
	216	MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
	217	MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
	218	MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
	219	MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
	220	MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
	221	MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
	222	MX27_PAD_ATA_DATA7__FEC_MDC 0x0
	223	MX27_PAD_ATA_DATA8__FEC_CRS 0x0
	224	MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
	225	MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
	226	MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
	227	MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
	228	MX27_PAD_ATA_DATA13__FEC_COL 0x0
	229	MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
	230	MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
	231	MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
	232	>;
	233	};
	234
	235	pinctrl_i2c2: i2c2grp {
	236	fsl,pins = <
	237	MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
	238	MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
	239	>;
	240	};
dde56973 AS	241
	242	pinctrl_nfc: nfcgrp {
	243	fsl,pins = <
	244	MX27_PAD_NFRB__NFRB 0x0
	245	MX27_PAD_NFCLE__NFCLE 0x0
	246	MX27_PAD_NFWP_B__NFWP_B 0x0
	247	MX27_PAD_NFCE_B__NFCE_B 0x0
	248	MX27_PAD_NFALE__NFALE 0x0
	249	MX27_PAD_NFRE_B__NFRE_B 0x0
	250	MX27_PAD_NFWE_B__NFWE_B 0x0
	251	>;
	252	};
74ded659	253
2c405689 AS	254	pinctrl_ssi1: ssi1grp {
	255	fsl,pins = <
	256	MX27_PAD_SSI1_FS__SSI1_FS 0x0
	257	MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
	258	MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
	259	MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
	260	>;
	261	};
	262
74ded659 AS	263	pinctrl_usbotg: usbotggrp {
	264	fsl,pins = <
	265	MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
	266	MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
	267	MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
	268	MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
	269	MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
	270	MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
	271	MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
	272	MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
	273	MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
	274	MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
	275	MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
	276	MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
	277	>;
	278	};
26508cb7 MP	279	};
	280	};
	281
1b45aceb	282	&nfc {
dde56973 AS	283	pinctrl-names = "default";
dde56973 AS	284	pinctrl-0 = <&pinctrl_nfc>;
1b45aceb AS	285	nand-bus-width = <8>;
1b45aceb AS	286	nand-ecc-mode = "hw";
d9a57aaf	287	nand-on-flash-bbt;
1b45aceb AS	288	status = "okay";
1b45aceb AS	289	};
984d6fc3	290
2c405689 AS	291	&ssi1 {
	292	pinctrl-names = "default";
	293	pinctrl-0 = <&pinctrl_ssi1>;
	294	fsl,mode = "i2s-slave";
	295	status = "okay";
	296	};
	297
74ded659 AS	298	&usbotg {
	299	pinctrl-names = "default";
	300	pinctrl-0 = <&pinctrl_usbotg>;
	301	dr_mode = "otg";
	302	phy_type = "ulpi";
	303	vbus-supply = <&sw3_reg>;
	304	status = "okay";
	305	};
	306
	307	&usbphy0 {
	308	vcc-supply = <&sw3_reg>;
	309	};
	310
984d6fc3 AS	311	&weim {
	312	status = "okay";
	313
3c3ea296	314	nor: nor@0,0 {
984d6fc3 AS	315	compatible = "cfi-flash";
	316	reg = <0 0x00000000 0x02000000>;
	317	bank-width = <2>;
	318	linux,mtd-name = "physmap-flash.0";
	319	fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
	320	#address-cells = <1>;
	321	#size-cells = <1>;
	322	};
cff2a713	323
3c3ea296	324	sram: sram@1,0 {
cff2a713 AS	325	compatible = "mtd-ram";
	326	reg = <1 0x00000000 0x00800000>;
	327	bank-width = <2>;
	328	linux,mtd-name = "mtd-ram.0";
	329	fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
	330	#address-cells = <1>;
	331	#size-cells = <1>;
	332	};
984d6fc3	333	};