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860c06f6 FE |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | /dts-v1/; | |
36dffd8f | 13 | #include "imx25.dtsi" |
860c06f6 FE |
14 | |
15 | / { | |
16 | model = "Freescale i.MX25 Product Development Kit"; | |
17 | compatible = "fsl,imx25-pdk", "fsl,imx25"; | |
18 | ||
19 | memory { | |
20 | reg = <0x80000000 0x4000000>; | |
21 | }; | |
6e3ef2f6 FE |
22 | |
23 | regulators { | |
24 | compatible = "simple-bus"; | |
25 | #address-cells = <1>; | |
26 | #size-cells = <0>; | |
27 | ||
28 | reg_fec_3v3: regulator@0 { | |
29 | compatible = "regulator-fixed"; | |
30 | reg = <0>; | |
31 | regulator-name = "fec-3v3"; | |
32 | regulator-min-microvolt = <3300000>; | |
33 | regulator-max-microvolt = <3300000>; | |
34 | gpio = <&gpio2 3 0>; | |
35 | enable-active-high; | |
36 | }; | |
37 | }; | |
860c06f6 FE |
38 | }; |
39 | ||
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40 | &esdhc1 { |
41 | pinctrl-names = "default"; | |
42 | pinctrl-0 = <&pinctrl_esdhc1>; | |
43 | cd-gpios = <&gpio2 1 0>; | |
44 | wp-gpios = <&gpio2 0 0>; | |
45 | status = "okay"; | |
46 | }; | |
47 | ||
860c06f6 FE |
48 | &fec { |
49 | phy-mode = "rmii"; | |
f0bd6881 FE |
50 | pinctrl-names = "default"; |
51 | pinctrl-0 = <&pinctrl_fec>; | |
6e3ef2f6 | 52 | phy-supply = <®_fec_3v3>; |
c7b15c28 | 53 | phy-reset-gpios = <&gpio4 8 0>; |
860c06f6 FE |
54 | status = "okay"; |
55 | }; | |
56 | ||
53ba9c70 FE |
57 | &iomuxc { |
58 | imx25-pdk { | |
707e6906 FE |
59 | pinctrl_esdhc1: esdhc1grp { |
60 | fsl,pins = < | |
61 | MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 | |
62 | MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 | |
63 | MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 | |
64 | MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 | |
65 | MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 | |
66 | MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 | |
67 | MX25_PAD_A14__GPIO_2_0 0x80000000 | |
68 | MX25_PAD_A15__GPIO_2_1 0x80000000 | |
69 | >; | |
70 | }; | |
71 | ||
f0bd6881 FE |
72 | pinctrl_fec: fecgrp { |
73 | fsl,pins = < | |
74 | MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 | |
75 | MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 | |
76 | MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 | |
77 | MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 | |
78 | MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | |
79 | MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 | |
80 | MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 | |
81 | MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 | |
82 | MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 | |
6e3ef2f6 | 83 | MX25_PAD_A17__GPIO_2_3 0x80000000 |
c7b15c28 | 84 | MX25_PAD_D12__GPIO_4_8 0x80000000 |
f0bd6881 FE |
85 | >; |
86 | }; | |
87 | ||
53ba9c70 FE |
88 | pinctrl_uart1: uart1grp { |
89 | fsl,pins = < | |
90 | MX25_PAD_UART1_RTS__UART1_RTS 0xe0 | |
91 | MX25_PAD_UART1_CTS__UART1_CTS 0xe0 | |
92 | MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 | |
93 | MX25_PAD_UART1_RXD__UART1_RXD 0xc0 | |
94 | >; | |
95 | }; | |
96 | }; | |
97 | }; | |
98 | ||
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99 | &nfc { |
100 | nand-on-flash-bbt; | |
101 | status = "okay"; | |
102 | }; | |
8617cb0b FE |
103 | |
104 | &uart1 { | |
53ba9c70 FE |
105 | pinctrl-names = "default"; |
106 | pinctrl-0 = <&pinctrl_uart1>; | |
107 | fsl,uart-has-rtscts; | |
8617cb0b FE |
108 | status = "okay"; |
109 | }; |