[linux-2.6-block.git] / arch / arm / boot / dts / imx25-pdk.dts

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx25.dtsi"

/ {
	model = "Freescale i.MX25 Product Development Kit";
	compatible = "fsl,imx25-pdk", "fsl,imx25";

	memory {
		reg = <0x80000000 0x4000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_fec_3v3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "fec-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio2 3 0>;
			enable-active-high;
		};

		reg_2p5v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
		};

		reg_3p3v: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

	};

	sound {
		compatible = "fsl,imx25-pdk-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx25-pdk-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <4>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	cd-gpios = <&gpio2 1 0>;
	wp-gpios = <&gpio2 0 0>;
	status = "okay";
};

&fec {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-supply = <&reg_fec_3v3>;
	phy-reset-gpios = <&gpio4 8 0>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	codec: sgtl5000@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 129>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&iomuxc {
	imx25-pdk {
		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX25_PAD_RW__AUD4_TXFS			0xe0
				MX25_PAD_OE__AUD4_TXC			0xe0
				MX25_PAD_EB0__AUD4_TXD			0xe0
				MX25_PAD_EB1__AUD4_RXD			0xe0
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX25_PAD_SD1_CMD__SD1_CMD		0x80000000
				MX25_PAD_SD1_CLK__SD1_CLK		0x80000000
				MX25_PAD_SD1_DATA0__SD1_DATA0		0x80000000
				MX25_PAD_SD1_DATA1__SD1_DATA1		0x80000000
				MX25_PAD_SD1_DATA2__SD1_DATA2		0x80000000
				MX25_PAD_SD1_DATA3__SD1_DATA3		0x80000000
				MX25_PAD_A14__GPIO_2_0			0x80000000
				MX25_PAD_A15__GPIO_2_1			0x80000000
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
				MX25_PAD_A17__GPIO_2_3			0x80000000
				MX25_PAD_D12__GPIO_4_8			0x80000000
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
			>;
		};

		pinctrl_kpp: kppgrp {
			fsl,pins = <
				MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
				MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
				MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
				MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
				MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
				MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
				MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
				MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
			>;
		};


		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
			>;
		};
	};
};

&nfc {
	nand-on-flash-bbt;
	status = "okay";
};

&kpp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_kpp>;
	linux,keymap = <
			MATRIX_KEY(0x0, 0x0, KEY_UP)
			MATRIX_KEY(0x0, 0x1, KEY_DOWN)
			MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
			MATRIX_KEY(0x0, 0x3, KEY_HOME)
			MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
			MATRIX_KEY(0x1, 0x1, KEY_LEFT)
			MATRIX_KEY(0x1, 0x2, KEY_ENTER)
			MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
			MATRIX_KEY(0x2, 0x0, KEY_F6)
			MATRIX_KEY(0x2, 0x1, KEY_F8)
			MATRIX_KEY(0x2, 0x2, KEY_F9)
			MATRIX_KEY(0x2, 0x3, KEY_F10)
			MATRIX_KEY(0x3, 0x0, KEY_F1)
			MATRIX_KEY(0x3, 0x1, KEY_F2)
			MATRIX_KEY(0x3, 0x2, KEY_F3)
			MATRIX_KEY(0x3, 0x2, KEY_POWER)
	>;
	status = "okay";
};

&ssi1 {
	codec-handle = <&codec>;
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	fsl,uart-has-rtscts;
	status = "okay";
};
Commit	Line	Data
860c06f6 FE	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	/dts-v1/;
9223dd87	13	#include <dt-bindings/input/input.h>
36dffd8f	14	#include "imx25.dtsi"
860c06f6 FE	15
	16	/ {
	17	model = "Freescale i.MX25 Product Development Kit";
	18	compatible = "fsl,imx25-pdk", "fsl,imx25";
	19
	20	memory {
	21	reg = <0x80000000 0x4000000>;
	22	};
6e3ef2f6 FE	23
	24	regulators {
	25	compatible = "simple-bus";
	26	#address-cells = <1>;
	27	#size-cells = <0>;
	28
	29	reg_fec_3v3: regulator@0 {
	30	compatible = "regulator-fixed";
	31	reg = <0>;
	32	regulator-name = "fec-3v3";
	33	regulator-min-microvolt = <3300000>;
	34	regulator-max-microvolt = <3300000>;
	35	gpio = <&gpio2 3 0>;
	36	enable-active-high;
	37	};
35d2bc8c FE	38
	39	reg_2p5v: regulator@1 {
	40	compatible = "regulator-fixed";
	41	reg = <1>;
	42	regulator-name = "2P5V";
	43	regulator-min-microvolt = <2500000>;
	44	regulator-max-microvolt = <2500000>;
	45	};
	46
	47	reg_3p3v: regulator@2 {
	48	compatible = "regulator-fixed";
	49	reg = <2>;
	50	regulator-name = "3P3V";
	51	regulator-min-microvolt = <3300000>;
	52	regulator-max-microvolt = <3300000>;
	53	};
	54
	55	};
	56
	57	sound {
	58	compatible = "fsl,imx25-pdk-sgtl5000",
	59	"fsl,imx-audio-sgtl5000";
	60	model = "imx25-pdk-sgtl5000";
	61	ssi-controller = <&ssi1>;
	62	audio-codec = <&codec>;
	63	audio-routing =
	64	"MIC_IN", "Mic Jack",
	65	"Mic Jack", "Mic Bias",
	66	"Headphone Jack", "HP_OUT";
	67	mux-int-port = <1>;
	68	mux-ext-port = <4>;
6e3ef2f6	69	};
860c06f6 FE	70	};
860c06f6 FE	71
35d2bc8c FE	72	&audmux {
	73	pinctrl-names = "default";
	74	pinctrl-0 = <&pinctrl_audmux>;
	75	status = "okay";
	76	};
	77
707e6906 FE	78	&esdhc1 {
	79	pinctrl-names = "default";
	80	pinctrl-0 = <&pinctrl_esdhc1>;
	81	cd-gpios = <&gpio2 1 0>;
	82	wp-gpios = <&gpio2 0 0>;
	83	status = "okay";
	84	};
	85
860c06f6 FE	86	&fec {
860c06f6 FE	87	phy-mode = "rmii";
f0bd6881 FE	88	pinctrl-names = "default";
f0bd6881 FE	89	pinctrl-0 = <&pinctrl_fec>;
6e3ef2f6	90	phy-supply = <&reg_fec_3v3>;
c7b15c28	91	phy-reset-gpios = <&gpio4 8 0>;
860c06f6 FE	92	status = "okay";
	93	};
	94
35d2bc8c FE	95	&i2c1 {
	96	clock-frequency = <100000>;
	97	pinctrl-names = "default";
	98	pinctrl-0 = <&pinctrl_i2c1>;
	99	status = "okay";
	100
	101	codec: sgtl5000@0a {
	102	compatible = "fsl,sgtl5000";
	103	reg = <0x0a>;
	104	clocks = <&clks 129>;
	105	VDDA-supply = <&reg_2p5v>;
	106	VDDIO-supply = <&reg_3p3v>;
	107	};
	108	};
	109
53ba9c70 FE	110	&iomuxc {
53ba9c70 FE	111	imx25-pdk {
35d2bc8c FE	112	pinctrl_audmux: audmuxgrp {
	113	fsl,pins = <
	114	MX25_PAD_RW__AUD4_TXFS 0xe0
	115	MX25_PAD_OE__AUD4_TXC 0xe0
	116	MX25_PAD_EB0__AUD4_TXD 0xe0
	117	MX25_PAD_EB1__AUD4_RXD 0xe0
	118	>;
	119	};
	120
707e6906 FE	121	pinctrl_esdhc1: esdhc1grp {
	122	fsl,pins = <
	123	MX25_PAD_SD1_CMD__SD1_CMD 0x80000000
	124	MX25_PAD_SD1_CLK__SD1_CLK 0x80000000
	125	MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000
	126	MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000
	127	MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000
	128	MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000
	129	MX25_PAD_A14__GPIO_2_0 0x80000000
	130	MX25_PAD_A15__GPIO_2_1 0x80000000
	131	>;
	132	};
	133
f0bd6881 FE	134	pinctrl_fec: fecgrp {
	135	fsl,pins = <
	136	MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
	137	MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
	138	MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
	139	MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
	140	MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
	141	MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
	142	MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
	143	MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
	144	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
6e3ef2f6	145	MX25_PAD_A17__GPIO_2_3 0x80000000
c7b15c28	146	MX25_PAD_D12__GPIO_4_8 0x80000000
f0bd6881 FE	147	>;
	148	};
	149
35d2bc8c FE	150	pinctrl_i2c1: i2c1grp {
	151	fsl,pins = <
	152	MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
	153	MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
	154	>;
	155	};
	156
9223dd87 FE	157	pinctrl_kpp: kppgrp {
	158	fsl,pins = <
	159	MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000
	160	MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000
	161	MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000
	162	MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
	163	MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
	164	MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
	165	MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
	166	MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
	167	>;
	168	};
	169
	170
53ba9c70 FE	171	pinctrl_uart1: uart1grp {
	172	fsl,pins = <
	173	MX25_PAD_UART1_RTS__UART1_RTS 0xe0
	174	MX25_PAD_UART1_CTS__UART1_CTS 0xe0
	175	MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
	176	MX25_PAD_UART1_RXD__UART1_RXD 0xc0
	177	>;
	178	};
	179	};
	180	};
	181
860c06f6 FE	182	&nfc {
	183	nand-on-flash-bbt;
	184	status = "okay";
	185	};
8617cb0b	186
9223dd87 FE	187	&kpp {
	188	pinctrl-names = "default";
	189	pinctrl-0 = <&pinctrl_kpp>;
	190	linux,keymap = <
	191	MATRIX_KEY(0x0, 0x0, KEY_UP)
	192	MATRIX_KEY(0x0, 0x1, KEY_DOWN)
	193	MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
	194	MATRIX_KEY(0x0, 0x3, KEY_HOME)
	195	MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
	196	MATRIX_KEY(0x1, 0x1, KEY_LEFT)
	197	MATRIX_KEY(0x1, 0x2, KEY_ENTER)
	198	MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
	199	MATRIX_KEY(0x2, 0x0, KEY_F6)
	200	MATRIX_KEY(0x2, 0x1, KEY_F8)
	201	MATRIX_KEY(0x2, 0x2, KEY_F9)
	202	MATRIX_KEY(0x2, 0x3, KEY_F10)
	203	MATRIX_KEY(0x3, 0x0, KEY_F1)
	204	MATRIX_KEY(0x3, 0x1, KEY_F2)
	205	MATRIX_KEY(0x3, 0x2, KEY_F3)
	206	MATRIX_KEY(0x3, 0x2, KEY_POWER)
	207	>;
	208	status = "okay";
	209	};
	210
35d2bc8c FE	211	&ssi1 {
	212	codec-handle = <&codec>;
	213	fsl,mode = "i2s-slave";
	214	status = "okay";
	215	};
	216
8617cb0b	217	&uart1 {
53ba9c70 FE	218	pinctrl-names = "default";
	219	pinctrl-0 = <&pinctrl_uart1>;
	220	fsl,uart-has-rtscts;
8617cb0b FE	221	status = "okay";
8617cb0b FE	222	};