projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 62300cbf SH |
1 | /* |
| 2 | * Copyright 2012 Sascha Hauer, Pengutronix | |
| 3 | * | |
| 4 | * The code contained herein is licensed under the GNU General Public | |
| 5 | * License. You may obtain a copy of the GNU General Public License | |
| 6 | * Version 2 or later at the following locations: | |
| 7 | * | |
| 8 | * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | * http://www.gnu.org/copyleft/gpl.html | |
| 10 | */ | |
| 11 | ||
| 12 | /dts-v1/; | |
| 36dffd8f | 13 | #include "imx25.dtsi" |
| 62300cbf SH |
14 | |
| 15 | / { | |
| 16 | model = "Ka-Ro TX25"; | |
| 17 | compatible = "karo,imx25-tx25", "fsl,imx25"; | |
| 18 | ||
| 48f51963 SH |
19 | chosen { |
| 20 | stdout-path = &uart1; | |
| 21 | }; | |
| 22 | ||
| 62300cbf SH |
23 | memory { |
| 24 | reg = <0x80000000 0x02000000 0x90000000 0x02000000>; | |
| 25 | }; | |
| be4ccfce | 26 | }; |
| 62300cbf | 27 | |
| 8d69043d SH |
28 | &iomuxc { |
| 29 | pinctrl_uart1: uart1grp { | |
| 30 | fsl,pins = < | |
| 31 | MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 | |
| 32 | MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 | |
| 33 | MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 | |
| 34 | MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 | |
| 35 | >; | |
| 36 | }; | |
| 37 | ||
| 38 | pinctrl_fec: fecgrp { | |
| 39 | fsl,pins = < | |
| 40 | MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ | |
| 41 | MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ | |
| 42 | MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 | |
| 43 | MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | |
| 44 | MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 | |
| 45 | MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 | |
| 46 | MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | |
| 47 | MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 | |
| 48 | MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 | |
| 49 | MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 | |
| 50 | MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 | |
| 51 | >; | |
| 52 | }; | |
| 53 | ||
| 54 | pinctrl_nfc: nfcgrp { | |
| 55 | fsl,pins = < | |
| 56 | MX25_PAD_NF_CE0__NF_CE0 0x80000000 | |
| 57 | MX25_PAD_NFWE_B__NFWE_B 0x80000000 | |
| 58 | MX25_PAD_NFRE_B__NFRE_B 0x80000000 | |
| 59 | MX25_PAD_NFALE__NFALE 0x80000000 | |
| 60 | MX25_PAD_NFCLE__NFCLE 0x80000000 | |
| 61 | MX25_PAD_NFWP_B__NFWP_B 0x80000000 | |
| 62 | MX25_PAD_NFRB__NFRB 0x80000000 | |
| 63 | MX25_PAD_D7__D7 0x80000000 | |
| 64 | MX25_PAD_D6__D6 0x80000000 | |
| 65 | MX25_PAD_D5__D5 0x80000000 | |
| 66 | MX25_PAD_D4__D4 0x80000000 | |
| 67 | MX25_PAD_D3__D3 0x80000000 | |
| 68 | MX25_PAD_D2__D2 0x80000000 | |
| 69 | MX25_PAD_D1__D1 0x80000000 | |
| 70 | MX25_PAD_D0__D0 0x80000000 | |
| 71 | >; | |
| 72 | }; | |
| 73 | }; | |
| 74 | ||
| be4ccfce | 75 | &uart1 { |
| 8d69043d SH |
76 | pinctrl-names = "default"; |
| 77 | pinctrl-0 = <&pinctrl_uart1>; | |
| be4ccfce SG |
78 | status = "okay"; |
| 79 | }; | |
| 62300cbf | 80 | |
| be4ccfce | 81 | &fec { |
| 8d69043d SH |
82 | pinctrl-names = "default"; |
| 83 | pinctrl-0 = <&pinctrl_fec>; | |
| be4ccfce | 84 | phy-mode = "rmii"; |
| 152fab67 | 85 | status = "okay"; |
| be4ccfce | 86 | }; |
| 62300cbf | 87 | |
| be4ccfce | 88 | &nfc { |
| 8d69043d SH |
89 | pinctrl-names = "default"; |
| 90 | pinctrl-0 = <&pinctrl_nfc>; | |
| be4ccfce SG |
91 | nand-on-flash-bbt; |
| 92 | status = "okay"; | |
| 62300cbf | 93 | }; |