[linux-2.6-block.git] / arch / arm / boot / dts / imx25-karo-tx25.dts

/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx25.dtsi"

/ {
	model = "Ka-Ro TX25";
	compatible = "karo,imx25-tx25", "fsl,imx25";

	chosen {
		stdout-path = &uart1;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_fec_phy: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "fec-phy";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 9 0>;
			enable-active-high;
		};
	};

	memory {
		reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
	};
};

&iomuxc {
	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
			MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
			MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
			MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX25_PAD_D11__GPIO_4_9		0x80000000 /* FEC PHY power on pin */
			MX25_PAD_D13__GPIO_4_7		0x80000000 /* FEC reset */
			MX25_PAD_FEC_MDC__FEC_MDC	0x80000000
			MX25_PAD_FEC_MDIO__FEC_MDIO	0x80000000
			MX25_PAD_FEC_TDATA0__FEC_TDATA0	0x80000000
			MX25_PAD_FEC_TDATA1__FEC_TDATA1	0x80000000
			MX25_PAD_FEC_TX_EN__FEC_TX_EN	0x80000000
			MX25_PAD_FEC_RDATA0__FEC_RDATA0	0x80000000
			MX25_PAD_FEC_RDATA1__FEC_RDATA1	0x80000000
			MX25_PAD_FEC_RX_DV__FEC_RX_DV	0x80000000
			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK	0x80000000
		>;
	};

	pinctrl_nfc: nfcgrp {
		fsl,pins = <
			MX25_PAD_NF_CE0__NF_CE0		0x80000000
			MX25_PAD_NFWE_B__NFWE_B		0x80000000
			MX25_PAD_NFRE_B__NFRE_B		0x80000000
			MX25_PAD_NFALE__NFALE		0x80000000
			MX25_PAD_NFCLE__NFCLE		0x80000000
			MX25_PAD_NFWP_B__NFWP_B		0x80000000
			MX25_PAD_NFRB__NFRB		0x80000000
			MX25_PAD_D7__D7			0x80000000
			MX25_PAD_D6__D6			0x80000000
			MX25_PAD_D5__D5			0x80000000
			MX25_PAD_D4__D4			0x80000000
			MX25_PAD_D3__D3			0x80000000
			MX25_PAD_D2__D2			0x80000000
			MX25_PAD_D1__D1			0x80000000
			MX25_PAD_D0__D0			0x80000000
		>;
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-reset-gpios = <&gpio3 7 0>;
	phy-mode = "rmii";
	phy-supply = <&reg_fec_phy>;
	status = "okay";
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	nand-on-flash-bbt;
	nand-ecc-mode = "hw";
	nand-bus-width = <8>;
	status = "okay";
};
Commit	Line	Data
62300cbf SH	1	/*
	2	* Copyright 2012 Sascha Hauer, Pengutronix
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	/dts-v1/;
36dffd8f	13	#include "imx25.dtsi"
62300cbf SH	14
	15	/ {
	16	model = "Ka-Ro TX25";
	17	compatible = "karo,imx25-tx25", "fsl,imx25";
	18
48f51963 SH	19	chosen {
	20	stdout-path = &uart1;
	21	};
	22
974e5872 SH	23	regulators {
	24	compatible = "simple-bus";
	25	#address-cells = <1>;
	26	#size-cells = <0>;
	27
	28	reg_fec_phy: regulator@0 {
	29	compatible = "regulator-fixed";
	30	reg = <0>;
	31	regulator-name = "fec-phy";
	32	regulator-min-microvolt = <3300000>;
	33	regulator-max-microvolt = <3300000>;
	34	gpio = <&gpio4 9 0>;
	35	enable-active-high;
	36	};
	37	};
	38
62300cbf SH	39	memory {
	40	reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
	41	};
be4ccfce	42	};
62300cbf	43
8d69043d SH	44	&iomuxc {
	45	pinctrl_uart1: uart1grp {
	46	fsl,pins = <
	47	MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
	48	MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
	49	MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
	50	MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
	51	>;
	52	};
	53
	54	pinctrl_fec: fecgrp {
	55	fsl,pins = <
	56	MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
	57	MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */
	58	MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
	59	MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000
	60	MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
	61	MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
	62	MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
	63	MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
	64	MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
	65	MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
	66	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
	67	>;
	68	};
	69
	70	pinctrl_nfc: nfcgrp {
	71	fsl,pins = <
	72	MX25_PAD_NF_CE0__NF_CE0 0x80000000
	73	MX25_PAD_NFWE_B__NFWE_B 0x80000000
	74	MX25_PAD_NFRE_B__NFRE_B 0x80000000
	75	MX25_PAD_NFALE__NFALE 0x80000000
	76	MX25_PAD_NFCLE__NFCLE 0x80000000
	77	MX25_PAD_NFWP_B__NFWP_B 0x80000000
	78	MX25_PAD_NFRB__NFRB 0x80000000
	79	MX25_PAD_D7__D7 0x80000000
	80	MX25_PAD_D6__D6 0x80000000
	81	MX25_PAD_D5__D5 0x80000000
	82	MX25_PAD_D4__D4 0x80000000
	83	MX25_PAD_D3__D3 0x80000000
	84	MX25_PAD_D2__D2 0x80000000
	85	MX25_PAD_D1__D1 0x80000000
	86	MX25_PAD_D0__D0 0x80000000
	87	>;
	88	};
	89	};
	90
be4ccfce	91	&uart1 {
8d69043d SH	92	pinctrl-names = "default";
8d69043d SH	93	pinctrl-0 = <&pinctrl_uart1>;
be4ccfce SG	94	status = "okay";
be4ccfce SG	95	};
62300cbf	96
be4ccfce	97	&fec {
8d69043d SH	98	pinctrl-names = "default";
8d69043d SH	99	pinctrl-0 = <&pinctrl_fec>;
974e5872	100	phy-reset-gpios = <&gpio3 7 0>;
be4ccfce	101	phy-mode = "rmii";
974e5872	102	phy-supply = <&reg_fec_phy>;
152fab67	103	status = "okay";
be4ccfce	104	};
62300cbf	105
be4ccfce	106	&nfc {
8d69043d SH	107	pinctrl-names = "default";
8d69043d SH	108	pinctrl-0 = <&pinctrl_nfc>;
be4ccfce	109	nand-on-flash-bbt;
1885e5de SH	110	nand-ecc-mode = "hw";
1885e5de SH	111	nand-bus-width = <8>;
be4ccfce	112	status = "okay";
62300cbf	113	};