[linux-2.6-block.git] / arch / arm / boot / dts / hisi-x5hd2-dkb.dts

/*
 * Copyright (c) 2013-2014 Linaro Ltd.
 * Copyright (c) 2013-2014 Hisilicon Limited.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  publishhed by the Free Software Foundation.
 */

/dts-v1/;
#include "hisi-x5hd2.dtsi"

/ {
	model = "Hisilicon HIX5HD2 Development Board";
	compatible = "hisilicon,hix5hd2";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "hisilicon,hix5hd2-smp";

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&l2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&l2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000>;
	};
};

&timer0 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&gmac0 {
	#address-cells = <1>;
	#size-cells = <0>;
	phy-handle = <&phy2>;
	phy-mode = "mii";
	/* Placeholder, overwritten by bootloader */
	mac-address = [00 00 00 00 00 00];
	status = "okay";

	phy2: ethernet-phy@2 {
		reg = <2>;
	};
};

&gmac1 {
	#address-cells = <1>;
	#size-cells = <0>;
	phy-handle = <&phy1>;
	phy-mode = "rgmii";
	/* Placeholder, overwritten by bootloader */
	mac-address = [00 00 00 00 00 00];
	status = "okay";

	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&ahci {
	phys = <&sata_phy>;
	phy-names = "sata-phy";
};
Commit	Line	Data
75a4795a HY	1	/*
	2	* Copyright (c) 2013-2014 Linaro Ltd.
	3	* Copyright (c) 2013-2014 Hisilicon Limited.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
	9
	10	/dts-v1/;
	11	#include "hisi-x5hd2.dtsi"
	12
	13	/ {
	14	model = "Hisilicon HIX5HD2 Development Board";
	15	compatible = "hisilicon,hix5hd2";
	16
	17	chosen {
14317946	18	stdout-path = "serial0:115200n8";
75a4795a HY	19	};
	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
c2fff85e	24	enable-method = "hisilicon,hix5hd2-smp";
75a4795a HY	25
	26	cpu@0 {
	27	compatible = "arm,cortex-a9";
	28	device_type = "cpu";
	29	reg = <0>;
	30	next-level-cache = <&l2>;
	31	};
	32
	33	cpu@1 {
	34	compatible = "arm,cortex-a9";
	35	device_type = "cpu";
	36	reg = <1>;
	37	next-level-cache = <&l2>;
	38	};
	39	};
	40
	41	memory {
	42	device_type = "memory";
	43	reg = <0x00000000 0x80000000>;
	44	};
	45	};
	46
	47	&timer0 {
	48	status = "okay";
	49	};
	50
	51	&uart0 {
	52	status = "okay";
	53	};
9fb0e6e7 ZG	54
	55	&gmac0 {
	56	#address-cells = <1>;
	57	#size-cells = <0>;
	58	phy-handle = <&phy2>;
	59	phy-mode = "mii";
	60	/* Placeholder, overwritten by bootloader */
	61	mac-address = [00 00 00 00 00 00];
	62	status = "okay";
	63
	64	phy2: ethernet-phy@2 {
	65	reg = <2>;
	66	};
	67	};
	68
	69	&gmac1 {
	70	#address-cells = <1>;
	71	#size-cells = <0>;
	72	phy-handle = <&phy1>;
	73	phy-mode = "rgmii";
	74	/* Placeholder, overwritten by bootloader */
	75	mac-address = [00 00 00 00 00 00];
	76	status = "okay";
	77
	78	phy1: ethernet-phy@1 {
	79	reg = <1>;
	80	};
	81	};
a47f88ef ZG	82
	83	&ahci {
	84	phys = <&sata_phy>;
	85	phy-names = "sata-phy";
	86	};