projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 4f0d20ec KK |
1 | /* |
| 2 | * SAMSUNG EXYNOS5420 SoC cpu device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * This file provides desired ordering for Exynos5420 and Exynos5800 | |
| 8 | * boards: CPU[0123] being the A15. | |
| 9 | * | |
| 10 | * The Exynos5420, 5422 and 5800 actually share the same CPU configuration | |
| 11 | * but particular boards choose different booting order. | |
| 12 | * | |
| 13 | * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 | |
| 14 | * booting cluster (big or LITTLE) is chosen by IROM code by reading | |
| 15 | * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting | |
| 16 | * from the LITTLE: Cortex-A7. | |
| 17 | * | |
| 18 | * This program is free software; you can redistribute it and/or modify | |
| 19 | * it under the terms of the GNU General Public License version 2 as | |
| 20 | * published by the Free Software Foundation. | |
| 21 | */ | |
| 22 | ||
| 23 | / { | |
| 24 | cpus { | |
| 25 | #address-cells = <1>; | |
| 26 | #size-cells = <0>; | |
| 27 | ||
| 28 | cpu0: cpu@0 { | |
| 29 | device_type = "cpu"; | |
| 30 | compatible = "arm,cortex-a15"; | |
| 31 | reg = <0x0>; | |
| 66a4a1fb | 32 | clocks = <&clock CLK_ARM_CLK>; |
| 4f0d20ec KK |
33 | clock-frequency = <1800000000>; |
| 34 | cci-control-port = <&cci_control1>; | |
| 66a4a1fb | 35 | operating-points-v2 = <&cluster_a15_opp_table>; |
| 65ebf53f KK |
36 | cooling-min-level = <0>; |
| 37 | cooling-max-level = <11>; | |
| 38 | #cooling-cells = <2>; /* min followed by max */ | |
| 45bfc2a3 | 39 | capacity-dmips-mhz = <1024>; |
| 4f0d20ec KK |
40 | }; |
| 41 | ||
| 42 | cpu1: cpu@1 { | |
| 43 | device_type = "cpu"; | |
| 44 | compatible = "arm,cortex-a15"; | |
| 45 | reg = <0x1>; | |
| 46 | clock-frequency = <1800000000>; | |
| 47 | cci-control-port = <&cci_control1>; | |
| 66a4a1fb | 48 | operating-points-v2 = <&cluster_a15_opp_table>; |
| 65ebf53f KK |
49 | cooling-min-level = <0>; |
| 50 | cooling-max-level = <11>; | |
| 51 | #cooling-cells = <2>; /* min followed by max */ | |
| 45bfc2a3 | 52 | capacity-dmips-mhz = <1024>; |
| 4f0d20ec KK |
53 | }; |
| 54 | ||
| 55 | cpu2: cpu@2 { | |
| 56 | device_type = "cpu"; | |
| 57 | compatible = "arm,cortex-a15"; | |
| 58 | reg = <0x2>; | |
| 59 | clock-frequency = <1800000000>; | |
| 60 | cci-control-port = <&cci_control1>; | |
| 66a4a1fb | 61 | operating-points-v2 = <&cluster_a15_opp_table>; |
| 65ebf53f KK |
62 | cooling-min-level = <0>; |
| 63 | cooling-max-level = <11>; | |
| 64 | #cooling-cells = <2>; /* min followed by max */ | |
| 45bfc2a3 | 65 | capacity-dmips-mhz = <1024>; |
| 4f0d20ec KK |
66 | }; |
| 67 | ||
| 68 | cpu3: cpu@3 { | |
| 69 | device_type = "cpu"; | |
| 70 | compatible = "arm,cortex-a15"; | |
| 71 | reg = <0x3>; | |
| 72 | clock-frequency = <1800000000>; | |
| 73 | cci-control-port = <&cci_control1>; | |
| 66a4a1fb | 74 | operating-points-v2 = <&cluster_a15_opp_table>; |
| 65ebf53f KK |
75 | cooling-min-level = <0>; |
| 76 | cooling-max-level = <11>; | |
| 77 | #cooling-cells = <2>; /* min followed by max */ | |
| 45bfc2a3 | 78 | capacity-dmips-mhz = <1024>; |
| 4f0d20ec KK |
79 | }; |
| 80 | ||
| 81 | cpu4: cpu@100 { | |
| 82 | device_type = "cpu"; | |
| 83 | compatible = "arm,cortex-a7"; | |
| 84 | reg = <0x100>; | |
| 66a4a1fb | 85 | clocks = <&clock CLK_KFC_CLK>; |
| 4f0d20ec KK |
86 | clock-frequency = <1000000000>; |
| 87 | cci-control-port = <&cci_control0>; | |
| 66a4a1fb | 88 | operating-points-v2 = <&cluster_a7_opp_table>; |
| 65ebf53f KK |
89 | cooling-min-level = <0>; |
| 90 | cooling-max-level = <7>; | |
| 91 | #cooling-cells = <2>; /* min followed by max */ | |
| 45bfc2a3 | 92 | capacity-dmips-mhz = <539>; |
| 4f0d20ec KK |
93 | }; |
| 94 | ||
| 95 | cpu5: cpu@101 { | |
| 96 | device_type = "cpu"; | |
| 97 | compatible = "arm,cortex-a7"; | |
| 98 | reg = <0x101>; | |
| 99 | clock-frequency = <1000000000>; | |
| 100 | cci-control-port = <&cci_control0>; | |
| 66a4a1fb | 101 | operating-points-v2 = <&cluster_a7_opp_table>; |
| 65ebf53f KK |
102 | cooling-min-level = <0>; |
| 103 | cooling-max-level = <7>; | |
| 104 | #cooling-cells = <2>; /* min followed by max */ | |
| 45bfc2a3 | 105 | capacity-dmips-mhz = <539>; |
| 4f0d20ec KK |
106 | }; |
| 107 | ||
| 108 | cpu6: cpu@102 { | |
| 109 | device_type = "cpu"; | |
| 110 | compatible = "arm,cortex-a7"; | |
| 111 | reg = <0x102>; | |
| 112 | clock-frequency = <1000000000>; | |
| 113 | cci-control-port = <&cci_control0>; | |
| 66a4a1fb | 114 | operating-points-v2 = <&cluster_a7_opp_table>; |
| 65ebf53f KK |
115 | cooling-min-level = <0>; |
| 116 | cooling-max-level = <7>; | |
| 117 | #cooling-cells = <2>; /* min followed by max */ | |
| 45bfc2a3 | 118 | capacity-dmips-mhz = <539>; |
| 4f0d20ec KK |
119 | }; |
| 120 | ||
| 121 | cpu7: cpu@103 { | |
| 122 | device_type = "cpu"; | |
| 123 | compatible = "arm,cortex-a7"; | |
| 124 | reg = <0x103>; | |
| 125 | clock-frequency = <1000000000>; | |
| 126 | cci-control-port = <&cci_control0>; | |
| 66a4a1fb | 127 | operating-points-v2 = <&cluster_a7_opp_table>; |
| 65ebf53f KK |
128 | cooling-min-level = <0>; |
| 129 | cooling-max-level = <7>; | |
| 130 | #cooling-cells = <2>; /* min followed by max */ | |
| 45bfc2a3 | 131 | capacity-dmips-mhz = <539>; |
| 4f0d20ec KK |
132 | }; |
| 133 | }; | |
| 134 | }; |