Commit | Line | Data |
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107e6aad TD |
1 | /* |
2 | * SAMSUNG EXYNOS5410 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. | |
8 | * EXYNOS5410 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
c9cf996d | 16 | #include "exynos54xx.dtsi" |
1462b137 | 17 | #include "exynos-syscon-restart.dtsi" |
107e6aad | 18 | #include <dt-bindings/clock/exynos5410.h> |
ad3b5ef7 | 19 | #include <dt-bindings/clock/exynos-audss-clk.h> |
e5995e6d | 20 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
107e6aad TD |
21 | |
22 | / { | |
23 | compatible = "samsung,exynos5410", "samsung,exynos5"; | |
24 | interrupt-parent = <&gic>; | |
25 | ||
1e64f48e | 26 | aliases { |
1eca825f HK |
27 | pinctrl0 = &pinctrl_0; |
28 | pinctrl1 = &pinctrl_1; | |
29 | pinctrl2 = &pinctrl_2; | |
30 | pinctrl3 = &pinctrl_3; | |
1e64f48e TF |
31 | }; |
32 | ||
107e6aad TD |
33 | cpus { |
34 | #address-cells = <1>; | |
35 | #size-cells = <0>; | |
36 | ||
c37ccce1 | 37 | cpu0: cpu@0 { |
107e6aad TD |
38 | device_type = "cpu"; |
39 | compatible = "arm,cortex-a15"; | |
40 | reg = <0x0>; | |
22298d6a | 41 | clock-frequency = <1600000000>; |
107e6aad TD |
42 | }; |
43 | ||
c37ccce1 | 44 | cpu1: cpu@1 { |
107e6aad TD |
45 | device_type = "cpu"; |
46 | compatible = "arm,cortex-a15"; | |
47 | reg = <0x1>; | |
22298d6a | 48 | clock-frequency = <1600000000>; |
107e6aad TD |
49 | }; |
50 | ||
c37ccce1 | 51 | cpu2: cpu@2 { |
107e6aad TD |
52 | device_type = "cpu"; |
53 | compatible = "arm,cortex-a15"; | |
54 | reg = <0x2>; | |
22298d6a | 55 | clock-frequency = <1600000000>; |
107e6aad TD |
56 | }; |
57 | ||
c37ccce1 | 58 | cpu3: cpu@3 { |
107e6aad TD |
59 | device_type = "cpu"; |
60 | compatible = "arm,cortex-a15"; | |
61 | reg = <0x3>; | |
22298d6a | 62 | clock-frequency = <1600000000>; |
107e6aad TD |
63 | }; |
64 | }; | |
65 | ||
66 | soc: soc { | |
67 | compatible = "simple-bus"; | |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | ranges; | |
71 | ||
0a8f5941 AF |
72 | pmu_system_controller: system-controller@10040000 { |
73 | compatible = "samsung,exynos5410-pmu", "syscon"; | |
74 | reg = <0x10040000 0x5000>; | |
2cbc0de1 KK |
75 | clock-names = "clkout16"; |
76 | clocks = <&fin_pll>; | |
77 | #clock-cells = <1>; | |
0a8f5941 AF |
78 | }; |
79 | ||
107e6aad TD |
80 | clock: clock-controller@10010000 { |
81 | compatible = "samsung,exynos5410-clock"; | |
82 | reg = <0x10010000 0x30000>; | |
83 | #clock-cells = <1>; | |
84 | }; | |
85 | ||
ad3b5ef7 SN |
86 | clock_audss: audss-clock-controller@3810000 { |
87 | compatible = "samsung,exynos5410-audss-clock"; | |
88 | reg = <0x03810000 0x0C>; | |
89 | #clock-cells = <1>; | |
90 | clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; | |
91 | clock-names = "pll_ref", "pll_in"; | |
92 | }; | |
93 | ||
c1a3b068 KK |
94 | tmu_cpu0: tmu@10060000 { |
95 | compatible = "samsung,exynos5420-tmu"; | |
96 | reg = <0x10060000 0x100>; | |
6abdf8d1 | 97 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
c1a3b068 KK |
98 | clocks = <&clock CLK_TMU>; |
99 | clock-names = "tmu_apbif"; | |
100 | #include "exynos4412-tmu-sensor-conf.dtsi" | |
101 | }; | |
102 | ||
103 | tmu_cpu1: tmu@10064000 { | |
104 | compatible = "samsung,exynos5420-tmu"; | |
105 | reg = <0x10064000 0x100>; | |
6abdf8d1 | 106 | interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; |
c1a3b068 KK |
107 | clocks = <&clock CLK_TMU>; |
108 | clock-names = "tmu_apbif"; | |
109 | #include "exynos4412-tmu-sensor-conf.dtsi" | |
110 | }; | |
111 | ||
112 | tmu_cpu2: tmu@10068000 { | |
113 | compatible = "samsung,exynos5420-tmu"; | |
114 | reg = <0x10068000 0x100>; | |
6abdf8d1 | 115 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
c1a3b068 KK |
116 | clocks = <&clock CLK_TMU>; |
117 | clock-names = "tmu_apbif"; | |
118 | #include "exynos4412-tmu-sensor-conf.dtsi" | |
119 | }; | |
120 | ||
121 | tmu_cpu3: tmu@1006c000 { | |
122 | compatible = "samsung,exynos5420-tmu"; | |
123 | reg = <0x1006c000 0x100>; | |
6abdf8d1 | 124 | interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; |
c1a3b068 KK |
125 | clocks = <&clock CLK_TMU>; |
126 | clock-names = "tmu_apbif"; | |
127 | #include "exynos4412-tmu-sensor-conf.dtsi" | |
128 | }; | |
129 | ||
107e6aad TD |
130 | mmc_0: mmc@12200000 { |
131 | compatible = "samsung,exynos5250-dw-mshc"; | |
132 | reg = <0x12200000 0x1000>; | |
888950b0 | 133 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
107e6aad TD |
134 | #address-cells = <1>; |
135 | #size-cells = <0>; | |
136 | clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; | |
137 | clock-names = "biu", "ciu"; | |
138 | fifo-depth = <0x80>; | |
139 | status = "disabled"; | |
140 | }; | |
141 | ||
142 | mmc_1: mmc@12210000 { | |
143 | compatible = "samsung,exynos5250-dw-mshc"; | |
144 | reg = <0x12210000 0x1000>; | |
888950b0 | 145 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
107e6aad TD |
146 | #address-cells = <1>; |
147 | #size-cells = <0>; | |
148 | clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; | |
149 | clock-names = "biu", "ciu"; | |
150 | fifo-depth = <0x80>; | |
151 | status = "disabled"; | |
152 | }; | |
153 | ||
154 | mmc_2: mmc@12220000 { | |
155 | compatible = "samsung,exynos5250-dw-mshc"; | |
156 | reg = <0x12220000 0x1000>; | |
888950b0 | 157 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
107e6aad TD |
158 | #address-cells = <1>; |
159 | #size-cells = <0>; | |
160 | clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; | |
161 | clock-names = "biu", "ciu"; | |
162 | fifo-depth = <0x80>; | |
163 | status = "disabled"; | |
164 | }; | |
165 | ||
1eca825f HK |
166 | pinctrl_0: pinctrl@13400000 { |
167 | compatible = "samsung,exynos5410-pinctrl"; | |
168 | reg = <0x13400000 0x1000>; | |
888950b0 | 169 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
1eca825f HK |
170 | |
171 | wakeup-interrupt-controller { | |
172 | compatible = "samsung,exynos4210-wakeup-eint"; | |
173 | interrupt-parent = <&gic>; | |
888950b0 | 174 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
1eca825f HK |
175 | }; |
176 | }; | |
177 | ||
178 | pinctrl_1: pinctrl@14000000 { | |
179 | compatible = "samsung,exynos5410-pinctrl"; | |
180 | reg = <0x14000000 0x1000>; | |
888950b0 | 181 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
1eca825f HK |
182 | }; |
183 | ||
184 | pinctrl_2: pinctrl@10d10000 { | |
185 | compatible = "samsung,exynos5410-pinctrl"; | |
186 | reg = <0x10d10000 0x1000>; | |
888950b0 | 187 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
1eca825f HK |
188 | }; |
189 | ||
190 | pinctrl_3: pinctrl@03860000 { | |
191 | compatible = "samsung,exynos5410-pinctrl"; | |
192 | reg = <0x03860000 0x1000>; | |
888950b0 | 193 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
1eca825f | 194 | }; |
ad3b5ef7 SN |
195 | |
196 | amba { | |
197 | #address-cells = <1>; | |
198 | #size-cells = <1>; | |
199 | compatible = "simple-bus"; | |
200 | interrupt-parent = <&gic>; | |
201 | ranges; | |
202 | ||
203 | pdma0: pdma@12680000 { | |
204 | compatible = "arm,pl330", "arm,primecell"; | |
205 | reg = <0x121A0000 0x1000>; | |
8e35c48e | 206 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
ad3b5ef7 SN |
207 | clocks = <&clock CLK_PDMA0>; |
208 | clock-names = "apb_pclk"; | |
209 | #dma-cells = <1>; | |
210 | #dma-channels = <8>; | |
211 | #dma-requests = <32>; | |
212 | }; | |
213 | ||
214 | pdma1: pdma@12690000 { | |
215 | compatible = "arm,pl330", "arm,primecell"; | |
216 | reg = <0x121B0000 0x1000>; | |
8e35c48e | 217 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
ad3b5ef7 SN |
218 | clocks = <&clock CLK_PDMA1>; |
219 | clock-names = "apb_pclk"; | |
220 | #dma-cells = <1>; | |
221 | #dma-channels = <8>; | |
222 | #dma-requests = <32>; | |
223 | }; | |
224 | }; | |
225 | ||
226 | audi2s0: i2s@03830000 { | |
227 | compatible = "samsung,exynos5420-i2s"; | |
228 | reg = <0x03830000 0x100>; | |
229 | dmas = <&pdma0 10 | |
230 | &pdma0 9 | |
231 | &pdma0 8>; | |
232 | dma-names = "tx", "rx", "tx-sec"; | |
233 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
234 | <&clock_audss EXYNOS_I2S_BUS>, | |
235 | <&clock_audss EXYNOS_SCLK_I2S>; | |
236 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
237 | #clock-cells = <1>; | |
238 | clock-output-names = "i2s_cdclk0"; | |
239 | #sound-dai-cells = <1>; | |
240 | samsung,idma-addr = <0x03000000>; | |
241 | pinctrl-names = "default"; | |
242 | pinctrl-0 = <&audi2s0_bus>; | |
243 | status = "disabled"; | |
244 | }; | |
88ad58ba | 245 | }; |
c1a3b068 KK |
246 | |
247 | thermal-zones { | |
248 | cpu0_thermal: cpu0-thermal { | |
249 | thermal-sensors = <&tmu_cpu0>; | |
250 | #include "exynos5420-trip-points.dtsi" | |
251 | }; | |
252 | cpu1_thermal: cpu1-thermal { | |
253 | thermal-sensors = <&tmu_cpu1>; | |
254 | #include "exynos5420-trip-points.dtsi" | |
255 | }; | |
256 | cpu2_thermal: cpu2-thermal { | |
257 | thermal-sensors = <&tmu_cpu2>; | |
258 | #include "exynos5420-trip-points.dtsi" | |
259 | }; | |
260 | cpu3_thermal: cpu3-thermal { | |
261 | thermal-sensors = <&tmu_cpu3>; | |
262 | #include "exynos5420-trip-points.dtsi" | |
263 | }; | |
264 | }; | |
88ad58ba | 265 | }; |
1eca825f | 266 | |
e1e146b1 KK |
267 | &i2c_0 { |
268 | clocks = <&clock CLK_I2C0>; | |
269 | clock-names = "i2c"; | |
270 | pinctrl-names = "default"; | |
271 | pinctrl-0 = <&i2c0_bus>; | |
272 | }; | |
273 | ||
274 | &i2c_1 { | |
275 | clocks = <&clock CLK_I2C1>; | |
276 | clock-names = "i2c"; | |
277 | pinctrl-names = "default"; | |
278 | pinctrl-0 = <&i2c1_bus>; | |
279 | }; | |
280 | ||
281 | &i2c_2 { | |
282 | clocks = <&clock CLK_I2C2>; | |
283 | clock-names = "i2c"; | |
284 | pinctrl-names = "default"; | |
285 | pinctrl-0 = <&i2c2_bus>; | |
286 | }; | |
287 | ||
288 | &i2c_3 { | |
289 | clocks = <&clock CLK_I2C3>; | |
290 | clock-names = "i2c"; | |
291 | pinctrl-names = "default"; | |
292 | pinctrl-0 = <&i2c3_bus>; | |
293 | }; | |
294 | ||
295 | &hsi2c_4 { | |
296 | clocks = <&clock CLK_USI0>; | |
297 | clock-names = "hsi2c"; | |
298 | pinctrl-names = "default"; | |
299 | pinctrl-0 = <&i2c4_hs_bus>; | |
300 | }; | |
301 | ||
302 | &hsi2c_5 { | |
303 | clocks = <&clock CLK_USI1>; | |
304 | clock-names = "hsi2c"; | |
305 | pinctrl-names = "default"; | |
306 | pinctrl-0 = <&i2c5_hs_bus>; | |
307 | }; | |
308 | ||
309 | &hsi2c_6 { | |
310 | clocks = <&clock CLK_USI2>; | |
311 | clock-names = "hsi2c"; | |
312 | pinctrl-names = "default"; | |
313 | pinctrl-0 = <&i2c6_hs_bus>; | |
314 | }; | |
315 | ||
316 | &hsi2c_7 { | |
317 | clocks = <&clock CLK_USI3>; | |
318 | clock-names = "hsi2c"; | |
319 | pinctrl-names = "default"; | |
320 | pinctrl-0 = <&i2c7_hs_bus>; | |
321 | }; | |
322 | ||
c9cf996d KK |
323 | &mct { |
324 | clocks = <&fin_pll>, <&clock CLK_MCT>; | |
325 | clock-names = "fin_pll", "mct"; | |
326 | }; | |
327 | ||
88ad58ba KK |
328 | &pwm { |
329 | clocks = <&clock CLK_PWM>; | |
330 | clock-names = "timers"; | |
331 | }; | |
107e6aad | 332 | |
e1e146b1 KK |
333 | &rtc { |
334 | clocks = <&clock CLK_RTC>; | |
335 | clock-names = "rtc"; | |
336 | interrupt-parent = <&pmu_system_controller>; | |
337 | status = "disabled"; | |
338 | }; | |
339 | ||
88ad58ba KK |
340 | &serial_0 { |
341 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | |
342 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
343 | dmas = <&pdma0 13>, <&pdma0 14>; |
344 | dma-names = "rx", "tx"; | |
88ad58ba | 345 | }; |
107e6aad | 346 | |
88ad58ba KK |
347 | &serial_1 { |
348 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | |
349 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
350 | dmas = <&pdma1 15>, <&pdma1 16>; |
351 | dma-names = "rx", "tx"; | |
88ad58ba KK |
352 | }; |
353 | ||
354 | &serial_2 { | |
355 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | |
356 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
357 | dmas = <&pdma0 15>, <&pdma0 16>; |
358 | dma-names = "rx", "tx"; | |
88ad58ba KK |
359 | }; |
360 | ||
361 | &serial_3 { | |
594127ad KK |
362 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
363 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
364 | dmas = <&pdma1 17>, <&pdma1 18>; |
365 | dma-names = "rx", "tx"; | |
88ad58ba KK |
366 | }; |
367 | ||
b8bd7e23 KK |
368 | &sss { |
369 | clocks = <&clock CLK_SSS>; | |
370 | clock-names = "secss"; | |
371 | }; | |
372 | ||
88ad58ba KK |
373 | &sromc { |
374 | #address-cells = <2>; | |
375 | #size-cells = <1>; | |
376 | ranges = <0 0 0x04000000 0x20000 | |
377 | 1 0 0x05000000 0x20000 | |
378 | 2 0 0x06000000 0x20000 | |
379 | 3 0 0x07000000 0x20000>; | |
107e6aad | 380 | }; |
1eca825f | 381 | |
cb089656 KK |
382 | &usbdrd3_0 { |
383 | clocks = <&clock CLK_USBD300>; | |
384 | clock-names = "usbdrd30"; | |
385 | }; | |
386 | ||
387 | &usbdrd_phy0 { | |
388 | clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; | |
389 | clock-names = "phy", "ref"; | |
390 | samsung,pmu-syscon = <&pmu_system_controller>; | |
391 | }; | |
392 | ||
393 | &usbdrd3_1 { | |
394 | clocks = <&clock CLK_USBD301>; | |
395 | clock-names = "usbdrd30"; | |
396 | }; | |
397 | ||
e5995e6d | 398 | &usbdrd_dwc3_1 { |
6abdf8d1 | 399 | interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; |
e5995e6d KK |
400 | }; |
401 | ||
cb089656 KK |
402 | &usbdrd_phy1 { |
403 | clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; | |
404 | clock-names = "phy", "ref"; | |
405 | samsung,pmu-syscon = <&pmu_system_controller>; | |
406 | }; | |
407 | ||
408 | &usbhost1 { | |
409 | clocks = <&clock CLK_USBH20>; | |
410 | clock-names = "usbhost"; | |
411 | }; | |
412 | ||
413 | &usbhost2 { | |
414 | clocks = <&clock CLK_USBH20>; | |
415 | clock-names = "usbhost"; | |
416 | }; | |
417 | ||
418 | &usb2_phy { | |
419 | clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; | |
420 | clock-names = "phy", "ref"; | |
421 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
422 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
423 | }; | |
424 | ||
b8bd7e23 KK |
425 | &watchdog { |
426 | clocks = <&clock CLK_WDT>; | |
427 | clock-names = "watchdog"; | |
428 | samsung,syscon-phandle = <&pmu_system_controller>; | |
429 | }; | |
430 | ||
1eca825f | 431 | #include "exynos5410-pinctrl.dtsi" |