[linux-2.6-block.git] / arch / arm / boot / dts / exynos4210.dtsi

/*
 * Samsung's Exynos4210 SoC device tree source
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2010-2011 Linaro Ltd.
 *		www.linaro.org
 *
 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include "exynos4.dtsi"
#include "exynos4210-pinctrl.dtsi"

/ {
	compatible = "samsung,exynos4210", "samsung,exynos4";

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
	};

	sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x20000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@1f000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x1f000 0x1000>;
		};
	};

	pd_lcd1: lcd1-power-domain@10023CA0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023CA0 0x20>;
	};

	gic: interrupt-controller@10490000 {
		cpu-offset = <0x8000>;
	};

	combiner: interrupt-controller@10440000 {
		samsung,combiner-nr = <16>;
		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
	};

	mct@10050000 {
		compatible = "samsung,exynos4210-mct";
		reg = <0x10050000 0x800>;
		interrupt-parent = <&mct_map>;
		interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
		clock-names = "fin_pll", "mct";

		mct_map: mct-map {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &gic 0 57 0>,
					<1 &gic 0 69 0>,
					<2 &combiner 12 6>,
					<3 &combiner 12 7>,
					<4 &gic 0 42 0>,
					<5 &gic 0 48 0>;
		};
	};

	clock: clock-controller@10030000 {
		compatible = "samsung,exynos4210-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&combiner>;
		interrupts = <2 2>, <3 2>;
	};

	pinctrl_0: pinctrl@11400000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x11400000 0x1000>;
		interrupts = <0 47 0>;
	};

	pinctrl_1: pinctrl@11000000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x11000000 0x1000>;
		interrupts = <0 46 0>;

		wakup_eint: wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <0 32 0>;
		};
	};

	pinctrl_2: pinctrl@03860000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x03860000 0x1000>;
	};

	tmu@100C0000 {
		compatible = "samsung,exynos4210-tmu";
		interrupt-parent = <&combiner>;
		reg = <0x100C0000 0x100>;
		interrupts = <2 4>;
		clocks = <&clock CLK_TMU_APBIF>;
		clock-names = "tmu_apbif";
		status = "disabled";
	};

	g2d@12800000 {
		compatible = "samsung,s5pv210-g2d";
		reg = <0x12800000 0x1000>;
		interrupts = <0 89 0>;
		clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
		clock-names = "sclk_fimg2d", "fimg2d";
		status = "disabled";
	};

	camera {
		clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
			 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";

		fimc_0: fimc@11800000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,cam-if;
		};

		fimc_1: fimc@11810000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,cam-if;
		};

		fimc_2: fimc@11820000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,lcd-wb;
		};

		fimc_3: fimc@11830000 {
			samsung,pix-limits = <1920 8192 1366 1920>;
			samsung,rotators = <0>;
			samsung,mainscaler-ext;
			samsung,lcd-wb;
		};
	};
};
Commit	Line	Data
0561ceab TA	1	/*
	2	* Samsung's Exynos4210 SoC device tree source
	3	*
	4	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	* Copyright (c) 2010-2011 Linaro Ltd.
	7	* www.linaro.org
	8	*
	9	* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
	10	* based board files can include this file and provide values for board specfic
	11	* bindings.
	12	*
	13	* Note: This file does not include device nodes for all the controllers in
	14	* Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
	15	* nodes can be added to this file.
	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License version 2 as
	19	* published by the Free Software Foundation.
	20	*/
	21
3799279f PV	22	#include "exynos4.dtsi"
3799279f PV	23	#include "exynos4210-pinctrl.dtsi"
0561ceab TA	24
0561ceab TA	25	/ {
8bdb31b4	26	compatible = "samsung,exynos4210", "samsung,exynos4";
0561ceab	27
4980c39b	28	aliases {
87711d8c TA	29	pinctrl0 = &pinctrl_0;
	30	pinctrl1 = &pinctrl_1;
	31	pinctrl2 = &pinctrl_2;
4980c39b TA	32	};
4980c39b TA	33
b3205dea SK	34	sysram@02020000 {
	35	compatible = "mmio-sram";
	36	reg = <0x02020000 0x20000>;
	37	#address-cells = <1>;
	38	#size-cells = <1>;
	39	ranges = <0 0x02020000 0x20000>;
	40
	41	smp-sysram@0 {
	42	compatible = "samsung,exynos4210-sysram";
	43	reg = <0x0 0x1000>;
	44	};
	45
	46	smp-sysram@1f000 {
	47	compatible = "samsung,exynos4210-sysram-ns";
	48	reg = <0x1f000 0x1000>;
	49	};
	50	};
	51
91d88f03 TF	52	pd_lcd1: lcd1-power-domain@10023CA0 {
	53	compatible = "samsung,exynos4210-pd";
	54	reg = <0x10023CA0 0x20>;
	55	};
	56
0572b725	57	gic: interrupt-controller@10490000 {
da911782	58	cpu-offset = <0x8000>;
0561ceab TA	59	};
0561ceab TA	60
0572b725	61	combiner: interrupt-controller@10440000 {
30269ddf	62	samsung,combiner-nr = <16>;
4922972e TA	63	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
	64	<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
	65	<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
	66	<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
	67	};
	68
bbd9700a TA	69	mct@10050000 {
	70	compatible = "samsung,exynos4210-mct";
	71	reg = <0x10050000 0x800>;
bbd9700a	72	interrupt-parent = <&mct_map>;
84ee1c15	73	interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
1c75a78a	74	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
7ad34337	75	clock-names = "fin_pll", "mct";
bbd9700a TA	76
bbd9700a TA	77	mct_map: mct-map {
84ee1c15	78	#interrupt-cells = <1>;
bbd9700a TA	79	#address-cells = <0>;
bbd9700a TA	80	#size-cells = <0>;
84ee1c15 TF	81	interrupt-map = <0 &gic 0 57 0>,
	82	<1 &gic 0 69 0>,
	83	<2 &combiner 12 6>,
	84	<3 &combiner 12 7>,
	85	<4 &gic 0 42 0>,
	86	<5 &gic 0 48 0>;
bbd9700a TA	87	};
	88	};
	89
e7787aed	90	clock: clock-controller@10030000 {
d8bafc87 TA	91	compatible = "samsung,exynos4210-clock";
	92	reg = <0x10030000 0x20000>;
	93	#clock-cells = <1>;
	94	};
	95
db35234e CP	96	pmu {
	97	compatible = "arm,cortex-a9-pmu";
	98	interrupt-parent = <&combiner>;
	99	interrupts = <2 2>, <3 2>;
	100	};
	101
87711d8c	102	pinctrl_0: pinctrl@11400000 {
b533c868	103	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	104	reg = <0x11400000 0x1000>;
87711d8c TA	105	interrupts = <0 47 0>;
87711d8c TA	106	};
	107
	108	pinctrl_1: pinctrl@11000000 {
b533c868	109	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	110	reg = <0x11000000 0x1000>;
87711d8c TA	111	interrupts = <0 46 0>;
87711d8c TA	112
	113	wakup_eint: wakeup-interrupt-controller {
	114	compatible = "samsung,exynos4210-wakeup-eint";
	115	interrupt-parent = <&gic>;
a04b07c0	116	interrupts = <0 32 0>;
87711d8c TA	117	};
	118	};
	119
	120	pinctrl_2: pinctrl@03860000 {
b533c868	121	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	122	reg = <0x03860000 0x1000>;
	123	};
	124
8d4155db ADK	125	tmu@100C0000 {
	126	compatible = "samsung,exynos4210-tmu";
	127	interrupt-parent = <&combiner>;
	128	reg = <0x100C0000 0x100>;
	129	interrupts = <2 4>;
1c75a78a	130	clocks = <&clock CLK_TMU_APBIF>;
e6199af6 SK	131	clock-names = "tmu_apbif";
e6199af6 SK	132	status = "disabled";
8d4155db	133	};
66d302ac SK	134
	135	g2d@12800000 {
	136	compatible = "samsung,s5pv210-g2d";
	137	reg = <0x12800000 0x1000>;
	138	interrupts = <0 89 0>;
1c75a78a	139	clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
37bf5796	140	clock-names = "sclk_fimg2d", "fimg2d";
66d302ac SK	141	status = "disabled";
66d302ac SK	142	};
54a8896a SN	143
54a8896a SN	144	camera {
1c75a78a AH	145	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
1c75a78a AH	146	<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
54a8896a SN	147	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
	148
	149	fimc_0: fimc@11800000 {
	150	samsung,pix-limits = <4224 8192 1920 4224>;
	151	samsung,mainscaler-ext;
	152	samsung,cam-if;
	153	};
	154
	155	fimc_1: fimc@11810000 {
	156	samsung,pix-limits = <4224 8192 1920 4224>;
	157	samsung,mainscaler-ext;
	158	samsung,cam-if;
	159	};
	160
	161	fimc_2: fimc@11820000 {
	162	samsung,pix-limits = <4224 8192 1920 4224>;
	163	samsung,mainscaler-ext;
	164	samsung,lcd-wb;
	165	};
	166
	167	fimc_3: fimc@11830000 {
	168	samsung,pix-limits = <1920 8192 1366 1920>;
	169	samsung,rotators = <0>;
	170	samsung,mainscaler-ext;
	171	samsung,lcd-wb;
	172	};
	173	};
0561ceab	174	};