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ARM: dts: exynos: use lowercase hex addresses
[linux-2.6-block.git] / arch / arm / boot / dts / exynos4.dtsi
CommitLineData
cc4637f7 1// SPDX-License-Identifier: GPL-2.0
b571abb3
TF		 2/*
3 * Samsung's Exynos4 SoC series common device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
11 * SoCs from Exynos4 series can include this file and provide values for SoCs
12 * specfic bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
16 * nodes can be added to this file.
b571abb3
TF		 17 */
18
1c75a78a 19#include <dt-bindings/clock/exynos4.h>
990a7bfd 20#include <dt-bindings/clock/exynos-audss-clk.h>
74e2c958 21#include <dt-bindings/interrupt-controller/arm-gic.h>
63aee4fa 22#include <dt-bindings/interrupt-controller/irq.h>
b571abb3
TF		 23
24/ {
25 interrupt-parent = <&gic>;
1354835a
JMC		 26 #address-cells = <1>;
27 #size-cells = <1>;
b571abb3
TF		 28
29 aliases {
30 spi0 = &spi_0;
31 spi1 = &spi_1;
32 spi2 = &spi_2;
34db4990
DA		 33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
ed80d4ca 41 i2c8 = &i2c_8;
d1b8a41d
SN		 42 csis0 = &csis_0;
43 csis1 = &csis_1;
44 fimc0 = &fimc_0;
45 fimc1 = &fimc_1;
46 fimc2 = &fimc_2;
47 fimc3 = &fimc_3;
1e64f48e
TF		 48 serial0 = &serial_0;
49 serial1 = &serial_1;
50 serial2 = &serial_2;
51 serial3 = &serial_3;
b571abb3
TF		 52 };
53
be003001
KK		 54 pmu: pmu {
55 compatible = "arm,cortex-a9-pmu";
56 interrupt-parent = <&combiner>;
6da4e11c 57 status = "disabled";
be003001
KK		 58 };
59
73a901d0
MP		 60 soc: soc {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
990a7bfd 65
73a901d0
MP		 66 clock_audss: clock-controller@3810000 {
67 compatible = "samsung,exynos4210-audss-clock";
9ca5a7ce 68 reg = <0x03810000 0x0c>;
73a901d0
MP		 69 #clock-cells = <1>;
70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
71 <&clock CLK_SCLK_AUDIO0>,
72 <&clock CLK_SCLK_AUDIO0>;
73 clock-names = "pll_ref", "pll_in", "sclk_audio",
74 "sclk_pcm_in";
75 };
096ee6ad 76
73a901d0
MP		 77 i2s0: i2s@3830000 {
78 compatible = "samsung,s5pv210-i2s";
79 reg = <0x03830000 0x100>;
80 clocks = <&clock_audss EXYNOS_I2S_BUS>,
81 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
82 <&clock_audss EXYNOS_SCLK_I2S>;
83 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
84 #clock-cells = <1>;
85 clock-output-names = "i2s_cdclk0";
86 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
87 dma-names = "tx", "rx", "tx-sec";
88 samsung,idma-addr = <0x03000000>;
89 #sound-dai-cells = <1>;
90 status = "disabled";
91 };
05a3589f 92
73a901d0
MP		 93 chipid@10000000 {
94 compatible = "samsung,exynos4210-chipid";
95 reg = <0x10000000 0x100>;
96 };
df4400ac 97
73a901d0
MP		 98 scu: snoop-control-unit@10500000 {
99 compatible = "arm,cortex-a9-scu";
100 reg = <0x10500000 0x2000>;
101 };
21b190d2 102
73a901d0
MP		 103 memory-controller@12570000 {
104 compatible = "samsung,exynos4210-srom";
105 reg = <0x12570000 0x14>;
106 };
91d88f03 107
73a901d0
MP		 108 mipi_phy: video-phy {
109 compatible = "samsung,s5pv210-mipi-video-phy";
110 #phy-cells = <1>;
111 syscon = <&pmu_system_controller>;
112 };
91d88f03 113
e39fc20f 114 pd_mfc: power-domain@10023c40 {
73a901d0 115 compatible = "samsung,exynos4210-pd";
9ca5a7ce 116 reg = <0x10023c40 0x20>;
73a901d0
MP		 117 #power-domain-cells = <0>;
118 label = "MFC";
119 };
91d88f03 120
e39fc20f 121 pd_g3d: power-domain@10023c60 {
73a901d0 122 compatible = "samsung,exynos4210-pd";
9ca5a7ce 123 reg = <0x10023c60 0x20>;
73a901d0
MP		 124 #power-domain-cells = <0>;
125 label = "G3D";
126 };
91d88f03 127
e39fc20f 128 pd_lcd0: power-domain@10023c80 {
73a901d0 129 compatible = "samsung,exynos4210-pd";
9ca5a7ce 130 reg = <0x10023c80 0x20>;
73a901d0
MP		 131 #power-domain-cells = <0>;
132 label = "LCD0";
133 };
91d88f03 134
e39fc20f 135 pd_tv: power-domain@10023c20 {
73a901d0 136 compatible = "samsung,exynos4210-pd";
9ca5a7ce 137 reg = <0x10023c20 0x20>;
73a901d0
MP		 138 #power-domain-cells = <0>;
139 power-domains = <&pd_lcd0>;
140 label = "TV";
141 };
b571abb3 142
e39fc20f 143 pd_cam: power-domain@10023c00 {
73a901d0 144 compatible = "samsung,exynos4210-pd";
9ca5a7ce 145 reg = <0x10023c00 0x20>;
73a901d0
MP		 146 #power-domain-cells = <0>;
147 label = "CAM";
148 };
10ea1f18 149
e39fc20f 150 pd_gps: power-domain@10023ce0 {
73a901d0 151 compatible = "samsung,exynos4210-pd";
9ca5a7ce 152 reg = <0x10023ce0 0x20>;
73a901d0
MP		 153 #power-domain-cells = <0>;
154 label = "GPS";
155 };
b571abb3 156
e39fc20f 157 pd_gps_alive: power-domain@10023d00 {
73a901d0 158 compatible = "samsung,exynos4210-pd";
9ca5a7ce 159 reg = <0x10023d00 0x20>;
73a901d0
MP		 160 #power-domain-cells = <0>;
161 label = "GPS alive";
162 };
b571abb3 163
73a901d0
MP		 164 gic: interrupt-controller@10490000 {
165 compatible = "arm,cortex-a9-gic";
166 #interrupt-cells = <3>;
167 interrupt-controller;
168 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
169 };
6f4b82a3 170
73a901d0
MP		 171 combiner: interrupt-controller@10440000 {
172 compatible = "samsung,exynos4210-combiner";
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 reg = <0x10440000 0x1000>;
176 };
a64b1b22 177
73a901d0
MP		 178 sys_reg: syscon@10010000 {
179 compatible = "samsung,exynos4-sysreg", "syscon";
180 reg = <0x10010000 0x400>;
181 };
8b7dd64c 182
73a901d0
MP		 183 pmu_system_controller: system-controller@10020000 {
184 compatible = "samsung,exynos4210-pmu", "syscon";
185 reg = <0x10020000 0x4000>;
186 interrupt-controller;
187 #interrupt-cells = <3>;
188 interrupt-parent = <&gic>;
189 };
d1b8a41d 190
73a901d0
MP		 191 dsi_0: dsi@11c80000 {
192 compatible = "samsung,exynos4210-mipi-dsi";
9ca5a7ce 193 reg = <0x11c80000 0x10000>;
73a901d0
MP		 194 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
195 power-domains = <&pd_lcd0>;
196 phys = <&mipi_phy 1>;
197 phy-names = "dsim";
198 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
199 clock-names = "bus_clk", "sclk_mipi";
d1b8a41d 200 status = "disabled";
73a901d0
MP		 201 #address-cells = <1>;
202 #size-cells = <0>;
d1b8a41d
SN		 203 };
204
73a901d0
MP		 205 camera: camera {
206 compatible = "samsung,fimc", "simple-bus";
d1b8a41d 207 status = "disabled";
73a901d0
MP		 208 #address-cells = <1>;
209 #size-cells = <1>;
210 #clock-cells = <1>;
211 clock-output-names = "cam_a_clkout", "cam_b_clkout";
212 ranges;
213
214 fimc_0: fimc@11800000 {
215 compatible = "samsung,exynos4210-fimc";
216 reg = <0x11800000 0x1000>;
217 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clock CLK_FIMC0>,
219 <&clock CLK_SCLK_FIMC0>;
220 clock-names = "fimc", "sclk_fimc";
221 power-domains = <&pd_cam>;
222 samsung,sysreg = <&sys_reg>;
223 iommus = <&sysmmu_fimc0>;
224 status = "disabled";
225 };
226
227 fimc_1: fimc@11810000 {
228 compatible = "samsung,exynos4210-fimc";
229 reg = <0x11810000 0x1000>;
230 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clock CLK_FIMC1>,
232 <&clock CLK_SCLK_FIMC1>;
233 clock-names = "fimc", "sclk_fimc";
234 power-domains = <&pd_cam>;
235 samsung,sysreg = <&sys_reg>;
236 iommus = <&sysmmu_fimc1>;
237 status = "disabled";
238 };
239
240 fimc_2: fimc@11820000 {
241 compatible = "samsung,exynos4210-fimc";
242 reg = <0x11820000 0x1000>;
243 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clock CLK_FIMC2>,
245 <&clock CLK_SCLK_FIMC2>;
246 clock-names = "fimc", "sclk_fimc";
247 power-domains = <&pd_cam>;
248 samsung,sysreg = <&sys_reg>;
249 iommus = <&sysmmu_fimc2>;
250 status = "disabled";
251 };
252
253 fimc_3: fimc@11830000 {
254 compatible = "samsung,exynos4210-fimc";
255 reg = <0x11830000 0x1000>;
256 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clock CLK_FIMC3>,
258 <&clock CLK_SCLK_FIMC3>;
259 clock-names = "fimc", "sclk_fimc";
260 power-domains = <&pd_cam>;
261 samsung,sysreg = <&sys_reg>;
262 iommus = <&sysmmu_fimc3>;
263 status = "disabled";
264 };
265
266 csis_0: csis@11880000 {
267 compatible = "samsung,exynos4210-csis";
268 reg = <0x11880000 0x4000>;
269 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clock CLK_CSIS0>,
271 <&clock CLK_SCLK_CSIS0>;
272 clock-names = "csis", "sclk_csis";
273 bus-width = <4>;
274 power-domains = <&pd_cam>;
275 phys = <&mipi_phy 0>;
276 phy-names = "csis";
277 status = "disabled";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 };
281
282 csis_1: csis@11890000 {
283 compatible = "samsung,exynos4210-csis";
284 reg = <0x11890000 0x4000>;
285 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clock CLK_CSIS1>,
287 <&clock CLK_SCLK_CSIS1>;
288 clock-names = "csis", "sclk_csis";
289 bus-width = <2>;
290 power-domains = <&pd_cam>;
291 phys = <&mipi_phy 2>;
292 phy-names = "csis";
293 status = "disabled";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 };
d1b8a41d
SN		 297 };
298
73a901d0
MP		 299 rtc: rtc@10070000 {
300 compatible = "samsung,s3c6410-rtc";
301 reg = <0x10070000 0x100>;
302 interrupt-parent = <&pmu_system_controller>;
303 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clock CLK_RTC>;
306 clock-names = "rtc";
d1b8a41d
SN		 307 status = "disabled";
308 };
309
73a901d0
MP		 310 keypad: keypad@100a0000 {
311 compatible = "samsung,s5pv210-keypad";
9ca5a7ce 312 reg = <0x100a0000 0x100>;
73a901d0
MP		 313 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clock CLK_KEYIF>;
315 clock-names = "keypad";
d1b8a41d
SN		 316 status = "disabled";
317 };
318
c805b77c 319 sdhci_0: mmc@12510000 {
73a901d0
MP		 320 compatible = "samsung,exynos4210-sdhci";
321 reg = <0x12510000 0x100>;
322 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
324 clock-names = "hsmmc", "mmc_busclk.2";
d1b8a41d 325 status = "disabled";
d1b8a41d
SN		 326 };
327
c805b77c 328 sdhci_1: mmc@12520000 {
73a901d0
MP		 329 compatible = "samsung,exynos4210-sdhci";
330 reg = <0x12520000 0x100>;
331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
333 clock-names = "hsmmc", "mmc_busclk.2";
d1b8a41d 334 status = "disabled";
d1b8a41d 335 };
b571abb3 336
c805b77c 337 sdhci_2: mmc@12530000 {
73a901d0
MP		 338 compatible = "samsung,exynos4210-sdhci";
339 reg = <0x12530000 0x100>;
340 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
342 clock-names = "hsmmc", "mmc_busclk.2";
343 status = "disabled";
344 };
26bbd41f 345
c805b77c 346 sdhci_3: mmc@12540000 {
73a901d0
MP		 347 compatible = "samsung,exynos4210-sdhci";
348 reg = <0x12540000 0x100>;
349 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
351 clock-names = "hsmmc", "mmc_busclk.2";
352 status = "disabled";
353 };
ef14d94c 354
7bac2cd7 355 exynos_usbphy: usb-phy@125b0000 {
73a901d0 356 compatible = "samsung,exynos4210-usb2-phy";
9ca5a7ce 357 reg = <0x125b0000 0x100>;
73a901d0
MP		 358 samsung,pmureg-phandle = <&pmu_system_controller>;
359 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
360 clock-names = "phy", "ref";
361 #phy-cells = <1>;
362 status = "disabled";
363 };
b571abb3 364
177c86fa 365 hsotg: usb@12480000 {
73a901d0
MP		 366 compatible = "samsung,s3c6400-hsotg";
367 reg = <0x12480000 0x20000>;
368 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clock CLK_USB_DEVICE>;
370 clock-names = "otg";
371 phys = <&exynos_usbphy 0>;
372 phy-names = "usb2-phy";
dfaf06ba 373 status = "disabled";
366126d5 374 };
73a901d0 375
b412be7d 376 ehci: usb@12580000 {
73a901d0
MP		 377 compatible = "samsung,exynos4210-ehci";
378 reg = <0x12580000 0x100>;
379 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clock CLK_USB_HOST>;
381 clock-names = "usbhost";
dfaf06ba 382 status = "disabled";
314de2f6
MS		 383 phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>;
384 phy-names = "host", "hsic0", "hsic1";
366126d5 385 };
73a901d0 386
b412be7d 387 ohci: usb@12590000 {
73a901d0
MP		 388 compatible = "samsung,exynos4210-ohci";
389 reg = <0x12590000 0x100>;
390 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clock CLK_USB_HOST>;
392 clock-names = "usbhost";
dfaf06ba 393 status = "disabled";
314de2f6
MS		 394 phys = <&exynos_usbphy 1>;
395 phy-names = "host";
366126d5 396 };
6f9d02a0 397
8386e6a7
MS		 398 gpu: gpu@13000000 {
399 compatible = "samsung,exynos4210-mali", "arm,mali-400";
400 reg = <0x13000000 0x10000>;
401 /*
402 * CLK_G3D is not actually bus clock but a IP-level clock.
403 * The bus clock is not described in hardware manual.
404 */
405 clocks = <&clock CLK_G3D>,
406 <&clock CLK_SCLK_G3D>;
407 clock-names = "bus", "core";
408 power-domains = <&pd_g3d>;
409 status = "disabled";
410 };
411
73a901d0
MP		 412 i2s1: i2s@13960000 {
413 compatible = "samsung,s3c6410-i2s";
414 reg = <0x13960000 0x100>;
415 clocks = <&clock CLK_I2S1>;
416 clock-names = "iis";
417 #clock-cells = <1>;
418 clock-output-names = "i2s_cdclk1";
419 dmas = <&pdma1 12>, <&pdma1 11>;
420 dma-names = "tx", "rx";
421 #sound-dai-cells = <1>;
dfaf06ba 422 status = "disabled";
366126d5 423 };
6f9d02a0 424
73a901d0
MP		 425 i2s2: i2s@13970000 {
426 compatible = "samsung,s3c6410-i2s";
427 reg = <0x13970000 0x100>;
428 clocks = <&clock CLK_I2S2>;
429 clock-names = "iis";
430 #clock-cells = <1>;
431 clock-output-names = "i2s_cdclk2";
432 dmas = <&pdma0 14>, <&pdma0 13>;
433 dma-names = "tx", "rx";
434 #sound-dai-cells = <1>;
435 status = "disabled";
436 };
990a7bfd 437
73a901d0
MP		 438 mfc: codec@13400000 {
439 compatible = "samsung,mfc-v5";
440 reg = <0x13400000 0x10000>;
441 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
442 power-domains = <&pd_mfc>;
443 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
444 clock-names = "mfc", "sclk_mfc";
445 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
446 iommu-names = "left", "right";
447 };
990a7bfd 448
73a901d0
MP		 449 serial_0: serial@13800000 {
450 compatible = "samsung,exynos4210-uart";
451 reg = <0x13800000 0x100>;
452 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
454 clock-names = "uart", "clk_uart_baud0";
455 dmas = <&pdma0 15>, <&pdma0 16>;
456 dma-names = "rx", "tx";
457 status = "disabled";
458 };
20901f74 459
73a901d0
MP		 460 serial_1: serial@13810000 {
461 compatible = "samsung,exynos4210-uart";
462 reg = <0x13810000 0x100>;
463 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
465 clock-names = "uart", "clk_uart_baud0";
466 dmas = <&pdma1 15>, <&pdma1 16>;
467 dma-names = "rx", "tx";
468 status = "disabled";
469 };
b571abb3 470
73a901d0
MP		 471 serial_2: serial@13820000 {
472 compatible = "samsung,exynos4210-uart";
473 reg = <0x13820000 0x100>;
474 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
476 clock-names = "uart", "clk_uart_baud0";
477 dmas = <&pdma0 17>, <&pdma0 18>;
478 dma-names = "rx", "tx";
479 status = "disabled";
480 };
b571abb3 481
73a901d0
MP		 482 serial_3: serial@13830000 {
483 compatible = "samsung,exynos4210-uart";
484 reg = <0x13830000 0x100>;
485 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
487 clock-names = "uart", "clk_uart_baud0";
488 dmas = <&pdma1 17>, <&pdma1 18>;
489 dma-names = "rx", "tx";
490 status = "disabled";
491 };
b571abb3 492
73a901d0
MP		 493 i2c_0: i2c@13860000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "samsung,s3c2440-i2c";
497 reg = <0x13860000 0x100>;
498 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clock CLK_I2C0>;
500 clock-names = "i2c";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c0_bus>;
503 status = "disabled";
504 };
b571abb3 505
73a901d0
MP		 506 i2c_1: i2c@13870000 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "samsung,s3c2440-i2c";
510 reg = <0x13870000 0x100>;
511 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clock CLK_I2C1>;
513 clock-names = "i2c";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c1_bus>;
516 status = "disabled";
517 };
b571abb3 518
73a901d0
MP		 519 i2c_2: i2c@13880000 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "samsung,s3c2440-i2c";
523 reg = <0x13880000 0x100>;
524 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clock CLK_I2C2>;
526 clock-names = "i2c";
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c2_bus>;
529 status = "disabled";
530 };
b571abb3 531
73a901d0
MP		 532 i2c_3: i2c@13890000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "samsung,s3c2440-i2c";
536 reg = <0x13890000 0x100>;
537 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clock CLK_I2C3>;
539 clock-names = "i2c";
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c3_bus>;
542 status = "disabled";
543 };
b571abb3 544
73a901d0
MP		 545 i2c_4: i2c@138a0000 {
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "samsung,s3c2440-i2c";
9ca5a7ce 549 reg = <0x138a0000 0x100>;
73a901d0
MP		 550 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&clock CLK_I2C4>;
552 clock-names = "i2c";
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c4_bus>;
555 status = "disabled";
556 };
b571abb3 557
73a901d0
MP		 558 i2c_5: i2c@138b0000 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 compatible = "samsung,s3c2440-i2c";
9ca5a7ce 562 reg = <0x138b0000 0x100>;
73a901d0
MP		 563 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clock CLK_I2C5>;
565 clock-names = "i2c";
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c5_bus>;
568 status = "disabled";
569 };
b571abb3 570
73a901d0
MP		 571 i2c_6: i2c@138c0000 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 compatible = "samsung,s3c2440-i2c";
9ca5a7ce 575 reg = <0x138c0000 0x100>;
73a901d0
MP		 576 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clock CLK_I2C6>;
578 clock-names = "i2c";
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c6_bus>;
581 status = "disabled";
582 };
b571abb3 583
73a901d0
MP		 584 i2c_7: i2c@138d0000 {
585 #address-cells = <1>;
586 #size-cells = <0>;
587 compatible = "samsung,s3c2440-i2c";
9ca5a7ce 588 reg = <0x138d0000 0x100>;
73a901d0
MP		 589 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clock CLK_I2C7>;
591 clock-names = "i2c";
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c7_bus>;
594 status = "disabled";
595 };
b571abb3 596
73a901d0
MP		 597 i2c_8: i2c@138e0000 {
598 #address-cells = <1>;
599 #size-cells = <0>;
600 compatible = "samsung,s3c2440-hdmiphy-i2c";
9ca5a7ce 601 reg = <0x138e0000 0x100>;
73a901d0
MP		 602 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clock CLK_I2C_HDMI>;
604 clock-names = "i2c";
605 status = "disabled";
b571abb3 606
7bac2cd7 607 hdmi_i2c_phy: hdmi-phy@38 {
af1c89dd 608 compatible = "samsung,exynos4210-hdmiphy";
73a901d0
MP		 609 reg = <0x38>;
610 };
ed80d4ca 611 };
ed80d4ca 612
73a901d0
MP		 613 spi_0: spi@13920000 {
614 compatible = "samsung,exynos4210-spi";
615 reg = <0x13920000 0x100>;
616 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
617 dmas = <&pdma0 7>, <&pdma0 6>;
618 dma-names = "tx", "rx";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
622 clock-names = "spi", "spi_busclk0";
623 pinctrl-names = "default";
624 pinctrl-0 = <&spi0_bus>;
625 status = "disabled";
626 };
b571abb3 627
73a901d0
MP		 628 spi_1: spi@13930000 {
629 compatible = "samsung,exynos4210-spi";
630 reg = <0x13930000 0x100>;
631 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
632 dmas = <&pdma1 7>, <&pdma1 6>;
633 dma-names = "tx", "rx";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
637 clock-names = "spi", "spi_busclk0";
638 pinctrl-names = "default";
639 pinctrl-0 = <&spi1_bus>;
640 status = "disabled";
641 };
b571abb3 642
73a901d0
MP		 643 spi_2: spi@13940000 {
644 compatible = "samsung,exynos4210-spi";
645 reg = <0x13940000 0x100>;
646 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
647 dmas = <&pdma0 9>, <&pdma0 8>;
648 dma-names = "tx", "rx";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
652 clock-names = "spi", "spi_busclk0";
653 pinctrl-names = "default";
654 pinctrl-0 = <&spi2_bus>;
655 status = "disabled";
656 };
cc4193ea 657
73a901d0
MP		 658 pwm: pwm@139d0000 {
659 compatible = "samsung,exynos4210-pwm";
9ca5a7ce 660 reg = <0x139d0000 0x1000>;
73a901d0
MP		 661 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clock CLK_PWM>;
667 clock-names = "timers";
668 #pwm-cells = <3>;
669 status = "disabled";
670 };
b571abb3 671
cfeb53ae 672 pdma0: dma-controller@12680000 {
f91423e9
KK		 673 compatible = "arm,pl330", "arm,primecell";
674 reg = <0x12680000 0x1000>;
675 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clock CLK_PDMA0>;
677 clock-names = "apb_pclk";
678 #dma-cells = <1>;
f91423e9
KK		 679 };
680
cfeb53ae 681 pdma1: dma-controller@12690000 {
f91423e9
KK		 682 compatible = "arm,pl330", "arm,primecell";
683 reg = <0x12690000 0x1000>;
684 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&clock CLK_PDMA1>;
686 clock-names = "apb_pclk";
687 #dma-cells = <1>;
f91423e9
KK		 688 };
689
cfeb53ae 690 mdma1: dma-controller@12850000 {
f91423e9
KK		 691 compatible = "arm,pl330", "arm,primecell";
692 reg = <0x12850000 0x1000>;
693 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&clock CLK_MDMA>;
695 clock-names = "apb_pclk";
696 #dma-cells = <1>;
f7e758af 697 };
768c3a56 698
73a901d0
MP		 699 fimd: fimd@11c00000 {
700 compatible = "samsung,exynos4210-fimd";
701 interrupt-parent = <&combiner>;
702 reg = <0x11c00000 0x20000>;
703 interrupt-names = "fifo", "vsync", "lcd_sys";
704 interrupts = <11 0>, <11 1>, <11 2>;
705 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
706 clock-names = "sclk_fimd", "fimd";
707 power-domains = <&pd_lcd0>;
708 iommus = <&sysmmu_fimd0>;
709 samsung,sysreg = <&sys_reg>;
710 status = "disabled";
711 };
30e0e476 712
73a901d0
MP		 713 tmu: tmu@100c0000 {
714 interrupt-parent = <&combiner>;
9ca5a7ce 715 reg = <0x100c0000 0x100>;
73a901d0
MP		 716 interrupts = <2 4>;
717 status = "disabled";
c05b799e 718 #thermal-sensor-cells = <0>;
73a901d0 719 };
9843a223 720
73a901d0
MP		 721 jpeg_codec: jpeg-codec@11840000 {
722 compatible = "samsung,exynos4210-jpeg";
723 reg = <0x11840000 0x1000>;
724 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clock CLK_JPEG>;
726 clock-names = "jpeg";
727 power-domains = <&pd_cam>;
728 iommus = <&sysmmu_jpeg>;
729 };
f470b859 730
73a901d0
MP		 731 rotator: rotator@12810000 {
732 compatible = "samsung,exynos4210-rotator";
733 reg = <0x12810000 0x64>;
734 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clock CLK_ROTATOR>;
736 clock-names = "rotator";
737 iommus = <&sysmmu_rotator>;
738 };
0c7e90b5 739
73a901d0
MP		 740 hdmi: hdmi@12d00000 {
741 compatible = "samsung,exynos4210-hdmi";
9ca5a7ce 742 reg = <0x12d00000 0x70000>;
73a901d0
MP		 743 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
744 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
745 "sclk_hdmiphy", "mout_hdmi";
746 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
747 <&clock CLK_SCLK_PIXEL>,
748 <&clock CLK_SCLK_HDMIPHY>,
749 <&clock CLK_MOUT_HDMI>;
750 phy = <&hdmi_i2c_phy>;
751 power-domains = <&pd_tv>;
752 samsung,syscon-phandle = <&pmu_system_controller>;
753 #sound-dai-cells = <0>;
754 status = "disabled";
755 };
c795c88d 756
73a901d0
MP		 757 hdmicec: cec@100b0000 {
758 compatible = "samsung,s5p-cec";
9ca5a7ce 759 reg = <0x100b0000 0x200>;
73a901d0
MP		 760 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&clock CLK_HDMI_CEC>;
762 clock-names = "hdmicec";
763 samsung,syscon-phandle = <&pmu_system_controller>;
764 hdmi-phandle = <&hdmi>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&hdmi_cec>;
767 status = "disabled";
768 };
ed80d4ca 769
73a901d0
MP		 770 mixer: mixer@12c10000 {
771 compatible = "samsung,exynos4210-mixer";
772 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
9ca5a7ce 773 reg = <0x12c10000 0x2100>, <0x12c00000 0x300>;
73a901d0
MP		 774 power-domains = <&pd_tv>;
775 iommus = <&sysmmu_tv>;
776 status = "disabled";
777 };
ed80d4ca 778
1c6831b4 779 ppmu_dmc0: ppmu@106a0000 {
73a901d0
MP		 780 compatible = "samsung,exynos-ppmu";
781 reg = <0x106a0000 0x2000>;
782 clocks = <&clock CLK_PPMUDMC0>;
783 clock-names = "ppmu";
784 status = "disabled";
785 };
30e0e476 786
1c6831b4 787 ppmu_dmc1: ppmu@106b0000 {
73a901d0
MP		 788 compatible = "samsung,exynos-ppmu";
789 reg = <0x106b0000 0x2000>;
790 clocks = <&clock CLK_PPMUDMC1>;
791 clock-names = "ppmu";
792 status = "disabled";
793 };
30e0e476 794
1c6831b4 795 ppmu_cpu: ppmu@106c0000 {
73a901d0
MP		 796 compatible = "samsung,exynos-ppmu";
797 reg = <0x106c0000 0x2000>;
798 clocks = <&clock CLK_PPMUCPU>;
799 clock-names = "ppmu";
800 status = "disabled";
801 };
30e0e476 802
1c6831b4 803 ppmu_rightbus: ppmu@112a0000 {
73a901d0
MP		 804 compatible = "samsung,exynos-ppmu";
805 reg = <0x112a0000 0x2000>;
806 clocks = <&clock CLK_PPMURIGHT>;
807 clock-names = "ppmu";
808 status = "disabled";
809 };
30e0e476 810
1c6831b4 811 ppmu_leftbus: ppmu@116a0000 {
73a901d0
MP		 812 compatible = "samsung,exynos-ppmu";
813 reg = <0x116a0000 0x2000>;
814 clocks = <&clock CLK_PPMULEFT>;
815 clock-names = "ppmu";
816 status = "disabled";
817 };
30e0e476 818
1c6831b4 819 ppmu_camif: ppmu@11ac0000 {
73a901d0
MP		 820 compatible = "samsung,exynos-ppmu";
821 reg = <0x11ac0000 0x2000>;
822 clocks = <&clock CLK_PPMUCAMIF>;
823 clock-names = "ppmu";
824 status = "disabled";
825 };
30e0e476 826
1c6831b4 827 ppmu_lcd0: ppmu@11e40000 {
73a901d0
MP		 828 compatible = "samsung,exynos-ppmu";
829 reg = <0x11e40000 0x2000>;
830 clocks = <&clock CLK_PPMULCD0>;
831 clock-names = "ppmu";
832 status = "disabled";
833 };
30e0e476 834
1c6831b4 835 ppmu_fsys: ppmu@12630000 {
73a901d0
MP		 836 compatible = "samsung,exynos-ppmu";
837 reg = <0x12630000 0x2000>;
838 status = "disabled";
839 };
30e0e476 840
1c6831b4 841 ppmu_image: ppmu@12aa0000 {
73a901d0
MP		 842 compatible = "samsung,exynos-ppmu";
843 reg = <0x12aa0000 0x2000>;
844 clocks = <&clock CLK_PPMUIMAGE>;
845 clock-names = "ppmu";
846 status = "disabled";
847 };
30e0e476 848
1c6831b4 849 ppmu_tv: ppmu@12e40000 {
73a901d0
MP		 850 compatible = "samsung,exynos-ppmu";
851 reg = <0x12e40000 0x2000>;
852 clocks = <&clock CLK_PPMUTV>;
853 clock-names = "ppmu";
854 status = "disabled";
855 };
30e0e476 856
1c6831b4 857 ppmu_g3d: ppmu@13220000 {
73a901d0
MP		 858 compatible = "samsung,exynos-ppmu";
859 reg = <0x13220000 0x2000>;
860 clocks = <&clock CLK_PPMUG3D>;
861 clock-names = "ppmu";
862 status = "disabled";
863 };
30e0e476 864
1c6831b4 865 ppmu_mfc_left: ppmu@13660000 {
73a901d0
MP		 866 compatible = "samsung,exynos-ppmu";
867 reg = <0x13660000 0x2000>;
868 clocks = <&clock CLK_PPMUMFC_L>;
869 clock-names = "ppmu";
870 status = "disabled";
871 };
30e0e476 872
1c6831b4 873 ppmu_mfc_right: ppmu@13670000 {
73a901d0
MP		 874 compatible = "samsung,exynos-ppmu";
875 reg = <0x13670000 0x2000>;
876 clocks = <&clock CLK_PPMUMFC_R>;
877 clock-names = "ppmu";
878 status = "disabled";
879 };
71d3a9fb 880
73a901d0
MP		 881 sysmmu_mfc_l: sysmmu@13620000 {
882 compatible = "samsung,exynos-sysmmu";
883 reg = <0x13620000 0x1000>;
884 interrupt-parent = <&combiner>;
885 interrupts = <5 5>;
886 clock-names = "sysmmu", "master";
887 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
888 power-domains = <&pd_mfc>;
889 #iommu-cells = <0>;
890 };
71d3a9fb 891
73a901d0
MP		 892 sysmmu_mfc_r: sysmmu@13630000 {
893 compatible = "samsung,exynos-sysmmu";
894 reg = <0x13630000 0x1000>;
895 interrupt-parent = <&combiner>;
896 interrupts = <5 6>;
897 clock-names = "sysmmu", "master";
898 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
899 power-domains = <&pd_mfc>;
900 #iommu-cells = <0>;
901 };
71d3a9fb 902
73a901d0
MP		 903 sysmmu_tv: sysmmu@12e20000 {
904 compatible = "samsung,exynos-sysmmu";
9ca5a7ce 905 reg = <0x12e20000 0x1000>;
73a901d0
MP		 906 interrupt-parent = <&combiner>;
907 interrupts = <5 4>;
908 clock-names = "sysmmu", "master";
909 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
910 power-domains = <&pd_tv>;
911 #iommu-cells = <0>;
912 };
71d3a9fb 913
73a901d0
MP		 914 sysmmu_fimc0: sysmmu@11a20000 {
915 compatible = "samsung,exynos-sysmmu";
9ca5a7ce 916 reg = <0x11a20000 0x1000>;
73a901d0
MP		 917 interrupt-parent = <&combiner>;
918 interrupts = <4 2>;
919 clock-names = "sysmmu", "master";
920 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
921 power-domains = <&pd_cam>;
922 #iommu-cells = <0>;
923 };
71d3a9fb 924
73a901d0
MP		 925 sysmmu_fimc1: sysmmu@11a30000 {
926 compatible = "samsung,exynos-sysmmu";
9ca5a7ce 927 reg = <0x11a30000 0x1000>;
73a901d0
MP		 928 interrupt-parent = <&combiner>;
929 interrupts = <4 3>;
930 clock-names = "sysmmu", "master";
931 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
932 power-domains = <&pd_cam>;
933 #iommu-cells = <0>;
934 };
71d3a9fb 935
73a901d0
MP		 936 sysmmu_fimc2: sysmmu@11a40000 {
937 compatible = "samsung,exynos-sysmmu";
9ca5a7ce 938 reg = <0x11a40000 0x1000>;
73a901d0
MP		 939 interrupt-parent = <&combiner>;
940 interrupts = <4 4>;
941 clock-names = "sysmmu", "master";
942 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
943 power-domains = <&pd_cam>;
944 #iommu-cells = <0>;
945 };
71d3a9fb 946
73a901d0
MP		 947 sysmmu_fimc3: sysmmu@11a50000 {
948 compatible = "samsung,exynos-sysmmu";
9ca5a7ce 949 reg = <0x11a50000 0x1000>;
73a901d0
MP		 950 interrupt-parent = <&combiner>;
951 interrupts = <4 5>;
952 clock-names = "sysmmu", "master";
953 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
954 power-domains = <&pd_cam>;
955 #iommu-cells = <0>;
956 };
71d3a9fb 957
73a901d0
MP		 958 sysmmu_jpeg: sysmmu@11a60000 {
959 compatible = "samsung,exynos-sysmmu";
9ca5a7ce 960 reg = <0x11a60000 0x1000>;
73a901d0
MP		 961 interrupt-parent = <&combiner>;
962 interrupts = <4 6>;
963 clock-names = "sysmmu", "master";
964 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
965 power-domains = <&pd_cam>;
966 #iommu-cells = <0>;
967 };
71d3a9fb 968
73a901d0
MP		 969 sysmmu_rotator: sysmmu@12a30000 {
970 compatible = "samsung,exynos-sysmmu";
9ca5a7ce 971 reg = <0x12a30000 0x1000>;
73a901d0
MP		 972 interrupt-parent = <&combiner>;
973 interrupts = <5 0>;
974 clock-names = "sysmmu", "master";
975 clocks = <&clock CLK_SMMU_ROTATOR>,
976 <&clock CLK_ROTATOR>;
977 #iommu-cells = <0>;
978 };
71d3a9fb 979
73a901d0
MP		 980 sysmmu_fimd0: sysmmu@11e20000 {
981 compatible = "samsung,exynos-sysmmu";
9ca5a7ce 982 reg = <0x11e20000 0x1000>;
73a901d0
MP		 983 interrupt-parent = <&combiner>;
984 interrupts = <5 2>;
985 clock-names = "sysmmu", "master";
986 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
987 power-domains = <&pd_lcd0>;
988 #iommu-cells = <0>;
989 };
a452977c 990
73a901d0
MP		 991 sss: sss@10830000 {
992 compatible = "samsung,exynos4210-secss";
993 reg = <0x10830000 0x300>;
994 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&clock CLK_SSS>;
996 clock-names = "secss";
997 };
6c5eb1db 998
73a901d0
MP		 999 prng: rng@10830400 {
1000 compatible = "samsung,exynos4-rng";
1001 reg = <0x10830400 0x200>;
1002 clocks = <&clock CLK_SSS>;
1003 clock-names = "secss";
1004 };
a452977c 1005 };
b571abb3 1006};
a03e9dac
KK		 1007
1008#include "exynos-syscon-restart.dtsi"
Linux 6.x block layer and io_uring tree(s)