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cc4637f7 | 1 | // SPDX-License-Identifier: GPL-2.0 |
b571abb3 TF |
2 | /* |
3 | * Samsung's Exynos4 SoC series common device tree source | |
4 | * | |
5 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
6 | * http://www.samsung.com | |
7 | * Copyright (c) 2010-2011 Linaro Ltd. | |
8 | * www.linaro.org | |
9 | * | |
10 | * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular | |
11 | * SoCs from Exynos4 series can include this file and provide values for SoCs | |
2f690530 | 12 | * specific bindings. |
b571abb3 TF |
13 | * |
14 | * Note: This file does not include device nodes for all the controllers in | |
15 | * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional | |
16 | * nodes can be added to this file. | |
b571abb3 TF |
17 | */ |
18 | ||
1c75a78a | 19 | #include <dt-bindings/clock/exynos4.h> |
990a7bfd | 20 | #include <dt-bindings/clock/exynos-audss-clk.h> |
74e2c958 | 21 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
63aee4fa | 22 | #include <dt-bindings/interrupt-controller/irq.h> |
b571abb3 TF |
23 | |
24 | / { | |
25 | interrupt-parent = <&gic>; | |
1354835a JMC |
26 | #address-cells = <1>; |
27 | #size-cells = <1>; | |
b571abb3 TF |
28 | |
29 | aliases { | |
30 | spi0 = &spi_0; | |
31 | spi1 = &spi_1; | |
32 | spi2 = &spi_2; | |
34db4990 DA |
33 | i2c0 = &i2c_0; |
34 | i2c1 = &i2c_1; | |
35 | i2c2 = &i2c_2; | |
36 | i2c3 = &i2c_3; | |
37 | i2c4 = &i2c_4; | |
38 | i2c5 = &i2c_5; | |
39 | i2c6 = &i2c_6; | |
40 | i2c7 = &i2c_7; | |
ed80d4ca | 41 | i2c8 = &i2c_8; |
d1b8a41d SN |
42 | csis0 = &csis_0; |
43 | csis1 = &csis_1; | |
44 | fimc0 = &fimc_0; | |
45 | fimc1 = &fimc_1; | |
46 | fimc2 = &fimc_2; | |
47 | fimc3 = &fimc_3; | |
1e64f48e TF |
48 | serial0 = &serial_0; |
49 | serial1 = &serial_1; | |
50 | serial2 = &serial_2; | |
51 | serial3 = &serial_3; | |
b571abb3 TF |
52 | }; |
53 | ||
be003001 KK |
54 | pmu: pmu { |
55 | compatible = "arm,cortex-a9-pmu"; | |
56 | interrupt-parent = <&combiner>; | |
6da4e11c | 57 | status = "disabled"; |
be003001 KK |
58 | }; |
59 | ||
73a901d0 MP |
60 | soc: soc { |
61 | compatible = "simple-bus"; | |
62 | #address-cells = <1>; | |
63 | #size-cells = <1>; | |
64 | ranges; | |
990a7bfd | 65 | |
73a901d0 MP |
66 | clock_audss: clock-controller@3810000 { |
67 | compatible = "samsung,exynos4210-audss-clock"; | |
9ca5a7ce | 68 | reg = <0x03810000 0x0c>; |
73a901d0 MP |
69 | #clock-cells = <1>; |
70 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, | |
71 | <&clock CLK_SCLK_AUDIO0>, | |
72 | <&clock CLK_SCLK_AUDIO0>; | |
73 | clock-names = "pll_ref", "pll_in", "sclk_audio", | |
74 | "sclk_pcm_in"; | |
75 | }; | |
096ee6ad | 76 | |
73a901d0 MP |
77 | i2s0: i2s@3830000 { |
78 | compatible = "samsung,s5pv210-i2s"; | |
79 | reg = <0x03830000 0x100>; | |
80 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
81 | <&clock_audss EXYNOS_DOUT_AUD_BUS>, | |
82 | <&clock_audss EXYNOS_SCLK_I2S>; | |
83 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
84 | #clock-cells = <1>; | |
85 | clock-output-names = "i2s_cdclk0"; | |
86 | dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; | |
87 | dma-names = "tx", "rx", "tx-sec"; | |
88 | samsung,idma-addr = <0x03000000>; | |
89 | #sound-dai-cells = <1>; | |
90 | status = "disabled"; | |
91 | }; | |
05a3589f | 92 | |
73a901d0 MP |
93 | chipid@10000000 { |
94 | compatible = "samsung,exynos4210-chipid"; | |
95 | reg = <0x10000000 0x100>; | |
96 | }; | |
df4400ac | 97 | |
73a901d0 MP |
98 | scu: snoop-control-unit@10500000 { |
99 | compatible = "arm,cortex-a9-scu"; | |
100 | reg = <0x10500000 0x2000>; | |
101 | }; | |
21b190d2 | 102 | |
73a901d0 MP |
103 | memory-controller@12570000 { |
104 | compatible = "samsung,exynos4210-srom"; | |
105 | reg = <0x12570000 0x14>; | |
106 | }; | |
91d88f03 | 107 | |
e39fc20f | 108 | pd_mfc: power-domain@10023c40 { |
73a901d0 | 109 | compatible = "samsung,exynos4210-pd"; |
9ca5a7ce | 110 | reg = <0x10023c40 0x20>; |
73a901d0 MP |
111 | #power-domain-cells = <0>; |
112 | label = "MFC"; | |
113 | }; | |
91d88f03 | 114 | |
e39fc20f | 115 | pd_g3d: power-domain@10023c60 { |
73a901d0 | 116 | compatible = "samsung,exynos4210-pd"; |
9ca5a7ce | 117 | reg = <0x10023c60 0x20>; |
73a901d0 MP |
118 | #power-domain-cells = <0>; |
119 | label = "G3D"; | |
120 | }; | |
91d88f03 | 121 | |
e39fc20f | 122 | pd_lcd0: power-domain@10023c80 { |
73a901d0 | 123 | compatible = "samsung,exynos4210-pd"; |
9ca5a7ce | 124 | reg = <0x10023c80 0x20>; |
73a901d0 MP |
125 | #power-domain-cells = <0>; |
126 | label = "LCD0"; | |
127 | }; | |
91d88f03 | 128 | |
e39fc20f | 129 | pd_tv: power-domain@10023c20 { |
73a901d0 | 130 | compatible = "samsung,exynos4210-pd"; |
9ca5a7ce | 131 | reg = <0x10023c20 0x20>; |
73a901d0 MP |
132 | #power-domain-cells = <0>; |
133 | power-domains = <&pd_lcd0>; | |
134 | label = "TV"; | |
135 | }; | |
b571abb3 | 136 | |
e39fc20f | 137 | pd_cam: power-domain@10023c00 { |
73a901d0 | 138 | compatible = "samsung,exynos4210-pd"; |
9ca5a7ce | 139 | reg = <0x10023c00 0x20>; |
73a901d0 MP |
140 | #power-domain-cells = <0>; |
141 | label = "CAM"; | |
142 | }; | |
10ea1f18 | 143 | |
e39fc20f | 144 | pd_gps: power-domain@10023ce0 { |
73a901d0 | 145 | compatible = "samsung,exynos4210-pd"; |
9ca5a7ce | 146 | reg = <0x10023ce0 0x20>; |
73a901d0 MP |
147 | #power-domain-cells = <0>; |
148 | label = "GPS"; | |
149 | }; | |
b571abb3 | 150 | |
e39fc20f | 151 | pd_gps_alive: power-domain@10023d00 { |
73a901d0 | 152 | compatible = "samsung,exynos4210-pd"; |
9ca5a7ce | 153 | reg = <0x10023d00 0x20>; |
73a901d0 MP |
154 | #power-domain-cells = <0>; |
155 | label = "GPS alive"; | |
156 | }; | |
b571abb3 | 157 | |
73a901d0 MP |
158 | gic: interrupt-controller@10490000 { |
159 | compatible = "arm,cortex-a9-gic"; | |
160 | #interrupt-cells = <3>; | |
161 | interrupt-controller; | |
162 | reg = <0x10490000 0x10000>, <0x10480000 0x10000>; | |
163 | }; | |
6f4b82a3 | 164 | |
73a901d0 MP |
165 | combiner: interrupt-controller@10440000 { |
166 | compatible = "samsung,exynos4210-combiner"; | |
167 | #interrupt-cells = <2>; | |
168 | interrupt-controller; | |
169 | reg = <0x10440000 0x1000>; | |
170 | }; | |
a64b1b22 | 171 | |
73a901d0 MP |
172 | sys_reg: syscon@10010000 { |
173 | compatible = "samsung,exynos4-sysreg", "syscon"; | |
174 | reg = <0x10010000 0x400>; | |
175 | }; | |
8b7dd64c | 176 | |
73a901d0 | 177 | pmu_system_controller: system-controller@10020000 { |
d237b227 | 178 | compatible = "samsung,exynos4210-pmu", "simple-mfd", "syscon"; |
73a901d0 MP |
179 | reg = <0x10020000 0x4000>; |
180 | interrupt-controller; | |
181 | #interrupt-cells = <3>; | |
182 | interrupt-parent = <&gic>; | |
d237b227 KK |
183 | |
184 | mipi_phy: mipi-phy { | |
185 | compatible = "samsung,s5pv210-mipi-video-phy"; | |
186 | #phy-cells = <1>; | |
187 | }; | |
73a901d0 | 188 | }; |
d1b8a41d | 189 | |
73a901d0 MP |
190 | dsi_0: dsi@11c80000 { |
191 | compatible = "samsung,exynos4210-mipi-dsi"; | |
9ca5a7ce | 192 | reg = <0x11c80000 0x10000>; |
73a901d0 MP |
193 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
194 | power-domains = <&pd_lcd0>; | |
195 | phys = <&mipi_phy 1>; | |
196 | phy-names = "dsim"; | |
197 | clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; | |
198 | clock-names = "bus_clk", "sclk_mipi"; | |
d1b8a41d | 199 | status = "disabled"; |
73a901d0 MP |
200 | #address-cells = <1>; |
201 | #size-cells = <0>; | |
d1b8a41d SN |
202 | }; |
203 | ||
a1ca5609 KK |
204 | camera: camera@11800000 { |
205 | compatible = "samsung,fimc"; | |
d1b8a41d | 206 | status = "disabled"; |
73a901d0 MP |
207 | #address-cells = <1>; |
208 | #size-cells = <1>; | |
209 | #clock-cells = <1>; | |
210 | clock-output-names = "cam_a_clkout", "cam_b_clkout"; | |
211 | ranges; | |
212 | ||
213 | fimc_0: fimc@11800000 { | |
214 | compatible = "samsung,exynos4210-fimc"; | |
215 | reg = <0x11800000 0x1000>; | |
216 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
217 | clocks = <&clock CLK_FIMC0>, | |
218 | <&clock CLK_SCLK_FIMC0>; | |
219 | clock-names = "fimc", "sclk_fimc"; | |
220 | power-domains = <&pd_cam>; | |
221 | samsung,sysreg = <&sys_reg>; | |
222 | iommus = <&sysmmu_fimc0>; | |
223 | status = "disabled"; | |
224 | }; | |
225 | ||
226 | fimc_1: fimc@11810000 { | |
227 | compatible = "samsung,exynos4210-fimc"; | |
228 | reg = <0x11810000 0x1000>; | |
229 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
230 | clocks = <&clock CLK_FIMC1>, | |
231 | <&clock CLK_SCLK_FIMC1>; | |
232 | clock-names = "fimc", "sclk_fimc"; | |
233 | power-domains = <&pd_cam>; | |
234 | samsung,sysreg = <&sys_reg>; | |
235 | iommus = <&sysmmu_fimc1>; | |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
239 | fimc_2: fimc@11820000 { | |
240 | compatible = "samsung,exynos4210-fimc"; | |
241 | reg = <0x11820000 0x1000>; | |
242 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
243 | clocks = <&clock CLK_FIMC2>, | |
244 | <&clock CLK_SCLK_FIMC2>; | |
245 | clock-names = "fimc", "sclk_fimc"; | |
246 | power-domains = <&pd_cam>; | |
247 | samsung,sysreg = <&sys_reg>; | |
248 | iommus = <&sysmmu_fimc2>; | |
249 | status = "disabled"; | |
250 | }; | |
251 | ||
252 | fimc_3: fimc@11830000 { | |
253 | compatible = "samsung,exynos4210-fimc"; | |
254 | reg = <0x11830000 0x1000>; | |
255 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
256 | clocks = <&clock CLK_FIMC3>, | |
257 | <&clock CLK_SCLK_FIMC3>; | |
258 | clock-names = "fimc", "sclk_fimc"; | |
259 | power-domains = <&pd_cam>; | |
260 | samsung,sysreg = <&sys_reg>; | |
261 | iommus = <&sysmmu_fimc3>; | |
262 | status = "disabled"; | |
263 | }; | |
264 | ||
265 | csis_0: csis@11880000 { | |
266 | compatible = "samsung,exynos4210-csis"; | |
267 | reg = <0x11880000 0x4000>; | |
268 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
269 | clocks = <&clock CLK_CSIS0>, | |
270 | <&clock CLK_SCLK_CSIS0>; | |
271 | clock-names = "csis", "sclk_csis"; | |
272 | bus-width = <4>; | |
273 | power-domains = <&pd_cam>; | |
274 | phys = <&mipi_phy 0>; | |
275 | phy-names = "csis"; | |
276 | status = "disabled"; | |
277 | #address-cells = <1>; | |
278 | #size-cells = <0>; | |
279 | }; | |
280 | ||
281 | csis_1: csis@11890000 { | |
282 | compatible = "samsung,exynos4210-csis"; | |
283 | reg = <0x11890000 0x4000>; | |
284 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
285 | clocks = <&clock CLK_CSIS1>, | |
286 | <&clock CLK_SCLK_CSIS1>; | |
287 | clock-names = "csis", "sclk_csis"; | |
288 | bus-width = <2>; | |
289 | power-domains = <&pd_cam>; | |
290 | phys = <&mipi_phy 2>; | |
291 | phy-names = "csis"; | |
292 | status = "disabled"; | |
293 | #address-cells = <1>; | |
294 | #size-cells = <0>; | |
295 | }; | |
d1b8a41d SN |
296 | }; |
297 | ||
73a901d0 MP |
298 | rtc: rtc@10070000 { |
299 | compatible = "samsung,s3c6410-rtc"; | |
300 | reg = <0x10070000 0x100>; | |
301 | interrupt-parent = <&pmu_system_controller>; | |
302 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
303 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
304 | clocks = <&clock CLK_RTC>; | |
305 | clock-names = "rtc"; | |
d1b8a41d SN |
306 | status = "disabled"; |
307 | }; | |
308 | ||
73a901d0 MP |
309 | keypad: keypad@100a0000 { |
310 | compatible = "samsung,s5pv210-keypad"; | |
9ca5a7ce | 311 | reg = <0x100a0000 0x100>; |
73a901d0 MP |
312 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
313 | clocks = <&clock CLK_KEYIF>; | |
314 | clock-names = "keypad"; | |
d1b8a41d SN |
315 | status = "disabled"; |
316 | }; | |
317 | ||
c805b77c | 318 | sdhci_0: mmc@12510000 { |
73a901d0 MP |
319 | compatible = "samsung,exynos4210-sdhci"; |
320 | reg = <0x12510000 0x100>; | |
321 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
322 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; | |
323 | clock-names = "hsmmc", "mmc_busclk.2"; | |
d1b8a41d | 324 | status = "disabled"; |
d1b8a41d SN |
325 | }; |
326 | ||
c805b77c | 327 | sdhci_1: mmc@12520000 { |
73a901d0 MP |
328 | compatible = "samsung,exynos4210-sdhci"; |
329 | reg = <0x12520000 0x100>; | |
330 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
331 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; | |
332 | clock-names = "hsmmc", "mmc_busclk.2"; | |
d1b8a41d | 333 | status = "disabled"; |
d1b8a41d | 334 | }; |
b571abb3 | 335 | |
c805b77c | 336 | sdhci_2: mmc@12530000 { |
73a901d0 MP |
337 | compatible = "samsung,exynos4210-sdhci"; |
338 | reg = <0x12530000 0x100>; | |
339 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
340 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; | |
341 | clock-names = "hsmmc", "mmc_busclk.2"; | |
342 | status = "disabled"; | |
343 | }; | |
26bbd41f | 344 | |
c805b77c | 345 | sdhci_3: mmc@12540000 { |
73a901d0 MP |
346 | compatible = "samsung,exynos4210-sdhci"; |
347 | reg = <0x12540000 0x100>; | |
348 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
349 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; | |
350 | clock-names = "hsmmc", "mmc_busclk.2"; | |
351 | status = "disabled"; | |
352 | }; | |
ef14d94c | 353 | |
7bac2cd7 | 354 | exynos_usbphy: usb-phy@125b0000 { |
73a901d0 | 355 | compatible = "samsung,exynos4210-usb2-phy"; |
9ca5a7ce | 356 | reg = <0x125b0000 0x100>; |
73a901d0 MP |
357 | samsung,pmureg-phandle = <&pmu_system_controller>; |
358 | clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; | |
359 | clock-names = "phy", "ref"; | |
360 | #phy-cells = <1>; | |
361 | status = "disabled"; | |
362 | }; | |
b571abb3 | 363 | |
177c86fa | 364 | hsotg: usb@12480000 { |
73a901d0 MP |
365 | compatible = "samsung,s3c6400-hsotg"; |
366 | reg = <0x12480000 0x20000>; | |
367 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
368 | clocks = <&clock CLK_USB_DEVICE>; | |
369 | clock-names = "otg"; | |
370 | phys = <&exynos_usbphy 0>; | |
371 | phy-names = "usb2-phy"; | |
dfaf06ba | 372 | status = "disabled"; |
366126d5 | 373 | }; |
73a901d0 | 374 | |
b412be7d | 375 | ehci: usb@12580000 { |
73a901d0 MP |
376 | compatible = "samsung,exynos4210-ehci"; |
377 | reg = <0x12580000 0x100>; | |
378 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
379 | clocks = <&clock CLK_USB_HOST>; | |
380 | clock-names = "usbhost"; | |
dfaf06ba | 381 | status = "disabled"; |
314de2f6 MS |
382 | phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>; |
383 | phy-names = "host", "hsic0", "hsic1"; | |
366126d5 | 384 | }; |
73a901d0 | 385 | |
b412be7d | 386 | ohci: usb@12590000 { |
73a901d0 MP |
387 | compatible = "samsung,exynos4210-ohci"; |
388 | reg = <0x12590000 0x100>; | |
389 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
390 | clocks = <&clock CLK_USB_HOST>; | |
391 | clock-names = "usbhost"; | |
dfaf06ba | 392 | status = "disabled"; |
314de2f6 MS |
393 | phys = <&exynos_usbphy 1>; |
394 | phy-names = "host"; | |
366126d5 | 395 | }; |
6f9d02a0 | 396 | |
8386e6a7 MS |
397 | gpu: gpu@13000000 { |
398 | compatible = "samsung,exynos4210-mali", "arm,mali-400"; | |
399 | reg = <0x13000000 0x10000>; | |
400 | /* | |
401 | * CLK_G3D is not actually bus clock but a IP-level clock. | |
402 | * The bus clock is not described in hardware manual. | |
403 | */ | |
404 | clocks = <&clock CLK_G3D>, | |
405 | <&clock CLK_SCLK_G3D>; | |
406 | clock-names = "bus", "core"; | |
407 | power-domains = <&pd_g3d>; | |
408 | status = "disabled"; | |
409 | }; | |
410 | ||
73a901d0 MP |
411 | i2s1: i2s@13960000 { |
412 | compatible = "samsung,s3c6410-i2s"; | |
413 | reg = <0x13960000 0x100>; | |
414 | clocks = <&clock CLK_I2S1>; | |
415 | clock-names = "iis"; | |
416 | #clock-cells = <1>; | |
417 | clock-output-names = "i2s_cdclk1"; | |
418 | dmas = <&pdma1 12>, <&pdma1 11>; | |
419 | dma-names = "tx", "rx"; | |
420 | #sound-dai-cells = <1>; | |
dfaf06ba | 421 | status = "disabled"; |
366126d5 | 422 | }; |
6f9d02a0 | 423 | |
73a901d0 MP |
424 | i2s2: i2s@13970000 { |
425 | compatible = "samsung,s3c6410-i2s"; | |
426 | reg = <0x13970000 0x100>; | |
427 | clocks = <&clock CLK_I2S2>; | |
428 | clock-names = "iis"; | |
429 | #clock-cells = <1>; | |
430 | clock-output-names = "i2s_cdclk2"; | |
431 | dmas = <&pdma0 14>, <&pdma0 13>; | |
432 | dma-names = "tx", "rx"; | |
433 | #sound-dai-cells = <1>; | |
434 | status = "disabled"; | |
435 | }; | |
990a7bfd | 436 | |
73a901d0 MP |
437 | mfc: codec@13400000 { |
438 | compatible = "samsung,mfc-v5"; | |
439 | reg = <0x13400000 0x10000>; | |
440 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
441 | power-domains = <&pd_mfc>; | |
442 | clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; | |
443 | clock-names = "mfc", "sclk_mfc"; | |
444 | iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; | |
445 | iommu-names = "left", "right"; | |
446 | }; | |
990a7bfd | 447 | |
73a901d0 MP |
448 | serial_0: serial@13800000 { |
449 | compatible = "samsung,exynos4210-uart"; | |
450 | reg = <0x13800000 0x100>; | |
451 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
452 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | |
453 | clock-names = "uart", "clk_uart_baud0"; | |
454 | dmas = <&pdma0 15>, <&pdma0 16>; | |
455 | dma-names = "rx", "tx"; | |
456 | status = "disabled"; | |
457 | }; | |
20901f74 | 458 | |
73a901d0 MP |
459 | serial_1: serial@13810000 { |
460 | compatible = "samsung,exynos4210-uart"; | |
461 | reg = <0x13810000 0x100>; | |
462 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
463 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | |
464 | clock-names = "uart", "clk_uart_baud0"; | |
465 | dmas = <&pdma1 15>, <&pdma1 16>; | |
466 | dma-names = "rx", "tx"; | |
467 | status = "disabled"; | |
468 | }; | |
b571abb3 | 469 | |
73a901d0 MP |
470 | serial_2: serial@13820000 { |
471 | compatible = "samsung,exynos4210-uart"; | |
472 | reg = <0x13820000 0x100>; | |
473 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
474 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | |
475 | clock-names = "uart", "clk_uart_baud0"; | |
476 | dmas = <&pdma0 17>, <&pdma0 18>; | |
477 | dma-names = "rx", "tx"; | |
478 | status = "disabled"; | |
479 | }; | |
b571abb3 | 480 | |
73a901d0 MP |
481 | serial_3: serial@13830000 { |
482 | compatible = "samsung,exynos4210-uart"; | |
483 | reg = <0x13830000 0x100>; | |
484 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
485 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; | |
486 | clock-names = "uart", "clk_uart_baud0"; | |
487 | dmas = <&pdma1 17>, <&pdma1 18>; | |
488 | dma-names = "rx", "tx"; | |
489 | status = "disabled"; | |
490 | }; | |
b571abb3 | 491 | |
73a901d0 MP |
492 | i2c_0: i2c@13860000 { |
493 | #address-cells = <1>; | |
494 | #size-cells = <0>; | |
495 | compatible = "samsung,s3c2440-i2c"; | |
496 | reg = <0x13860000 0x100>; | |
497 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
498 | clocks = <&clock CLK_I2C0>; | |
499 | clock-names = "i2c"; | |
500 | pinctrl-names = "default"; | |
501 | pinctrl-0 = <&i2c0_bus>; | |
502 | status = "disabled"; | |
503 | }; | |
b571abb3 | 504 | |
73a901d0 MP |
505 | i2c_1: i2c@13870000 { |
506 | #address-cells = <1>; | |
507 | #size-cells = <0>; | |
508 | compatible = "samsung,s3c2440-i2c"; | |
509 | reg = <0x13870000 0x100>; | |
510 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
511 | clocks = <&clock CLK_I2C1>; | |
512 | clock-names = "i2c"; | |
513 | pinctrl-names = "default"; | |
514 | pinctrl-0 = <&i2c1_bus>; | |
515 | status = "disabled"; | |
516 | }; | |
b571abb3 | 517 | |
73a901d0 MP |
518 | i2c_2: i2c@13880000 { |
519 | #address-cells = <1>; | |
520 | #size-cells = <0>; | |
521 | compatible = "samsung,s3c2440-i2c"; | |
522 | reg = <0x13880000 0x100>; | |
523 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
524 | clocks = <&clock CLK_I2C2>; | |
525 | clock-names = "i2c"; | |
526 | pinctrl-names = "default"; | |
527 | pinctrl-0 = <&i2c2_bus>; | |
528 | status = "disabled"; | |
529 | }; | |
b571abb3 | 530 | |
73a901d0 MP |
531 | i2c_3: i2c@13890000 { |
532 | #address-cells = <1>; | |
533 | #size-cells = <0>; | |
534 | compatible = "samsung,s3c2440-i2c"; | |
535 | reg = <0x13890000 0x100>; | |
536 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
537 | clocks = <&clock CLK_I2C3>; | |
538 | clock-names = "i2c"; | |
539 | pinctrl-names = "default"; | |
540 | pinctrl-0 = <&i2c3_bus>; | |
541 | status = "disabled"; | |
542 | }; | |
b571abb3 | 543 | |
73a901d0 MP |
544 | i2c_4: i2c@138a0000 { |
545 | #address-cells = <1>; | |
546 | #size-cells = <0>; | |
547 | compatible = "samsung,s3c2440-i2c"; | |
9ca5a7ce | 548 | reg = <0x138a0000 0x100>; |
73a901d0 MP |
549 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
550 | clocks = <&clock CLK_I2C4>; | |
551 | clock-names = "i2c"; | |
552 | pinctrl-names = "default"; | |
553 | pinctrl-0 = <&i2c4_bus>; | |
554 | status = "disabled"; | |
555 | }; | |
b571abb3 | 556 | |
73a901d0 MP |
557 | i2c_5: i2c@138b0000 { |
558 | #address-cells = <1>; | |
559 | #size-cells = <0>; | |
560 | compatible = "samsung,s3c2440-i2c"; | |
9ca5a7ce | 561 | reg = <0x138b0000 0x100>; |
73a901d0 MP |
562 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
563 | clocks = <&clock CLK_I2C5>; | |
564 | clock-names = "i2c"; | |
565 | pinctrl-names = "default"; | |
566 | pinctrl-0 = <&i2c5_bus>; | |
567 | status = "disabled"; | |
568 | }; | |
b571abb3 | 569 | |
73a901d0 MP |
570 | i2c_6: i2c@138c0000 { |
571 | #address-cells = <1>; | |
572 | #size-cells = <0>; | |
573 | compatible = "samsung,s3c2440-i2c"; | |
9ca5a7ce | 574 | reg = <0x138c0000 0x100>; |
73a901d0 MP |
575 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
576 | clocks = <&clock CLK_I2C6>; | |
577 | clock-names = "i2c"; | |
578 | pinctrl-names = "default"; | |
579 | pinctrl-0 = <&i2c6_bus>; | |
580 | status = "disabled"; | |
581 | }; | |
b571abb3 | 582 | |
73a901d0 MP |
583 | i2c_7: i2c@138d0000 { |
584 | #address-cells = <1>; | |
585 | #size-cells = <0>; | |
586 | compatible = "samsung,s3c2440-i2c"; | |
9ca5a7ce | 587 | reg = <0x138d0000 0x100>; |
73a901d0 MP |
588 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
589 | clocks = <&clock CLK_I2C7>; | |
590 | clock-names = "i2c"; | |
591 | pinctrl-names = "default"; | |
592 | pinctrl-0 = <&i2c7_bus>; | |
593 | status = "disabled"; | |
594 | }; | |
b571abb3 | 595 | |
73a901d0 MP |
596 | i2c_8: i2c@138e0000 { |
597 | #address-cells = <1>; | |
598 | #size-cells = <0>; | |
599 | compatible = "samsung,s3c2440-hdmiphy-i2c"; | |
9ca5a7ce | 600 | reg = <0x138e0000 0x100>; |
73a901d0 MP |
601 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
602 | clocks = <&clock CLK_I2C_HDMI>; | |
603 | clock-names = "i2c"; | |
604 | status = "disabled"; | |
b571abb3 | 605 | |
7bac2cd7 | 606 | hdmi_i2c_phy: hdmi-phy@38 { |
af1c89dd | 607 | compatible = "samsung,exynos4210-hdmiphy"; |
73a901d0 MP |
608 | reg = <0x38>; |
609 | }; | |
ed80d4ca | 610 | }; |
ed80d4ca | 611 | |
73a901d0 MP |
612 | spi_0: spi@13920000 { |
613 | compatible = "samsung,exynos4210-spi"; | |
614 | reg = <0x13920000 0x100>; | |
615 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
616 | dmas = <&pdma0 7>, <&pdma0 6>; | |
617 | dma-names = "tx", "rx"; | |
618 | #address-cells = <1>; | |
619 | #size-cells = <0>; | |
620 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; | |
621 | clock-names = "spi", "spi_busclk0"; | |
622 | pinctrl-names = "default"; | |
623 | pinctrl-0 = <&spi0_bus>; | |
624 | status = "disabled"; | |
625 | }; | |
b571abb3 | 626 | |
73a901d0 MP |
627 | spi_1: spi@13930000 { |
628 | compatible = "samsung,exynos4210-spi"; | |
629 | reg = <0x13930000 0x100>; | |
630 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
631 | dmas = <&pdma1 7>, <&pdma1 6>; | |
632 | dma-names = "tx", "rx"; | |
633 | #address-cells = <1>; | |
634 | #size-cells = <0>; | |
635 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; | |
636 | clock-names = "spi", "spi_busclk0"; | |
637 | pinctrl-names = "default"; | |
638 | pinctrl-0 = <&spi1_bus>; | |
639 | status = "disabled"; | |
640 | }; | |
b571abb3 | 641 | |
73a901d0 MP |
642 | spi_2: spi@13940000 { |
643 | compatible = "samsung,exynos4210-spi"; | |
644 | reg = <0x13940000 0x100>; | |
645 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
646 | dmas = <&pdma0 9>, <&pdma0 8>; | |
647 | dma-names = "tx", "rx"; | |
648 | #address-cells = <1>; | |
649 | #size-cells = <0>; | |
650 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; | |
651 | clock-names = "spi", "spi_busclk0"; | |
652 | pinctrl-names = "default"; | |
653 | pinctrl-0 = <&spi2_bus>; | |
654 | status = "disabled"; | |
655 | }; | |
cc4193ea | 656 | |
73a901d0 MP |
657 | pwm: pwm@139d0000 { |
658 | compatible = "samsung,exynos4210-pwm"; | |
9ca5a7ce | 659 | reg = <0x139d0000 0x1000>; |
73a901d0 MP |
660 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, |
661 | <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, | |
662 | <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
663 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
664 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
665 | clocks = <&clock CLK_PWM>; | |
666 | clock-names = "timers"; | |
667 | #pwm-cells = <3>; | |
668 | status = "disabled"; | |
669 | }; | |
b571abb3 | 670 | |
cfeb53ae | 671 | pdma0: dma-controller@12680000 { |
f91423e9 KK |
672 | compatible = "arm,pl330", "arm,primecell"; |
673 | reg = <0x12680000 0x1000>; | |
674 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
675 | clocks = <&clock CLK_PDMA0>; | |
676 | clock-names = "apb_pclk"; | |
677 | #dma-cells = <1>; | |
f91423e9 KK |
678 | }; |
679 | ||
cfeb53ae | 680 | pdma1: dma-controller@12690000 { |
f91423e9 KK |
681 | compatible = "arm,pl330", "arm,primecell"; |
682 | reg = <0x12690000 0x1000>; | |
683 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
684 | clocks = <&clock CLK_PDMA1>; | |
685 | clock-names = "apb_pclk"; | |
686 | #dma-cells = <1>; | |
f91423e9 KK |
687 | }; |
688 | ||
cfeb53ae | 689 | mdma1: dma-controller@12850000 { |
f91423e9 KK |
690 | compatible = "arm,pl330", "arm,primecell"; |
691 | reg = <0x12850000 0x1000>; | |
692 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
693 | clocks = <&clock CLK_MDMA>; | |
694 | clock-names = "apb_pclk"; | |
695 | #dma-cells = <1>; | |
f7e758af | 696 | }; |
768c3a56 | 697 | |
73a901d0 MP |
698 | fimd: fimd@11c00000 { |
699 | compatible = "samsung,exynos4210-fimd"; | |
700 | interrupt-parent = <&combiner>; | |
701 | reg = <0x11c00000 0x20000>; | |
702 | interrupt-names = "fifo", "vsync", "lcd_sys"; | |
703 | interrupts = <11 0>, <11 1>, <11 2>; | |
704 | clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; | |
705 | clock-names = "sclk_fimd", "fimd"; | |
706 | power-domains = <&pd_lcd0>; | |
707 | iommus = <&sysmmu_fimd0>; | |
708 | samsung,sysreg = <&sys_reg>; | |
709 | status = "disabled"; | |
710 | }; | |
30e0e476 | 711 | |
73a901d0 MP |
712 | tmu: tmu@100c0000 { |
713 | interrupt-parent = <&combiner>; | |
9ca5a7ce | 714 | reg = <0x100c0000 0x100>; |
73a901d0 MP |
715 | interrupts = <2 4>; |
716 | status = "disabled"; | |
c05b799e | 717 | #thermal-sensor-cells = <0>; |
73a901d0 | 718 | }; |
9843a223 | 719 | |
73a901d0 MP |
720 | jpeg_codec: jpeg-codec@11840000 { |
721 | compatible = "samsung,exynos4210-jpeg"; | |
722 | reg = <0x11840000 0x1000>; | |
723 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
724 | clocks = <&clock CLK_JPEG>; | |
725 | clock-names = "jpeg"; | |
726 | power-domains = <&pd_cam>; | |
727 | iommus = <&sysmmu_jpeg>; | |
728 | }; | |
f470b859 | 729 | |
73a901d0 MP |
730 | rotator: rotator@12810000 { |
731 | compatible = "samsung,exynos4210-rotator"; | |
732 | reg = <0x12810000 0x64>; | |
733 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
734 | clocks = <&clock CLK_ROTATOR>; | |
735 | clock-names = "rotator"; | |
736 | iommus = <&sysmmu_rotator>; | |
737 | }; | |
0c7e90b5 | 738 | |
73a901d0 MP |
739 | hdmi: hdmi@12d00000 { |
740 | compatible = "samsung,exynos4210-hdmi"; | |
9ca5a7ce | 741 | reg = <0x12d00000 0x70000>; |
73a901d0 MP |
742 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
743 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | |
744 | "sclk_hdmiphy", "mout_hdmi"; | |
745 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, | |
746 | <&clock CLK_SCLK_PIXEL>, | |
747 | <&clock CLK_SCLK_HDMIPHY>, | |
748 | <&clock CLK_MOUT_HDMI>; | |
749 | phy = <&hdmi_i2c_phy>; | |
750 | power-domains = <&pd_tv>; | |
751 | samsung,syscon-phandle = <&pmu_system_controller>; | |
752 | #sound-dai-cells = <0>; | |
753 | status = "disabled"; | |
754 | }; | |
c795c88d | 755 | |
73a901d0 MP |
756 | hdmicec: cec@100b0000 { |
757 | compatible = "samsung,s5p-cec"; | |
9ca5a7ce | 758 | reg = <0x100b0000 0x200>; |
73a901d0 MP |
759 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
760 | clocks = <&clock CLK_HDMI_CEC>; | |
761 | clock-names = "hdmicec"; | |
762 | samsung,syscon-phandle = <&pmu_system_controller>; | |
763 | hdmi-phandle = <&hdmi>; | |
764 | pinctrl-names = "default"; | |
765 | pinctrl-0 = <&hdmi_cec>; | |
766 | status = "disabled"; | |
767 | }; | |
ed80d4ca | 768 | |
73a901d0 MP |
769 | mixer: mixer@12c10000 { |
770 | compatible = "samsung,exynos4210-mixer"; | |
771 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
9ca5a7ce | 772 | reg = <0x12c10000 0x2100>, <0x12c00000 0x300>; |
73a901d0 MP |
773 | power-domains = <&pd_tv>; |
774 | iommus = <&sysmmu_tv>; | |
775 | status = "disabled"; | |
776 | }; | |
ed80d4ca | 777 | |
1c6831b4 | 778 | ppmu_dmc0: ppmu@106a0000 { |
73a901d0 MP |
779 | compatible = "samsung,exynos-ppmu"; |
780 | reg = <0x106a0000 0x2000>; | |
781 | clocks = <&clock CLK_PPMUDMC0>; | |
782 | clock-names = "ppmu"; | |
783 | status = "disabled"; | |
784 | }; | |
30e0e476 | 785 | |
1c6831b4 | 786 | ppmu_dmc1: ppmu@106b0000 { |
73a901d0 MP |
787 | compatible = "samsung,exynos-ppmu"; |
788 | reg = <0x106b0000 0x2000>; | |
789 | clocks = <&clock CLK_PPMUDMC1>; | |
790 | clock-names = "ppmu"; | |
791 | status = "disabled"; | |
792 | }; | |
30e0e476 | 793 | |
1c6831b4 | 794 | ppmu_cpu: ppmu@106c0000 { |
73a901d0 MP |
795 | compatible = "samsung,exynos-ppmu"; |
796 | reg = <0x106c0000 0x2000>; | |
797 | clocks = <&clock CLK_PPMUCPU>; | |
798 | clock-names = "ppmu"; | |
799 | status = "disabled"; | |
800 | }; | |
30e0e476 | 801 | |
1c6831b4 | 802 | ppmu_rightbus: ppmu@112a0000 { |
73a901d0 MP |
803 | compatible = "samsung,exynos-ppmu"; |
804 | reg = <0x112a0000 0x2000>; | |
805 | clocks = <&clock CLK_PPMURIGHT>; | |
806 | clock-names = "ppmu"; | |
807 | status = "disabled"; | |
808 | }; | |
30e0e476 | 809 | |
1c6831b4 | 810 | ppmu_leftbus: ppmu@116a0000 { |
73a901d0 MP |
811 | compatible = "samsung,exynos-ppmu"; |
812 | reg = <0x116a0000 0x2000>; | |
813 | clocks = <&clock CLK_PPMULEFT>; | |
814 | clock-names = "ppmu"; | |
815 | status = "disabled"; | |
816 | }; | |
30e0e476 | 817 | |
1c6831b4 | 818 | ppmu_camif: ppmu@11ac0000 { |
73a901d0 MP |
819 | compatible = "samsung,exynos-ppmu"; |
820 | reg = <0x11ac0000 0x2000>; | |
821 | clocks = <&clock CLK_PPMUCAMIF>; | |
822 | clock-names = "ppmu"; | |
823 | status = "disabled"; | |
824 | }; | |
30e0e476 | 825 | |
1c6831b4 | 826 | ppmu_lcd0: ppmu@11e40000 { |
73a901d0 MP |
827 | compatible = "samsung,exynos-ppmu"; |
828 | reg = <0x11e40000 0x2000>; | |
829 | clocks = <&clock CLK_PPMULCD0>; | |
830 | clock-names = "ppmu"; | |
831 | status = "disabled"; | |
832 | }; | |
30e0e476 | 833 | |
1c6831b4 | 834 | ppmu_fsys: ppmu@12630000 { |
73a901d0 MP |
835 | compatible = "samsung,exynos-ppmu"; |
836 | reg = <0x12630000 0x2000>; | |
837 | status = "disabled"; | |
838 | }; | |
30e0e476 | 839 | |
1c6831b4 | 840 | ppmu_image: ppmu@12aa0000 { |
73a901d0 MP |
841 | compatible = "samsung,exynos-ppmu"; |
842 | reg = <0x12aa0000 0x2000>; | |
843 | clocks = <&clock CLK_PPMUIMAGE>; | |
844 | clock-names = "ppmu"; | |
845 | status = "disabled"; | |
846 | }; | |
30e0e476 | 847 | |
1c6831b4 | 848 | ppmu_tv: ppmu@12e40000 { |
73a901d0 MP |
849 | compatible = "samsung,exynos-ppmu"; |
850 | reg = <0x12e40000 0x2000>; | |
851 | clocks = <&clock CLK_PPMUTV>; | |
852 | clock-names = "ppmu"; | |
853 | status = "disabled"; | |
854 | }; | |
30e0e476 | 855 | |
1c6831b4 | 856 | ppmu_g3d: ppmu@13220000 { |
73a901d0 MP |
857 | compatible = "samsung,exynos-ppmu"; |
858 | reg = <0x13220000 0x2000>; | |
859 | clocks = <&clock CLK_PPMUG3D>; | |
860 | clock-names = "ppmu"; | |
861 | status = "disabled"; | |
862 | }; | |
30e0e476 | 863 | |
1c6831b4 | 864 | ppmu_mfc_left: ppmu@13660000 { |
73a901d0 MP |
865 | compatible = "samsung,exynos-ppmu"; |
866 | reg = <0x13660000 0x2000>; | |
867 | clocks = <&clock CLK_PPMUMFC_L>; | |
868 | clock-names = "ppmu"; | |
869 | status = "disabled"; | |
870 | }; | |
30e0e476 | 871 | |
1c6831b4 | 872 | ppmu_mfc_right: ppmu@13670000 { |
73a901d0 MP |
873 | compatible = "samsung,exynos-ppmu"; |
874 | reg = <0x13670000 0x2000>; | |
875 | clocks = <&clock CLK_PPMUMFC_R>; | |
876 | clock-names = "ppmu"; | |
877 | status = "disabled"; | |
878 | }; | |
71d3a9fb | 879 | |
73a901d0 MP |
880 | sysmmu_mfc_l: sysmmu@13620000 { |
881 | compatible = "samsung,exynos-sysmmu"; | |
882 | reg = <0x13620000 0x1000>; | |
883 | interrupt-parent = <&combiner>; | |
884 | interrupts = <5 5>; | |
885 | clock-names = "sysmmu", "master"; | |
886 | clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; | |
887 | power-domains = <&pd_mfc>; | |
888 | #iommu-cells = <0>; | |
889 | }; | |
71d3a9fb | 890 | |
73a901d0 MP |
891 | sysmmu_mfc_r: sysmmu@13630000 { |
892 | compatible = "samsung,exynos-sysmmu"; | |
893 | reg = <0x13630000 0x1000>; | |
894 | interrupt-parent = <&combiner>; | |
895 | interrupts = <5 6>; | |
896 | clock-names = "sysmmu", "master"; | |
897 | clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; | |
898 | power-domains = <&pd_mfc>; | |
899 | #iommu-cells = <0>; | |
900 | }; | |
71d3a9fb | 901 | |
73a901d0 MP |
902 | sysmmu_tv: sysmmu@12e20000 { |
903 | compatible = "samsung,exynos-sysmmu"; | |
9ca5a7ce | 904 | reg = <0x12e20000 0x1000>; |
73a901d0 MP |
905 | interrupt-parent = <&combiner>; |
906 | interrupts = <5 4>; | |
907 | clock-names = "sysmmu", "master"; | |
908 | clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; | |
909 | power-domains = <&pd_tv>; | |
910 | #iommu-cells = <0>; | |
911 | }; | |
71d3a9fb | 912 | |
73a901d0 MP |
913 | sysmmu_fimc0: sysmmu@11a20000 { |
914 | compatible = "samsung,exynos-sysmmu"; | |
9ca5a7ce | 915 | reg = <0x11a20000 0x1000>; |
73a901d0 MP |
916 | interrupt-parent = <&combiner>; |
917 | interrupts = <4 2>; | |
918 | clock-names = "sysmmu", "master"; | |
919 | clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; | |
920 | power-domains = <&pd_cam>; | |
921 | #iommu-cells = <0>; | |
922 | }; | |
71d3a9fb | 923 | |
73a901d0 MP |
924 | sysmmu_fimc1: sysmmu@11a30000 { |
925 | compatible = "samsung,exynos-sysmmu"; | |
9ca5a7ce | 926 | reg = <0x11a30000 0x1000>; |
73a901d0 MP |
927 | interrupt-parent = <&combiner>; |
928 | interrupts = <4 3>; | |
929 | clock-names = "sysmmu", "master"; | |
930 | clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; | |
931 | power-domains = <&pd_cam>; | |
932 | #iommu-cells = <0>; | |
933 | }; | |
71d3a9fb | 934 | |
73a901d0 MP |
935 | sysmmu_fimc2: sysmmu@11a40000 { |
936 | compatible = "samsung,exynos-sysmmu"; | |
9ca5a7ce | 937 | reg = <0x11a40000 0x1000>; |
73a901d0 MP |
938 | interrupt-parent = <&combiner>; |
939 | interrupts = <4 4>; | |
940 | clock-names = "sysmmu", "master"; | |
941 | clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; | |
942 | power-domains = <&pd_cam>; | |
943 | #iommu-cells = <0>; | |
944 | }; | |
71d3a9fb | 945 | |
73a901d0 MP |
946 | sysmmu_fimc3: sysmmu@11a50000 { |
947 | compatible = "samsung,exynos-sysmmu"; | |
9ca5a7ce | 948 | reg = <0x11a50000 0x1000>; |
73a901d0 MP |
949 | interrupt-parent = <&combiner>; |
950 | interrupts = <4 5>; | |
951 | clock-names = "sysmmu", "master"; | |
952 | clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; | |
953 | power-domains = <&pd_cam>; | |
954 | #iommu-cells = <0>; | |
955 | }; | |
71d3a9fb | 956 | |
73a901d0 MP |
957 | sysmmu_jpeg: sysmmu@11a60000 { |
958 | compatible = "samsung,exynos-sysmmu"; | |
9ca5a7ce | 959 | reg = <0x11a60000 0x1000>; |
73a901d0 MP |
960 | interrupt-parent = <&combiner>; |
961 | interrupts = <4 6>; | |
962 | clock-names = "sysmmu", "master"; | |
963 | clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; | |
964 | power-domains = <&pd_cam>; | |
965 | #iommu-cells = <0>; | |
966 | }; | |
71d3a9fb | 967 | |
73a901d0 MP |
968 | sysmmu_rotator: sysmmu@12a30000 { |
969 | compatible = "samsung,exynos-sysmmu"; | |
9ca5a7ce | 970 | reg = <0x12a30000 0x1000>; |
73a901d0 MP |
971 | interrupt-parent = <&combiner>; |
972 | interrupts = <5 0>; | |
973 | clock-names = "sysmmu", "master"; | |
974 | clocks = <&clock CLK_SMMU_ROTATOR>, | |
975 | <&clock CLK_ROTATOR>; | |
976 | #iommu-cells = <0>; | |
977 | }; | |
71d3a9fb | 978 | |
73a901d0 MP |
979 | sysmmu_fimd0: sysmmu@11e20000 { |
980 | compatible = "samsung,exynos-sysmmu"; | |
9ca5a7ce | 981 | reg = <0x11e20000 0x1000>; |
73a901d0 MP |
982 | interrupt-parent = <&combiner>; |
983 | interrupts = <5 2>; | |
984 | clock-names = "sysmmu", "master"; | |
985 | clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; | |
986 | power-domains = <&pd_lcd0>; | |
987 | #iommu-cells = <0>; | |
988 | }; | |
a452977c | 989 | |
73a901d0 MP |
990 | sss: sss@10830000 { |
991 | compatible = "samsung,exynos4210-secss"; | |
992 | reg = <0x10830000 0x300>; | |
993 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
994 | clocks = <&clock CLK_SSS>; | |
995 | clock-names = "secss"; | |
996 | }; | |
6c5eb1db | 997 | |
73a901d0 MP |
998 | prng: rng@10830400 { |
999 | compatible = "samsung,exynos4-rng"; | |
1000 | reg = <0x10830400 0x200>; | |
1001 | clocks = <&clock CLK_SSS>; | |
1002 | clock-names = "secss"; | |
1003 | }; | |
a452977c | 1004 | }; |
b571abb3 | 1005 | }; |
a03e9dac KK |
1006 | |
1007 | #include "exynos-syscon-restart.dtsi" |