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cc4637f7 | 1 | // SPDX-License-Identifier: GPL-2.0 |
b571abb3 TF |
2 | /* |
3 | * Samsung's Exynos4 SoC series common device tree source | |
4 | * | |
5 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
6 | * http://www.samsung.com | |
7 | * Copyright (c) 2010-2011 Linaro Ltd. | |
8 | * www.linaro.org | |
9 | * | |
10 | * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular | |
11 | * SoCs from Exynos4 series can include this file and provide values for SoCs | |
12 | * specfic bindings. | |
13 | * | |
14 | * Note: This file does not include device nodes for all the controllers in | |
15 | * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional | |
16 | * nodes can be added to this file. | |
b571abb3 TF |
17 | */ |
18 | ||
1c75a78a | 19 | #include <dt-bindings/clock/exynos4.h> |
990a7bfd | 20 | #include <dt-bindings/clock/exynos-audss-clk.h> |
74e2c958 | 21 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
63aee4fa | 22 | #include <dt-bindings/interrupt-controller/irq.h> |
1462b137 | 23 | #include "exynos-syscon-restart.dtsi" |
b571abb3 TF |
24 | |
25 | / { | |
26 | interrupt-parent = <&gic>; | |
1354835a JMC |
27 | #address-cells = <1>; |
28 | #size-cells = <1>; | |
b571abb3 TF |
29 | |
30 | aliases { | |
31 | spi0 = &spi_0; | |
32 | spi1 = &spi_1; | |
33 | spi2 = &spi_2; | |
34db4990 DA |
34 | i2c0 = &i2c_0; |
35 | i2c1 = &i2c_1; | |
36 | i2c2 = &i2c_2; | |
37 | i2c3 = &i2c_3; | |
38 | i2c4 = &i2c_4; | |
39 | i2c5 = &i2c_5; | |
40 | i2c6 = &i2c_6; | |
41 | i2c7 = &i2c_7; | |
ed80d4ca | 42 | i2c8 = &i2c_8; |
d1b8a41d SN |
43 | csis0 = &csis_0; |
44 | csis1 = &csis_1; | |
45 | fimc0 = &fimc_0; | |
46 | fimc1 = &fimc_1; | |
47 | fimc2 = &fimc_2; | |
48 | fimc3 = &fimc_3; | |
1e64f48e TF |
49 | serial0 = &serial_0; |
50 | serial1 = &serial_1; | |
51 | serial2 = &serial_2; | |
52 | serial3 = &serial_3; | |
b571abb3 TF |
53 | }; |
54 | ||
73a901d0 MP |
55 | soc: soc { |
56 | compatible = "simple-bus"; | |
57 | #address-cells = <1>; | |
58 | #size-cells = <1>; | |
59 | ranges; | |
990a7bfd | 60 | |
73a901d0 MP |
61 | clock_audss: clock-controller@3810000 { |
62 | compatible = "samsung,exynos4210-audss-clock"; | |
63 | reg = <0x03810000 0x0C>; | |
64 | #clock-cells = <1>; | |
65 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, | |
66 | <&clock CLK_SCLK_AUDIO0>, | |
67 | <&clock CLK_SCLK_AUDIO0>; | |
68 | clock-names = "pll_ref", "pll_in", "sclk_audio", | |
69 | "sclk_pcm_in"; | |
70 | }; | |
096ee6ad | 71 | |
73a901d0 MP |
72 | i2s0: i2s@3830000 { |
73 | compatible = "samsung,s5pv210-i2s"; | |
74 | reg = <0x03830000 0x100>; | |
75 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
76 | <&clock_audss EXYNOS_DOUT_AUD_BUS>, | |
77 | <&clock_audss EXYNOS_SCLK_I2S>; | |
78 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
79 | #clock-cells = <1>; | |
80 | clock-output-names = "i2s_cdclk0"; | |
81 | dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; | |
82 | dma-names = "tx", "rx", "tx-sec"; | |
83 | samsung,idma-addr = <0x03000000>; | |
84 | #sound-dai-cells = <1>; | |
85 | status = "disabled"; | |
86 | }; | |
05a3589f | 87 | |
73a901d0 MP |
88 | chipid@10000000 { |
89 | compatible = "samsung,exynos4210-chipid"; | |
90 | reg = <0x10000000 0x100>; | |
91 | }; | |
df4400ac | 92 | |
73a901d0 MP |
93 | scu: snoop-control-unit@10500000 { |
94 | compatible = "arm,cortex-a9-scu"; | |
95 | reg = <0x10500000 0x2000>; | |
96 | }; | |
21b190d2 | 97 | |
73a901d0 MP |
98 | memory-controller@12570000 { |
99 | compatible = "samsung,exynos4210-srom"; | |
100 | reg = <0x12570000 0x14>; | |
101 | }; | |
91d88f03 | 102 | |
73a901d0 MP |
103 | mipi_phy: video-phy { |
104 | compatible = "samsung,s5pv210-mipi-video-phy"; | |
105 | #phy-cells = <1>; | |
106 | syscon = <&pmu_system_controller>; | |
107 | }; | |
91d88f03 | 108 | |
73a901d0 MP |
109 | pd_mfc: mfc-power-domain@10023c40 { |
110 | compatible = "samsung,exynos4210-pd"; | |
111 | reg = <0x10023C40 0x20>; | |
112 | #power-domain-cells = <0>; | |
113 | label = "MFC"; | |
114 | }; | |
91d88f03 | 115 | |
73a901d0 MP |
116 | pd_g3d: g3d-power-domain@10023c60 { |
117 | compatible = "samsung,exynos4210-pd"; | |
118 | reg = <0x10023C60 0x20>; | |
119 | #power-domain-cells = <0>; | |
120 | label = "G3D"; | |
121 | }; | |
91d88f03 | 122 | |
73a901d0 MP |
123 | pd_lcd0: lcd0-power-domain@10023c80 { |
124 | compatible = "samsung,exynos4210-pd"; | |
125 | reg = <0x10023C80 0x20>; | |
126 | #power-domain-cells = <0>; | |
127 | label = "LCD0"; | |
128 | }; | |
91d88f03 | 129 | |
73a901d0 MP |
130 | pd_tv: tv-power-domain@10023c20 { |
131 | compatible = "samsung,exynos4210-pd"; | |
132 | reg = <0x10023C20 0x20>; | |
133 | #power-domain-cells = <0>; | |
134 | power-domains = <&pd_lcd0>; | |
135 | label = "TV"; | |
136 | }; | |
b571abb3 | 137 | |
73a901d0 MP |
138 | pd_cam: cam-power-domain@10023c00 { |
139 | compatible = "samsung,exynos4210-pd"; | |
140 | reg = <0x10023C00 0x20>; | |
141 | #power-domain-cells = <0>; | |
142 | label = "CAM"; | |
143 | }; | |
10ea1f18 | 144 | |
73a901d0 MP |
145 | pd_gps: gps-power-domain@10023ce0 { |
146 | compatible = "samsung,exynos4210-pd"; | |
147 | reg = <0x10023CE0 0x20>; | |
148 | #power-domain-cells = <0>; | |
149 | label = "GPS"; | |
150 | }; | |
b571abb3 | 151 | |
73a901d0 MP |
152 | pd_gps_alive: gps-alive-power-domain@10023d00 { |
153 | compatible = "samsung,exynos4210-pd"; | |
154 | reg = <0x10023D00 0x20>; | |
155 | #power-domain-cells = <0>; | |
156 | label = "GPS alive"; | |
157 | }; | |
b571abb3 | 158 | |
73a901d0 MP |
159 | gic: interrupt-controller@10490000 { |
160 | compatible = "arm,cortex-a9-gic"; | |
161 | #interrupt-cells = <3>; | |
162 | interrupt-controller; | |
163 | reg = <0x10490000 0x10000>, <0x10480000 0x10000>; | |
164 | }; | |
6f4b82a3 | 165 | |
73a901d0 MP |
166 | combiner: interrupt-controller@10440000 { |
167 | compatible = "samsung,exynos4210-combiner"; | |
168 | #interrupt-cells = <2>; | |
169 | interrupt-controller; | |
170 | reg = <0x10440000 0x1000>; | |
171 | }; | |
a64b1b22 | 172 | |
73a901d0 MP |
173 | pmu: pmu { |
174 | compatible = "arm,cortex-a9-pmu"; | |
175 | interrupt-parent = <&combiner>; | |
176 | interrupts = <2 2>, <3 2>; | |
177 | }; | |
7b9613ac | 178 | |
73a901d0 MP |
179 | sys_reg: syscon@10010000 { |
180 | compatible = "samsung,exynos4-sysreg", "syscon"; | |
181 | reg = <0x10010000 0x400>; | |
182 | }; | |
8b7dd64c | 183 | |
73a901d0 MP |
184 | pmu_system_controller: system-controller@10020000 { |
185 | compatible = "samsung,exynos4210-pmu", "syscon"; | |
186 | reg = <0x10020000 0x4000>; | |
187 | interrupt-controller; | |
188 | #interrupt-cells = <3>; | |
189 | interrupt-parent = <&gic>; | |
190 | }; | |
d1b8a41d | 191 | |
73a901d0 MP |
192 | dsi_0: dsi@11c80000 { |
193 | compatible = "samsung,exynos4210-mipi-dsi"; | |
194 | reg = <0x11C80000 0x10000>; | |
195 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
196 | power-domains = <&pd_lcd0>; | |
197 | phys = <&mipi_phy 1>; | |
198 | phy-names = "dsim"; | |
199 | clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; | |
200 | clock-names = "bus_clk", "sclk_mipi"; | |
d1b8a41d | 201 | status = "disabled"; |
73a901d0 MP |
202 | #address-cells = <1>; |
203 | #size-cells = <0>; | |
d1b8a41d SN |
204 | }; |
205 | ||
73a901d0 MP |
206 | camera: camera { |
207 | compatible = "samsung,fimc", "simple-bus"; | |
d1b8a41d | 208 | status = "disabled"; |
73a901d0 MP |
209 | #address-cells = <1>; |
210 | #size-cells = <1>; | |
211 | #clock-cells = <1>; | |
212 | clock-output-names = "cam_a_clkout", "cam_b_clkout"; | |
213 | ranges; | |
214 | ||
215 | fimc_0: fimc@11800000 { | |
216 | compatible = "samsung,exynos4210-fimc"; | |
217 | reg = <0x11800000 0x1000>; | |
218 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
219 | clocks = <&clock CLK_FIMC0>, | |
220 | <&clock CLK_SCLK_FIMC0>; | |
221 | clock-names = "fimc", "sclk_fimc"; | |
222 | power-domains = <&pd_cam>; | |
223 | samsung,sysreg = <&sys_reg>; | |
224 | iommus = <&sysmmu_fimc0>; | |
225 | status = "disabled"; | |
226 | }; | |
227 | ||
228 | fimc_1: fimc@11810000 { | |
229 | compatible = "samsung,exynos4210-fimc"; | |
230 | reg = <0x11810000 0x1000>; | |
231 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
232 | clocks = <&clock CLK_FIMC1>, | |
233 | <&clock CLK_SCLK_FIMC1>; | |
234 | clock-names = "fimc", "sclk_fimc"; | |
235 | power-domains = <&pd_cam>; | |
236 | samsung,sysreg = <&sys_reg>; | |
237 | iommus = <&sysmmu_fimc1>; | |
238 | status = "disabled"; | |
239 | }; | |
240 | ||
241 | fimc_2: fimc@11820000 { | |
242 | compatible = "samsung,exynos4210-fimc"; | |
243 | reg = <0x11820000 0x1000>; | |
244 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
245 | clocks = <&clock CLK_FIMC2>, | |
246 | <&clock CLK_SCLK_FIMC2>; | |
247 | clock-names = "fimc", "sclk_fimc"; | |
248 | power-domains = <&pd_cam>; | |
249 | samsung,sysreg = <&sys_reg>; | |
250 | iommus = <&sysmmu_fimc2>; | |
251 | status = "disabled"; | |
252 | }; | |
253 | ||
254 | fimc_3: fimc@11830000 { | |
255 | compatible = "samsung,exynos4210-fimc"; | |
256 | reg = <0x11830000 0x1000>; | |
257 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
258 | clocks = <&clock CLK_FIMC3>, | |
259 | <&clock CLK_SCLK_FIMC3>; | |
260 | clock-names = "fimc", "sclk_fimc"; | |
261 | power-domains = <&pd_cam>; | |
262 | samsung,sysreg = <&sys_reg>; | |
263 | iommus = <&sysmmu_fimc3>; | |
264 | status = "disabled"; | |
265 | }; | |
266 | ||
267 | csis_0: csis@11880000 { | |
268 | compatible = "samsung,exynos4210-csis"; | |
269 | reg = <0x11880000 0x4000>; | |
270 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
271 | clocks = <&clock CLK_CSIS0>, | |
272 | <&clock CLK_SCLK_CSIS0>; | |
273 | clock-names = "csis", "sclk_csis"; | |
274 | bus-width = <4>; | |
275 | power-domains = <&pd_cam>; | |
276 | phys = <&mipi_phy 0>; | |
277 | phy-names = "csis"; | |
278 | status = "disabled"; | |
279 | #address-cells = <1>; | |
280 | #size-cells = <0>; | |
281 | }; | |
282 | ||
283 | csis_1: csis@11890000 { | |
284 | compatible = "samsung,exynos4210-csis"; | |
285 | reg = <0x11890000 0x4000>; | |
286 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
287 | clocks = <&clock CLK_CSIS1>, | |
288 | <&clock CLK_SCLK_CSIS1>; | |
289 | clock-names = "csis", "sclk_csis"; | |
290 | bus-width = <2>; | |
291 | power-domains = <&pd_cam>; | |
292 | phys = <&mipi_phy 2>; | |
293 | phy-names = "csis"; | |
294 | status = "disabled"; | |
295 | #address-cells = <1>; | |
296 | #size-cells = <0>; | |
297 | }; | |
d1b8a41d SN |
298 | }; |
299 | ||
73a901d0 MP |
300 | rtc: rtc@10070000 { |
301 | compatible = "samsung,s3c6410-rtc"; | |
302 | reg = <0x10070000 0x100>; | |
303 | interrupt-parent = <&pmu_system_controller>; | |
304 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
305 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
306 | clocks = <&clock CLK_RTC>; | |
307 | clock-names = "rtc"; | |
d1b8a41d SN |
308 | status = "disabled"; |
309 | }; | |
310 | ||
73a901d0 MP |
311 | keypad: keypad@100a0000 { |
312 | compatible = "samsung,s5pv210-keypad"; | |
313 | reg = <0x100A0000 0x100>; | |
314 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
315 | clocks = <&clock CLK_KEYIF>; | |
316 | clock-names = "keypad"; | |
d1b8a41d SN |
317 | status = "disabled"; |
318 | }; | |
319 | ||
73a901d0 MP |
320 | sdhci_0: sdhci@12510000 { |
321 | compatible = "samsung,exynos4210-sdhci"; | |
322 | reg = <0x12510000 0x100>; | |
323 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
324 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; | |
325 | clock-names = "hsmmc", "mmc_busclk.2"; | |
d1b8a41d | 326 | status = "disabled"; |
d1b8a41d SN |
327 | }; |
328 | ||
73a901d0 MP |
329 | sdhci_1: sdhci@12520000 { |
330 | compatible = "samsung,exynos4210-sdhci"; | |
331 | reg = <0x12520000 0x100>; | |
332 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
333 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; | |
334 | clock-names = "hsmmc", "mmc_busclk.2"; | |
d1b8a41d | 335 | status = "disabled"; |
d1b8a41d | 336 | }; |
b571abb3 | 337 | |
73a901d0 MP |
338 | sdhci_2: sdhci@12530000 { |
339 | compatible = "samsung,exynos4210-sdhci"; | |
340 | reg = <0x12530000 0x100>; | |
341 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
342 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; | |
343 | clock-names = "hsmmc", "mmc_busclk.2"; | |
344 | status = "disabled"; | |
345 | }; | |
26bbd41f | 346 | |
73a901d0 MP |
347 | sdhci_3: sdhci@12540000 { |
348 | compatible = "samsung,exynos4210-sdhci"; | |
349 | reg = <0x12540000 0x100>; | |
350 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
351 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; | |
352 | clock-names = "hsmmc", "mmc_busclk.2"; | |
353 | status = "disabled"; | |
354 | }; | |
ef14d94c | 355 | |
73a901d0 MP |
356 | exynos_usbphy: exynos-usbphy@125b0000 { |
357 | compatible = "samsung,exynos4210-usb2-phy"; | |
358 | reg = <0x125B0000 0x100>; | |
359 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
360 | clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; | |
361 | clock-names = "phy", "ref"; | |
362 | #phy-cells = <1>; | |
363 | status = "disabled"; | |
364 | }; | |
b571abb3 | 365 | |
73a901d0 MP |
366 | hsotg: hsotg@12480000 { |
367 | compatible = "samsung,s3c6400-hsotg"; | |
368 | reg = <0x12480000 0x20000>; | |
369 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
370 | clocks = <&clock CLK_USB_DEVICE>; | |
371 | clock-names = "otg"; | |
372 | phys = <&exynos_usbphy 0>; | |
373 | phy-names = "usb2-phy"; | |
dfaf06ba | 374 | status = "disabled"; |
366126d5 | 375 | }; |
73a901d0 MP |
376 | |
377 | ehci: ehci@12580000 { | |
378 | compatible = "samsung,exynos4210-ehci"; | |
379 | reg = <0x12580000 0x100>; | |
380 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
381 | clocks = <&clock CLK_USB_HOST>; | |
382 | clock-names = "usbhost"; | |
dfaf06ba | 383 | status = "disabled"; |
73a901d0 MP |
384 | #address-cells = <1>; |
385 | #size-cells = <0>; | |
386 | port@0 { | |
387 | reg = <0>; | |
388 | phys = <&exynos_usbphy 1>; | |
389 | status = "disabled"; | |
390 | }; | |
391 | port@1 { | |
392 | reg = <1>; | |
393 | phys = <&exynos_usbphy 2>; | |
394 | status = "disabled"; | |
395 | }; | |
396 | port@2 { | |
397 | reg = <2>; | |
398 | phys = <&exynos_usbphy 3>; | |
399 | status = "disabled"; | |
400 | }; | |
366126d5 | 401 | }; |
73a901d0 MP |
402 | |
403 | ohci: ohci@12590000 { | |
404 | compatible = "samsung,exynos4210-ohci"; | |
405 | reg = <0x12590000 0x100>; | |
406 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
407 | clocks = <&clock CLK_USB_HOST>; | |
408 | clock-names = "usbhost"; | |
dfaf06ba | 409 | status = "disabled"; |
73a901d0 MP |
410 | #address-cells = <1>; |
411 | #size-cells = <0>; | |
412 | port@0 { | |
413 | reg = <0>; | |
414 | phys = <&exynos_usbphy 1>; | |
415 | status = "disabled"; | |
416 | }; | |
366126d5 | 417 | }; |
6f9d02a0 | 418 | |
73a901d0 MP |
419 | i2s1: i2s@13960000 { |
420 | compatible = "samsung,s3c6410-i2s"; | |
421 | reg = <0x13960000 0x100>; | |
422 | clocks = <&clock CLK_I2S1>; | |
423 | clock-names = "iis"; | |
424 | #clock-cells = <1>; | |
425 | clock-output-names = "i2s_cdclk1"; | |
426 | dmas = <&pdma1 12>, <&pdma1 11>; | |
427 | dma-names = "tx", "rx"; | |
428 | #sound-dai-cells = <1>; | |
dfaf06ba | 429 | status = "disabled"; |
366126d5 | 430 | }; |
6f9d02a0 | 431 | |
73a901d0 MP |
432 | i2s2: i2s@13970000 { |
433 | compatible = "samsung,s3c6410-i2s"; | |
434 | reg = <0x13970000 0x100>; | |
435 | clocks = <&clock CLK_I2S2>; | |
436 | clock-names = "iis"; | |
437 | #clock-cells = <1>; | |
438 | clock-output-names = "i2s_cdclk2"; | |
439 | dmas = <&pdma0 14>, <&pdma0 13>; | |
440 | dma-names = "tx", "rx"; | |
441 | #sound-dai-cells = <1>; | |
442 | status = "disabled"; | |
443 | }; | |
990a7bfd | 444 | |
73a901d0 MP |
445 | mfc: codec@13400000 { |
446 | compatible = "samsung,mfc-v5"; | |
447 | reg = <0x13400000 0x10000>; | |
448 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
449 | power-domains = <&pd_mfc>; | |
450 | clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; | |
451 | clock-names = "mfc", "sclk_mfc"; | |
452 | iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; | |
453 | iommu-names = "left", "right"; | |
454 | }; | |
990a7bfd | 455 | |
73a901d0 MP |
456 | serial_0: serial@13800000 { |
457 | compatible = "samsung,exynos4210-uart"; | |
458 | reg = <0x13800000 0x100>; | |
459 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
460 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | |
461 | clock-names = "uart", "clk_uart_baud0"; | |
462 | dmas = <&pdma0 15>, <&pdma0 16>; | |
463 | dma-names = "rx", "tx"; | |
464 | status = "disabled"; | |
465 | }; | |
20901f74 | 466 | |
73a901d0 MP |
467 | serial_1: serial@13810000 { |
468 | compatible = "samsung,exynos4210-uart"; | |
469 | reg = <0x13810000 0x100>; | |
470 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
471 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | |
472 | clock-names = "uart", "clk_uart_baud0"; | |
473 | dmas = <&pdma1 15>, <&pdma1 16>; | |
474 | dma-names = "rx", "tx"; | |
475 | status = "disabled"; | |
476 | }; | |
b571abb3 | 477 | |
73a901d0 MP |
478 | serial_2: serial@13820000 { |
479 | compatible = "samsung,exynos4210-uart"; | |
480 | reg = <0x13820000 0x100>; | |
481 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
482 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | |
483 | clock-names = "uart", "clk_uart_baud0"; | |
484 | dmas = <&pdma0 17>, <&pdma0 18>; | |
485 | dma-names = "rx", "tx"; | |
486 | status = "disabled"; | |
487 | }; | |
b571abb3 | 488 | |
73a901d0 MP |
489 | serial_3: serial@13830000 { |
490 | compatible = "samsung,exynos4210-uart"; | |
491 | reg = <0x13830000 0x100>; | |
492 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
493 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; | |
494 | clock-names = "uart", "clk_uart_baud0"; | |
495 | dmas = <&pdma1 17>, <&pdma1 18>; | |
496 | dma-names = "rx", "tx"; | |
497 | status = "disabled"; | |
498 | }; | |
b571abb3 | 499 | |
73a901d0 MP |
500 | i2c_0: i2c@13860000 { |
501 | #address-cells = <1>; | |
502 | #size-cells = <0>; | |
503 | compatible = "samsung,s3c2440-i2c"; | |
504 | reg = <0x13860000 0x100>; | |
505 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
506 | clocks = <&clock CLK_I2C0>; | |
507 | clock-names = "i2c"; | |
508 | pinctrl-names = "default"; | |
509 | pinctrl-0 = <&i2c0_bus>; | |
510 | status = "disabled"; | |
511 | }; | |
b571abb3 | 512 | |
73a901d0 MP |
513 | i2c_1: i2c@13870000 { |
514 | #address-cells = <1>; | |
515 | #size-cells = <0>; | |
516 | compatible = "samsung,s3c2440-i2c"; | |
517 | reg = <0x13870000 0x100>; | |
518 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
519 | clocks = <&clock CLK_I2C1>; | |
520 | clock-names = "i2c"; | |
521 | pinctrl-names = "default"; | |
522 | pinctrl-0 = <&i2c1_bus>; | |
523 | status = "disabled"; | |
524 | }; | |
b571abb3 | 525 | |
73a901d0 MP |
526 | i2c_2: i2c@13880000 { |
527 | #address-cells = <1>; | |
528 | #size-cells = <0>; | |
529 | compatible = "samsung,s3c2440-i2c"; | |
530 | reg = <0x13880000 0x100>; | |
531 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
532 | clocks = <&clock CLK_I2C2>; | |
533 | clock-names = "i2c"; | |
534 | pinctrl-names = "default"; | |
535 | pinctrl-0 = <&i2c2_bus>; | |
536 | status = "disabled"; | |
537 | }; | |
b571abb3 | 538 | |
73a901d0 MP |
539 | i2c_3: i2c@13890000 { |
540 | #address-cells = <1>; | |
541 | #size-cells = <0>; | |
542 | compatible = "samsung,s3c2440-i2c"; | |
543 | reg = <0x13890000 0x100>; | |
544 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
545 | clocks = <&clock CLK_I2C3>; | |
546 | clock-names = "i2c"; | |
547 | pinctrl-names = "default"; | |
548 | pinctrl-0 = <&i2c3_bus>; | |
549 | status = "disabled"; | |
550 | }; | |
b571abb3 | 551 | |
73a901d0 MP |
552 | i2c_4: i2c@138a0000 { |
553 | #address-cells = <1>; | |
554 | #size-cells = <0>; | |
555 | compatible = "samsung,s3c2440-i2c"; | |
556 | reg = <0x138A0000 0x100>; | |
557 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
558 | clocks = <&clock CLK_I2C4>; | |
559 | clock-names = "i2c"; | |
560 | pinctrl-names = "default"; | |
561 | pinctrl-0 = <&i2c4_bus>; | |
562 | status = "disabled"; | |
563 | }; | |
b571abb3 | 564 | |
73a901d0 MP |
565 | i2c_5: i2c@138b0000 { |
566 | #address-cells = <1>; | |
567 | #size-cells = <0>; | |
568 | compatible = "samsung,s3c2440-i2c"; | |
569 | reg = <0x138B0000 0x100>; | |
570 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
571 | clocks = <&clock CLK_I2C5>; | |
572 | clock-names = "i2c"; | |
573 | pinctrl-names = "default"; | |
574 | pinctrl-0 = <&i2c5_bus>; | |
575 | status = "disabled"; | |
576 | }; | |
b571abb3 | 577 | |
73a901d0 MP |
578 | i2c_6: i2c@138c0000 { |
579 | #address-cells = <1>; | |
580 | #size-cells = <0>; | |
581 | compatible = "samsung,s3c2440-i2c"; | |
582 | reg = <0x138C0000 0x100>; | |
583 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
584 | clocks = <&clock CLK_I2C6>; | |
585 | clock-names = "i2c"; | |
586 | pinctrl-names = "default"; | |
587 | pinctrl-0 = <&i2c6_bus>; | |
588 | status = "disabled"; | |
589 | }; | |
b571abb3 | 590 | |
73a901d0 MP |
591 | i2c_7: i2c@138d0000 { |
592 | #address-cells = <1>; | |
593 | #size-cells = <0>; | |
594 | compatible = "samsung,s3c2440-i2c"; | |
595 | reg = <0x138D0000 0x100>; | |
596 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
597 | clocks = <&clock CLK_I2C7>; | |
598 | clock-names = "i2c"; | |
599 | pinctrl-names = "default"; | |
600 | pinctrl-0 = <&i2c7_bus>; | |
601 | status = "disabled"; | |
602 | }; | |
b571abb3 | 603 | |
73a901d0 MP |
604 | i2c_8: i2c@138e0000 { |
605 | #address-cells = <1>; | |
606 | #size-cells = <0>; | |
607 | compatible = "samsung,s3c2440-hdmiphy-i2c"; | |
608 | reg = <0x138E0000 0x100>; | |
609 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
610 | clocks = <&clock CLK_I2C_HDMI>; | |
611 | clock-names = "i2c"; | |
612 | status = "disabled"; | |
b571abb3 | 613 | |
73a901d0 MP |
614 | hdmi_i2c_phy: hdmiphy@38 { |
615 | compatible = "exynos4210-hdmiphy"; | |
616 | reg = <0x38>; | |
617 | }; | |
ed80d4ca | 618 | }; |
ed80d4ca | 619 | |
73a901d0 MP |
620 | spi_0: spi@13920000 { |
621 | compatible = "samsung,exynos4210-spi"; | |
622 | reg = <0x13920000 0x100>; | |
623 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
624 | dmas = <&pdma0 7>, <&pdma0 6>; | |
625 | dma-names = "tx", "rx"; | |
626 | #address-cells = <1>; | |
627 | #size-cells = <0>; | |
628 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; | |
629 | clock-names = "spi", "spi_busclk0"; | |
630 | pinctrl-names = "default"; | |
631 | pinctrl-0 = <&spi0_bus>; | |
632 | status = "disabled"; | |
633 | }; | |
b571abb3 | 634 | |
73a901d0 MP |
635 | spi_1: spi@13930000 { |
636 | compatible = "samsung,exynos4210-spi"; | |
637 | reg = <0x13930000 0x100>; | |
638 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
639 | dmas = <&pdma1 7>, <&pdma1 6>; | |
640 | dma-names = "tx", "rx"; | |
641 | #address-cells = <1>; | |
642 | #size-cells = <0>; | |
643 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; | |
644 | clock-names = "spi", "spi_busclk0"; | |
645 | pinctrl-names = "default"; | |
646 | pinctrl-0 = <&spi1_bus>; | |
647 | status = "disabled"; | |
648 | }; | |
b571abb3 | 649 | |
73a901d0 MP |
650 | spi_2: spi@13940000 { |
651 | compatible = "samsung,exynos4210-spi"; | |
652 | reg = <0x13940000 0x100>; | |
653 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
654 | dmas = <&pdma0 9>, <&pdma0 8>; | |
655 | dma-names = "tx", "rx"; | |
656 | #address-cells = <1>; | |
657 | #size-cells = <0>; | |
658 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; | |
659 | clock-names = "spi", "spi_busclk0"; | |
660 | pinctrl-names = "default"; | |
661 | pinctrl-0 = <&spi2_bus>; | |
662 | status = "disabled"; | |
663 | }; | |
cc4193ea | 664 | |
73a901d0 MP |
665 | pwm: pwm@139d0000 { |
666 | compatible = "samsung,exynos4210-pwm"; | |
667 | reg = <0x139D0000 0x1000>; | |
668 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, | |
669 | <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, | |
670 | <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
671 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
672 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
673 | clocks = <&clock CLK_PWM>; | |
674 | clock-names = "timers"; | |
675 | #pwm-cells = <3>; | |
676 | status = "disabled"; | |
677 | }; | |
b571abb3 | 678 | |
73a901d0 MP |
679 | amba { |
680 | #address-cells = <1>; | |
681 | #size-cells = <1>; | |
682 | compatible = "simple-bus"; | |
683 | interrupt-parent = <&gic>; | |
684 | ranges; | |
685 | ||
686 | pdma0: pdma@12680000 { | |
687 | compatible = "arm,pl330", "arm,primecell"; | |
688 | reg = <0x12680000 0x1000>; | |
689 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
690 | clocks = <&clock CLK_PDMA0>; | |
691 | clock-names = "apb_pclk"; | |
692 | #dma-cells = <1>; | |
693 | #dma-channels = <8>; | |
694 | #dma-requests = <32>; | |
695 | }; | |
696 | ||
697 | pdma1: pdma@12690000 { | |
698 | compatible = "arm,pl330", "arm,primecell"; | |
699 | reg = <0x12690000 0x1000>; | |
700 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
701 | clocks = <&clock CLK_PDMA1>; | |
702 | clock-names = "apb_pclk"; | |
703 | #dma-cells = <1>; | |
704 | #dma-channels = <8>; | |
705 | #dma-requests = <32>; | |
706 | }; | |
707 | ||
708 | mdma1: mdma@12850000 { | |
709 | compatible = "arm,pl330", "arm,primecell"; | |
710 | reg = <0x12850000 0x1000>; | |
711 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
712 | clocks = <&clock CLK_MDMA>; | |
713 | clock-names = "apb_pclk"; | |
714 | #dma-cells = <1>; | |
715 | #dma-channels = <8>; | |
716 | #dma-requests = <1>; | |
717 | }; | |
f7e758af | 718 | }; |
768c3a56 | 719 | |
73a901d0 MP |
720 | fimd: fimd@11c00000 { |
721 | compatible = "samsung,exynos4210-fimd"; | |
722 | interrupt-parent = <&combiner>; | |
723 | reg = <0x11c00000 0x20000>; | |
724 | interrupt-names = "fifo", "vsync", "lcd_sys"; | |
725 | interrupts = <11 0>, <11 1>, <11 2>; | |
726 | clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; | |
727 | clock-names = "sclk_fimd", "fimd"; | |
728 | power-domains = <&pd_lcd0>; | |
729 | iommus = <&sysmmu_fimd0>; | |
730 | samsung,sysreg = <&sys_reg>; | |
731 | status = "disabled"; | |
732 | }; | |
30e0e476 | 733 | |
73a901d0 MP |
734 | tmu: tmu@100c0000 { |
735 | interrupt-parent = <&combiner>; | |
736 | reg = <0x100C0000 0x100>; | |
737 | interrupts = <2 4>; | |
738 | status = "disabled"; | |
739 | #include "exynos4412-tmu-sensor-conf.dtsi" | |
740 | }; | |
9843a223 | 741 | |
73a901d0 MP |
742 | jpeg_codec: jpeg-codec@11840000 { |
743 | compatible = "samsung,exynos4210-jpeg"; | |
744 | reg = <0x11840000 0x1000>; | |
745 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
746 | clocks = <&clock CLK_JPEG>; | |
747 | clock-names = "jpeg"; | |
748 | power-domains = <&pd_cam>; | |
749 | iommus = <&sysmmu_jpeg>; | |
750 | }; | |
f470b859 | 751 | |
73a901d0 MP |
752 | rotator: rotator@12810000 { |
753 | compatible = "samsung,exynos4210-rotator"; | |
754 | reg = <0x12810000 0x64>; | |
755 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
756 | clocks = <&clock CLK_ROTATOR>; | |
757 | clock-names = "rotator"; | |
758 | iommus = <&sysmmu_rotator>; | |
759 | }; | |
0c7e90b5 | 760 | |
73a901d0 MP |
761 | hdmi: hdmi@12d00000 { |
762 | compatible = "samsung,exynos4210-hdmi"; | |
763 | reg = <0x12D00000 0x70000>; | |
764 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | |
765 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | |
766 | "sclk_hdmiphy", "mout_hdmi"; | |
767 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, | |
768 | <&clock CLK_SCLK_PIXEL>, | |
769 | <&clock CLK_SCLK_HDMIPHY>, | |
770 | <&clock CLK_MOUT_HDMI>; | |
771 | phy = <&hdmi_i2c_phy>; | |
772 | power-domains = <&pd_tv>; | |
773 | samsung,syscon-phandle = <&pmu_system_controller>; | |
774 | #sound-dai-cells = <0>; | |
775 | status = "disabled"; | |
776 | }; | |
c795c88d | 777 | |
73a901d0 MP |
778 | hdmicec: cec@100b0000 { |
779 | compatible = "samsung,s5p-cec"; | |
780 | reg = <0x100B0000 0x200>; | |
781 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
782 | clocks = <&clock CLK_HDMI_CEC>; | |
783 | clock-names = "hdmicec"; | |
784 | samsung,syscon-phandle = <&pmu_system_controller>; | |
785 | hdmi-phandle = <&hdmi>; | |
786 | pinctrl-names = "default"; | |
787 | pinctrl-0 = <&hdmi_cec>; | |
788 | status = "disabled"; | |
789 | }; | |
ed80d4ca | 790 | |
73a901d0 MP |
791 | mixer: mixer@12c10000 { |
792 | compatible = "samsung,exynos4210-mixer"; | |
793 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
794 | reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; | |
795 | power-domains = <&pd_tv>; | |
796 | iommus = <&sysmmu_tv>; | |
797 | status = "disabled"; | |
798 | }; | |
ed80d4ca | 799 | |
73a901d0 MP |
800 | ppmu_dmc0: ppmu_dmc0@106a0000 { |
801 | compatible = "samsung,exynos-ppmu"; | |
802 | reg = <0x106a0000 0x2000>; | |
803 | clocks = <&clock CLK_PPMUDMC0>; | |
804 | clock-names = "ppmu"; | |
805 | status = "disabled"; | |
806 | }; | |
30e0e476 | 807 | |
73a901d0 MP |
808 | ppmu_dmc1: ppmu_dmc1@106b0000 { |
809 | compatible = "samsung,exynos-ppmu"; | |
810 | reg = <0x106b0000 0x2000>; | |
811 | clocks = <&clock CLK_PPMUDMC1>; | |
812 | clock-names = "ppmu"; | |
813 | status = "disabled"; | |
814 | }; | |
30e0e476 | 815 | |
73a901d0 MP |
816 | ppmu_cpu: ppmu_cpu@106c0000 { |
817 | compatible = "samsung,exynos-ppmu"; | |
818 | reg = <0x106c0000 0x2000>; | |
819 | clocks = <&clock CLK_PPMUCPU>; | |
820 | clock-names = "ppmu"; | |
821 | status = "disabled"; | |
822 | }; | |
30e0e476 | 823 | |
73a901d0 MP |
824 | ppmu_rightbus: ppmu_rightbus@112a0000 { |
825 | compatible = "samsung,exynos-ppmu"; | |
826 | reg = <0x112a0000 0x2000>; | |
827 | clocks = <&clock CLK_PPMURIGHT>; | |
828 | clock-names = "ppmu"; | |
829 | status = "disabled"; | |
830 | }; | |
30e0e476 | 831 | |
73a901d0 MP |
832 | ppmu_leftbus: ppmu_leftbus0@116a0000 { |
833 | compatible = "samsung,exynos-ppmu"; | |
834 | reg = <0x116a0000 0x2000>; | |
835 | clocks = <&clock CLK_PPMULEFT>; | |
836 | clock-names = "ppmu"; | |
837 | status = "disabled"; | |
838 | }; | |
30e0e476 | 839 | |
73a901d0 MP |
840 | ppmu_camif: ppmu_camif@11ac0000 { |
841 | compatible = "samsung,exynos-ppmu"; | |
842 | reg = <0x11ac0000 0x2000>; | |
843 | clocks = <&clock CLK_PPMUCAMIF>; | |
844 | clock-names = "ppmu"; | |
845 | status = "disabled"; | |
846 | }; | |
30e0e476 | 847 | |
73a901d0 MP |
848 | ppmu_lcd0: ppmu_lcd0@11e40000 { |
849 | compatible = "samsung,exynos-ppmu"; | |
850 | reg = <0x11e40000 0x2000>; | |
851 | clocks = <&clock CLK_PPMULCD0>; | |
852 | clock-names = "ppmu"; | |
853 | status = "disabled"; | |
854 | }; | |
30e0e476 | 855 | |
73a901d0 MP |
856 | ppmu_fsys: ppmu_g3d@12630000 { |
857 | compatible = "samsung,exynos-ppmu"; | |
858 | reg = <0x12630000 0x2000>; | |
859 | status = "disabled"; | |
860 | }; | |
30e0e476 | 861 | |
73a901d0 MP |
862 | ppmu_image: ppmu_image@12aa0000 { |
863 | compatible = "samsung,exynos-ppmu"; | |
864 | reg = <0x12aa0000 0x2000>; | |
865 | clocks = <&clock CLK_PPMUIMAGE>; | |
866 | clock-names = "ppmu"; | |
867 | status = "disabled"; | |
868 | }; | |
30e0e476 | 869 | |
73a901d0 MP |
870 | ppmu_tv: ppmu_tv@12e40000 { |
871 | compatible = "samsung,exynos-ppmu"; | |
872 | reg = <0x12e40000 0x2000>; | |
873 | clocks = <&clock CLK_PPMUTV>; | |
874 | clock-names = "ppmu"; | |
875 | status = "disabled"; | |
876 | }; | |
30e0e476 | 877 | |
73a901d0 MP |
878 | ppmu_g3d: ppmu_g3d@13220000 { |
879 | compatible = "samsung,exynos-ppmu"; | |
880 | reg = <0x13220000 0x2000>; | |
881 | clocks = <&clock CLK_PPMUG3D>; | |
882 | clock-names = "ppmu"; | |
883 | status = "disabled"; | |
884 | }; | |
30e0e476 | 885 | |
73a901d0 MP |
886 | ppmu_mfc_left: ppmu_mfc_left@13660000 { |
887 | compatible = "samsung,exynos-ppmu"; | |
888 | reg = <0x13660000 0x2000>; | |
889 | clocks = <&clock CLK_PPMUMFC_L>; | |
890 | clock-names = "ppmu"; | |
891 | status = "disabled"; | |
892 | }; | |
30e0e476 | 893 | |
73a901d0 MP |
894 | ppmu_mfc_right: ppmu_mfc_right@13670000 { |
895 | compatible = "samsung,exynos-ppmu"; | |
896 | reg = <0x13670000 0x2000>; | |
897 | clocks = <&clock CLK_PPMUMFC_R>; | |
898 | clock-names = "ppmu"; | |
899 | status = "disabled"; | |
900 | }; | |
71d3a9fb | 901 | |
73a901d0 MP |
902 | sysmmu_mfc_l: sysmmu@13620000 { |
903 | compatible = "samsung,exynos-sysmmu"; | |
904 | reg = <0x13620000 0x1000>; | |
905 | interrupt-parent = <&combiner>; | |
906 | interrupts = <5 5>; | |
907 | clock-names = "sysmmu", "master"; | |
908 | clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; | |
909 | power-domains = <&pd_mfc>; | |
910 | #iommu-cells = <0>; | |
911 | }; | |
71d3a9fb | 912 | |
73a901d0 MP |
913 | sysmmu_mfc_r: sysmmu@13630000 { |
914 | compatible = "samsung,exynos-sysmmu"; | |
915 | reg = <0x13630000 0x1000>; | |
916 | interrupt-parent = <&combiner>; | |
917 | interrupts = <5 6>; | |
918 | clock-names = "sysmmu", "master"; | |
919 | clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; | |
920 | power-domains = <&pd_mfc>; | |
921 | #iommu-cells = <0>; | |
922 | }; | |
71d3a9fb | 923 | |
73a901d0 MP |
924 | sysmmu_tv: sysmmu@12e20000 { |
925 | compatible = "samsung,exynos-sysmmu"; | |
926 | reg = <0x12E20000 0x1000>; | |
927 | interrupt-parent = <&combiner>; | |
928 | interrupts = <5 4>; | |
929 | clock-names = "sysmmu", "master"; | |
930 | clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; | |
931 | power-domains = <&pd_tv>; | |
932 | #iommu-cells = <0>; | |
933 | }; | |
71d3a9fb | 934 | |
73a901d0 MP |
935 | sysmmu_fimc0: sysmmu@11a20000 { |
936 | compatible = "samsung,exynos-sysmmu"; | |
937 | reg = <0x11A20000 0x1000>; | |
938 | interrupt-parent = <&combiner>; | |
939 | interrupts = <4 2>; | |
940 | clock-names = "sysmmu", "master"; | |
941 | clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; | |
942 | power-domains = <&pd_cam>; | |
943 | #iommu-cells = <0>; | |
944 | }; | |
71d3a9fb | 945 | |
73a901d0 MP |
946 | sysmmu_fimc1: sysmmu@11a30000 { |
947 | compatible = "samsung,exynos-sysmmu"; | |
948 | reg = <0x11A30000 0x1000>; | |
949 | interrupt-parent = <&combiner>; | |
950 | interrupts = <4 3>; | |
951 | clock-names = "sysmmu", "master"; | |
952 | clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; | |
953 | power-domains = <&pd_cam>; | |
954 | #iommu-cells = <0>; | |
955 | }; | |
71d3a9fb | 956 | |
73a901d0 MP |
957 | sysmmu_fimc2: sysmmu@11a40000 { |
958 | compatible = "samsung,exynos-sysmmu"; | |
959 | reg = <0x11A40000 0x1000>; | |
960 | interrupt-parent = <&combiner>; | |
961 | interrupts = <4 4>; | |
962 | clock-names = "sysmmu", "master"; | |
963 | clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; | |
964 | power-domains = <&pd_cam>; | |
965 | #iommu-cells = <0>; | |
966 | }; | |
71d3a9fb | 967 | |
73a901d0 MP |
968 | sysmmu_fimc3: sysmmu@11a50000 { |
969 | compatible = "samsung,exynos-sysmmu"; | |
970 | reg = <0x11A50000 0x1000>; | |
971 | interrupt-parent = <&combiner>; | |
972 | interrupts = <4 5>; | |
973 | clock-names = "sysmmu", "master"; | |
974 | clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; | |
975 | power-domains = <&pd_cam>; | |
976 | #iommu-cells = <0>; | |
977 | }; | |
71d3a9fb | 978 | |
73a901d0 MP |
979 | sysmmu_jpeg: sysmmu@11a60000 { |
980 | compatible = "samsung,exynos-sysmmu"; | |
981 | reg = <0x11A60000 0x1000>; | |
982 | interrupt-parent = <&combiner>; | |
983 | interrupts = <4 6>; | |
984 | clock-names = "sysmmu", "master"; | |
985 | clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; | |
986 | power-domains = <&pd_cam>; | |
987 | #iommu-cells = <0>; | |
988 | }; | |
71d3a9fb | 989 | |
73a901d0 MP |
990 | sysmmu_rotator: sysmmu@12a30000 { |
991 | compatible = "samsung,exynos-sysmmu"; | |
992 | reg = <0x12A30000 0x1000>; | |
993 | interrupt-parent = <&combiner>; | |
994 | interrupts = <5 0>; | |
995 | clock-names = "sysmmu", "master"; | |
996 | clocks = <&clock CLK_SMMU_ROTATOR>, | |
997 | <&clock CLK_ROTATOR>; | |
998 | #iommu-cells = <0>; | |
999 | }; | |
71d3a9fb | 1000 | |
73a901d0 MP |
1001 | sysmmu_fimd0: sysmmu@11e20000 { |
1002 | compatible = "samsung,exynos-sysmmu"; | |
1003 | reg = <0x11E20000 0x1000>; | |
1004 | interrupt-parent = <&combiner>; | |
1005 | interrupts = <5 2>; | |
1006 | clock-names = "sysmmu", "master"; | |
1007 | clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; | |
1008 | power-domains = <&pd_lcd0>; | |
1009 | #iommu-cells = <0>; | |
1010 | }; | |
a452977c | 1011 | |
73a901d0 MP |
1012 | sss: sss@10830000 { |
1013 | compatible = "samsung,exynos4210-secss"; | |
1014 | reg = <0x10830000 0x300>; | |
1015 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
1016 | clocks = <&clock CLK_SSS>; | |
1017 | clock-names = "secss"; | |
1018 | }; | |
6c5eb1db | 1019 | |
73a901d0 MP |
1020 | prng: rng@10830400 { |
1021 | compatible = "samsung,exynos4-rng"; | |
1022 | reg = <0x10830400 0x200>; | |
1023 | clocks = <&clock CLK_SSS>; | |
1024 | clock-names = "secss"; | |
1025 | }; | |
a452977c | 1026 | }; |
b571abb3 | 1027 | }; |