Commit | Line | Data |
---|---|---|
ee6c7507 TK |
1 | /* |
2 | * Device Tree Source for DRA7xx clock data | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | &cm_core_aon_clocks { | |
11 | atl_clkin0_ck: atl_clkin0_ck { | |
12 | #clock-cells = <0>; | |
2ca0945f PU |
13 | compatible = "ti,dra7-atl-clock"; |
14 | clocks = <&atl_gfclk_mux>; | |
ee6c7507 TK |
15 | }; |
16 | ||
17 | atl_clkin1_ck: atl_clkin1_ck { | |
18 | #clock-cells = <0>; | |
2ca0945f PU |
19 | compatible = "ti,dra7-atl-clock"; |
20 | clocks = <&atl_gfclk_mux>; | |
ee6c7507 TK |
21 | }; |
22 | ||
23 | atl_clkin2_ck: atl_clkin2_ck { | |
24 | #clock-cells = <0>; | |
2ca0945f PU |
25 | compatible = "ti,dra7-atl-clock"; |
26 | clocks = <&atl_gfclk_mux>; | |
ee6c7507 TK |
27 | }; |
28 | ||
0cccd919 | 29 | atl_clkin3_ck: atl_clkin3_ck { |
ee6c7507 | 30 | #clock-cells = <0>; |
2ca0945f PU |
31 | compatible = "ti,dra7-atl-clock"; |
32 | clocks = <&atl_gfclk_mux>; | |
ee6c7507 TK |
33 | }; |
34 | ||
35 | hdmi_clkin_ck: hdmi_clkin_ck { | |
36 | #clock-cells = <0>; | |
37 | compatible = "fixed-clock"; | |
38 | clock-frequency = <0>; | |
39 | }; | |
40 | ||
41 | mlb_clkin_ck: mlb_clkin_ck { | |
42 | #clock-cells = <0>; | |
43 | compatible = "fixed-clock"; | |
44 | clock-frequency = <0>; | |
45 | }; | |
46 | ||
47 | mlbp_clkin_ck: mlbp_clkin_ck { | |
48 | #clock-cells = <0>; | |
49 | compatible = "fixed-clock"; | |
50 | clock-frequency = <0>; | |
51 | }; | |
52 | ||
53 | pciesref_acs_clk_ck: pciesref_acs_clk_ck { | |
54 | #clock-cells = <0>; | |
55 | compatible = "fixed-clock"; | |
56 | clock-frequency = <100000000>; | |
57 | }; | |
58 | ||
59 | ref_clkin0_ck: ref_clkin0_ck { | |
60 | #clock-cells = <0>; | |
61 | compatible = "fixed-clock"; | |
62 | clock-frequency = <0>; | |
63 | }; | |
64 | ||
65 | ref_clkin1_ck: ref_clkin1_ck { | |
66 | #clock-cells = <0>; | |
67 | compatible = "fixed-clock"; | |
68 | clock-frequency = <0>; | |
69 | }; | |
70 | ||
71 | ref_clkin2_ck: ref_clkin2_ck { | |
72 | #clock-cells = <0>; | |
73 | compatible = "fixed-clock"; | |
74 | clock-frequency = <0>; | |
75 | }; | |
76 | ||
77 | ref_clkin3_ck: ref_clkin3_ck { | |
78 | #clock-cells = <0>; | |
79 | compatible = "fixed-clock"; | |
80 | clock-frequency = <0>; | |
81 | }; | |
82 | ||
83 | rmii_clk_ck: rmii_clk_ck { | |
84 | #clock-cells = <0>; | |
85 | compatible = "fixed-clock"; | |
86 | clock-frequency = <0>; | |
87 | }; | |
88 | ||
89 | sdvenc_clkin_ck: sdvenc_clkin_ck { | |
90 | #clock-cells = <0>; | |
91 | compatible = "fixed-clock"; | |
92 | clock-frequency = <0>; | |
93 | }; | |
94 | ||
95 | secure_32k_clk_src_ck: secure_32k_clk_src_ck { | |
96 | #clock-cells = <0>; | |
97 | compatible = "fixed-clock"; | |
98 | clock-frequency = <32768>; | |
99 | }; | |
100 | ||
eea08802 | 101 | sys_clk32_crystal_ck: sys_clk32_crystal_ck { |
ee6c7507 TK |
102 | #clock-cells = <0>; |
103 | compatible = "fixed-clock"; | |
104 | clock-frequency = <32768>; | |
105 | }; | |
106 | ||
eea08802 K |
107 | sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { |
108 | #clock-cells = <0>; | |
109 | compatible = "fixed-factor-clock"; | |
110 | clocks = <&sys_clkin1>; | |
111 | clock-mult = <1>; | |
112 | clock-div = <610>; | |
113 | }; | |
114 | ||
ee6c7507 TK |
115 | virt_12000000_ck: virt_12000000_ck { |
116 | #clock-cells = <0>; | |
117 | compatible = "fixed-clock"; | |
118 | clock-frequency = <12000000>; | |
119 | }; | |
120 | ||
121 | virt_13000000_ck: virt_13000000_ck { | |
122 | #clock-cells = <0>; | |
123 | compatible = "fixed-clock"; | |
124 | clock-frequency = <13000000>; | |
125 | }; | |
126 | ||
127 | virt_16800000_ck: virt_16800000_ck { | |
128 | #clock-cells = <0>; | |
129 | compatible = "fixed-clock"; | |
130 | clock-frequency = <16800000>; | |
131 | }; | |
132 | ||
133 | virt_19200000_ck: virt_19200000_ck { | |
134 | #clock-cells = <0>; | |
135 | compatible = "fixed-clock"; | |
136 | clock-frequency = <19200000>; | |
137 | }; | |
138 | ||
139 | virt_20000000_ck: virt_20000000_ck { | |
140 | #clock-cells = <0>; | |
141 | compatible = "fixed-clock"; | |
142 | clock-frequency = <20000000>; | |
143 | }; | |
144 | ||
145 | virt_26000000_ck: virt_26000000_ck { | |
146 | #clock-cells = <0>; | |
147 | compatible = "fixed-clock"; | |
148 | clock-frequency = <26000000>; | |
149 | }; | |
150 | ||
151 | virt_27000000_ck: virt_27000000_ck { | |
152 | #clock-cells = <0>; | |
153 | compatible = "fixed-clock"; | |
154 | clock-frequency = <27000000>; | |
155 | }; | |
156 | ||
157 | virt_38400000_ck: virt_38400000_ck { | |
158 | #clock-cells = <0>; | |
159 | compatible = "fixed-clock"; | |
160 | clock-frequency = <38400000>; | |
161 | }; | |
162 | ||
163 | sys_clkin2: sys_clkin2 { | |
164 | #clock-cells = <0>; | |
165 | compatible = "fixed-clock"; | |
166 | clock-frequency = <22579200>; | |
167 | }; | |
168 | ||
169 | usb_otg_clkin_ck: usb_otg_clkin_ck { | |
170 | #clock-cells = <0>; | |
171 | compatible = "fixed-clock"; | |
172 | clock-frequency = <0>; | |
173 | }; | |
174 | ||
175 | video1_clkin_ck: video1_clkin_ck { | |
176 | #clock-cells = <0>; | |
177 | compatible = "fixed-clock"; | |
178 | clock-frequency = <0>; | |
179 | }; | |
180 | ||
181 | video1_m2_clkin_ck: video1_m2_clkin_ck { | |
182 | #clock-cells = <0>; | |
183 | compatible = "fixed-clock"; | |
184 | clock-frequency = <0>; | |
185 | }; | |
186 | ||
187 | video2_clkin_ck: video2_clkin_ck { | |
188 | #clock-cells = <0>; | |
189 | compatible = "fixed-clock"; | |
190 | clock-frequency = <0>; | |
191 | }; | |
192 | ||
193 | video2_m2_clkin_ck: video2_m2_clkin_ck { | |
194 | #clock-cells = <0>; | |
195 | compatible = "fixed-clock"; | |
196 | clock-frequency = <0>; | |
197 | }; | |
198 | ||
ca8a3d4e | 199 | dpll_abe_ck: dpll_abe_ck@1e0 { |
ee6c7507 TK |
200 | #clock-cells = <0>; |
201 | compatible = "ti,omap4-dpll-m4xen-clock"; | |
202 | clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; | |
203 | reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; | |
204 | }; | |
205 | ||
206 | dpll_abe_x2_ck: dpll_abe_x2_ck { | |
207 | #clock-cells = <0>; | |
208 | compatible = "ti,omap4-dpll-x2-clock"; | |
209 | clocks = <&dpll_abe_ck>; | |
210 | }; | |
211 | ||
ca8a3d4e | 212 | dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { |
ee6c7507 TK |
213 | #clock-cells = <0>; |
214 | compatible = "ti,divider-clock"; | |
215 | clocks = <&dpll_abe_x2_ck>; | |
216 | ti,max-div = <31>; | |
217 | ti,autoidle-shift = <8>; | |
218 | reg = <0x01f0>; | |
219 | ti,index-starts-at-one; | |
220 | ti,invert-autoidle-bit; | |
221 | }; | |
222 | ||
ca8a3d4e | 223 | abe_clk: abe_clk@108 { |
ee6c7507 TK |
224 | #clock-cells = <0>; |
225 | compatible = "ti,divider-clock"; | |
226 | clocks = <&dpll_abe_m2x2_ck>; | |
227 | ti,max-div = <4>; | |
228 | reg = <0x0108>; | |
229 | ti,index-power-of-two; | |
230 | }; | |
231 | ||
ca8a3d4e | 232 | dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { |
ee6c7507 TK |
233 | #clock-cells = <0>; |
234 | compatible = "ti,divider-clock"; | |
235 | clocks = <&dpll_abe_ck>; | |
236 | ti,max-div = <31>; | |
237 | ti,autoidle-shift = <8>; | |
238 | reg = <0x01f0>; | |
239 | ti,index-starts-at-one; | |
240 | ti,invert-autoidle-bit; | |
241 | }; | |
242 | ||
ca8a3d4e | 243 | dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { |
ee6c7507 TK |
244 | #clock-cells = <0>; |
245 | compatible = "ti,divider-clock"; | |
246 | clocks = <&dpll_abe_x2_ck>; | |
247 | ti,max-div = <31>; | |
248 | ti,autoidle-shift = <8>; | |
249 | reg = <0x01f4>; | |
250 | ti,index-starts-at-one; | |
251 | ti,invert-autoidle-bit; | |
252 | }; | |
253 | ||
ca8a3d4e | 254 | dpll_core_byp_mux: dpll_core_byp_mux@12c { |
d2192ea0 RK |
255 | #clock-cells = <0>; |
256 | compatible = "ti,mux-clock"; | |
257 | clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; | |
258 | ti,bit-shift = <23>; | |
259 | reg = <0x012c>; | |
260 | }; | |
261 | ||
ca8a3d4e | 262 | dpll_core_ck: dpll_core_ck@120 { |
ee6c7507 TK |
263 | #clock-cells = <0>; |
264 | compatible = "ti,omap4-dpll-core-clock"; | |
d2192ea0 | 265 | clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; |
ee6c7507 TK |
266 | reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; |
267 | }; | |
268 | ||
269 | dpll_core_x2_ck: dpll_core_x2_ck { | |
270 | #clock-cells = <0>; | |
271 | compatible = "ti,omap4-dpll-x2-clock"; | |
272 | clocks = <&dpll_core_ck>; | |
273 | }; | |
274 | ||
ca8a3d4e | 275 | dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { |
ee6c7507 TK |
276 | #clock-cells = <0>; |
277 | compatible = "ti,divider-clock"; | |
278 | clocks = <&dpll_core_x2_ck>; | |
279 | ti,max-div = <63>; | |
280 | ti,autoidle-shift = <8>; | |
281 | reg = <0x013c>; | |
282 | ti,index-starts-at-one; | |
283 | ti,invert-autoidle-bit; | |
284 | }; | |
285 | ||
286 | mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { | |
287 | #clock-cells = <0>; | |
288 | compatible = "fixed-factor-clock"; | |
289 | clocks = <&dpll_core_h12x2_ck>; | |
290 | clock-mult = <1>; | |
291 | clock-div = <1>; | |
292 | }; | |
293 | ||
ca8a3d4e | 294 | dpll_mpu_ck: dpll_mpu_ck@160 { |
ee6c7507 | 295 | #clock-cells = <0>; |
7e148070 | 296 | compatible = "ti,omap5-mpu-dpll-clock"; |
ee6c7507 TK |
297 | clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; |
298 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | |
299 | }; | |
300 | ||
ca8a3d4e | 301 | dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { |
ee6c7507 TK |
302 | #clock-cells = <0>; |
303 | compatible = "ti,divider-clock"; | |
304 | clocks = <&dpll_mpu_ck>; | |
305 | ti,max-div = <31>; | |
306 | ti,autoidle-shift = <8>; | |
307 | reg = <0x0170>; | |
308 | ti,index-starts-at-one; | |
309 | ti,invert-autoidle-bit; | |
310 | }; | |
311 | ||
312 | mpu_dclk_div: mpu_dclk_div { | |
313 | #clock-cells = <0>; | |
314 | compatible = "fixed-factor-clock"; | |
315 | clocks = <&dpll_mpu_m2_ck>; | |
316 | clock-mult = <1>; | |
317 | clock-div = <1>; | |
318 | }; | |
319 | ||
320 | dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { | |
321 | #clock-cells = <0>; | |
322 | compatible = "fixed-factor-clock"; | |
323 | clocks = <&dpll_core_h12x2_ck>; | |
324 | clock-mult = <1>; | |
325 | clock-div = <1>; | |
326 | }; | |
327 | ||
ca8a3d4e | 328 | dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { |
d2192ea0 RK |
329 | #clock-cells = <0>; |
330 | compatible = "ti,mux-clock"; | |
331 | clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; | |
332 | ti,bit-shift = <23>; | |
333 | reg = <0x0240>; | |
334 | }; | |
335 | ||
ca8a3d4e | 336 | dpll_dsp_ck: dpll_dsp_ck@234 { |
ee6c7507 TK |
337 | #clock-cells = <0>; |
338 | compatible = "ti,omap4-dpll-clock"; | |
d2192ea0 | 339 | clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; |
ee6c7507 TK |
340 | reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; |
341 | }; | |
342 | ||
ca8a3d4e | 343 | dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { |
ee6c7507 TK |
344 | #clock-cells = <0>; |
345 | compatible = "ti,divider-clock"; | |
346 | clocks = <&dpll_dsp_ck>; | |
347 | ti,max-div = <31>; | |
348 | ti,autoidle-shift = <8>; | |
349 | reg = <0x0244>; | |
350 | ti,index-starts-at-one; | |
351 | ti,invert-autoidle-bit; | |
352 | }; | |
353 | ||
354 | iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { | |
355 | #clock-cells = <0>; | |
356 | compatible = "fixed-factor-clock"; | |
357 | clocks = <&dpll_core_h12x2_ck>; | |
358 | clock-mult = <1>; | |
359 | clock-div = <1>; | |
360 | }; | |
361 | ||
ca8a3d4e | 362 | dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { |
d2192ea0 RK |
363 | #clock-cells = <0>; |
364 | compatible = "ti,mux-clock"; | |
365 | clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; | |
366 | ti,bit-shift = <23>; | |
367 | reg = <0x01ac>; | |
368 | }; | |
369 | ||
ca8a3d4e | 370 | dpll_iva_ck: dpll_iva_ck@1a0 { |
ee6c7507 TK |
371 | #clock-cells = <0>; |
372 | compatible = "ti,omap4-dpll-clock"; | |
d2192ea0 | 373 | clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; |
ee6c7507 TK |
374 | reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; |
375 | }; | |
376 | ||
ca8a3d4e | 377 | dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { |
ee6c7507 TK |
378 | #clock-cells = <0>; |
379 | compatible = "ti,divider-clock"; | |
380 | clocks = <&dpll_iva_ck>; | |
381 | ti,max-div = <31>; | |
382 | ti,autoidle-shift = <8>; | |
383 | reg = <0x01b0>; | |
384 | ti,index-starts-at-one; | |
385 | ti,invert-autoidle-bit; | |
386 | }; | |
387 | ||
388 | iva_dclk: iva_dclk { | |
389 | #clock-cells = <0>; | |
390 | compatible = "fixed-factor-clock"; | |
391 | clocks = <&dpll_iva_m2_ck>; | |
392 | clock-mult = <1>; | |
393 | clock-div = <1>; | |
394 | }; | |
395 | ||
ca8a3d4e | 396 | dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { |
d2192ea0 RK |
397 | #clock-cells = <0>; |
398 | compatible = "ti,mux-clock"; | |
399 | clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; | |
400 | ti,bit-shift = <23>; | |
401 | reg = <0x02e4>; | |
402 | }; | |
403 | ||
ca8a3d4e | 404 | dpll_gpu_ck: dpll_gpu_ck@2d8 { |
ee6c7507 TK |
405 | #clock-cells = <0>; |
406 | compatible = "ti,omap4-dpll-clock"; | |
d2192ea0 | 407 | clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; |
ee6c7507 TK |
408 | reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; |
409 | }; | |
410 | ||
ca8a3d4e | 411 | dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { |
ee6c7507 TK |
412 | #clock-cells = <0>; |
413 | compatible = "ti,divider-clock"; | |
414 | clocks = <&dpll_gpu_ck>; | |
415 | ti,max-div = <31>; | |
416 | ti,autoidle-shift = <8>; | |
417 | reg = <0x02e8>; | |
418 | ti,index-starts-at-one; | |
419 | ti,invert-autoidle-bit; | |
420 | }; | |
421 | ||
ca8a3d4e | 422 | dpll_core_m2_ck: dpll_core_m2_ck@130 { |
ee6c7507 TK |
423 | #clock-cells = <0>; |
424 | compatible = "ti,divider-clock"; | |
425 | clocks = <&dpll_core_ck>; | |
426 | ti,max-div = <31>; | |
427 | ti,autoidle-shift = <8>; | |
428 | reg = <0x0130>; | |
429 | ti,index-starts-at-one; | |
430 | ti,invert-autoidle-bit; | |
431 | }; | |
432 | ||
433 | core_dpll_out_dclk_div: core_dpll_out_dclk_div { | |
434 | #clock-cells = <0>; | |
435 | compatible = "fixed-factor-clock"; | |
436 | clocks = <&dpll_core_m2_ck>; | |
437 | clock-mult = <1>; | |
438 | clock-div = <1>; | |
439 | }; | |
440 | ||
ca8a3d4e | 441 | dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { |
d2192ea0 RK |
442 | #clock-cells = <0>; |
443 | compatible = "ti,mux-clock"; | |
444 | clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; | |
445 | ti,bit-shift = <23>; | |
446 | reg = <0x021c>; | |
447 | }; | |
448 | ||
ca8a3d4e | 449 | dpll_ddr_ck: dpll_ddr_ck@210 { |
ee6c7507 TK |
450 | #clock-cells = <0>; |
451 | compatible = "ti,omap4-dpll-clock"; | |
d2192ea0 | 452 | clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; |
ee6c7507 TK |
453 | reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; |
454 | }; | |
455 | ||
ca8a3d4e | 456 | dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { |
ee6c7507 TK |
457 | #clock-cells = <0>; |
458 | compatible = "ti,divider-clock"; | |
459 | clocks = <&dpll_ddr_ck>; | |
460 | ti,max-div = <31>; | |
461 | ti,autoidle-shift = <8>; | |
462 | reg = <0x0220>; | |
463 | ti,index-starts-at-one; | |
464 | ti,invert-autoidle-bit; | |
465 | }; | |
466 | ||
ca8a3d4e | 467 | dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { |
d2192ea0 RK |
468 | #clock-cells = <0>; |
469 | compatible = "ti,mux-clock"; | |
470 | clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; | |
471 | ti,bit-shift = <23>; | |
472 | reg = <0x02b4>; | |
473 | }; | |
474 | ||
ca8a3d4e | 475 | dpll_gmac_ck: dpll_gmac_ck@2a8 { |
ee6c7507 TK |
476 | #clock-cells = <0>; |
477 | compatible = "ti,omap4-dpll-clock"; | |
d2192ea0 | 478 | clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; |
ee6c7507 TK |
479 | reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; |
480 | }; | |
481 | ||
ca8a3d4e | 482 | dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { |
ee6c7507 TK |
483 | #clock-cells = <0>; |
484 | compatible = "ti,divider-clock"; | |
485 | clocks = <&dpll_gmac_ck>; | |
486 | ti,max-div = <31>; | |
487 | ti,autoidle-shift = <8>; | |
488 | reg = <0x02b8>; | |
489 | ti,index-starts-at-one; | |
490 | ti,invert-autoidle-bit; | |
491 | }; | |
492 | ||
493 | video2_dclk_div: video2_dclk_div { | |
494 | #clock-cells = <0>; | |
495 | compatible = "fixed-factor-clock"; | |
496 | clocks = <&video2_m2_clkin_ck>; | |
497 | clock-mult = <1>; | |
498 | clock-div = <1>; | |
499 | }; | |
500 | ||
501 | video1_dclk_div: video1_dclk_div { | |
502 | #clock-cells = <0>; | |
503 | compatible = "fixed-factor-clock"; | |
504 | clocks = <&video1_m2_clkin_ck>; | |
505 | clock-mult = <1>; | |
506 | clock-div = <1>; | |
507 | }; | |
508 | ||
509 | hdmi_dclk_div: hdmi_dclk_div { | |
510 | #clock-cells = <0>; | |
511 | compatible = "fixed-factor-clock"; | |
512 | clocks = <&hdmi_clkin_ck>; | |
513 | clock-mult = <1>; | |
514 | clock-div = <1>; | |
515 | }; | |
516 | ||
517 | per_dpll_hs_clk_div: per_dpll_hs_clk_div { | |
518 | #clock-cells = <0>; | |
519 | compatible = "fixed-factor-clock"; | |
520 | clocks = <&dpll_abe_m3x2_ck>; | |
521 | clock-mult = <1>; | |
522 | clock-div = <2>; | |
523 | }; | |
524 | ||
525 | usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { | |
526 | #clock-cells = <0>; | |
527 | compatible = "fixed-factor-clock"; | |
528 | clocks = <&dpll_abe_m3x2_ck>; | |
529 | clock-mult = <1>; | |
530 | clock-div = <3>; | |
531 | }; | |
532 | ||
533 | eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { | |
534 | #clock-cells = <0>; | |
535 | compatible = "fixed-factor-clock"; | |
536 | clocks = <&dpll_core_h12x2_ck>; | |
537 | clock-mult = <1>; | |
538 | clock-div = <1>; | |
539 | }; | |
540 | ||
ca8a3d4e | 541 | dpll_eve_byp_mux: dpll_eve_byp_mux@290 { |
d2192ea0 RK |
542 | #clock-cells = <0>; |
543 | compatible = "ti,mux-clock"; | |
544 | clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; | |
545 | ti,bit-shift = <23>; | |
546 | reg = <0x0290>; | |
547 | }; | |
548 | ||
ca8a3d4e | 549 | dpll_eve_ck: dpll_eve_ck@284 { |
ee6c7507 TK |
550 | #clock-cells = <0>; |
551 | compatible = "ti,omap4-dpll-clock"; | |
d2192ea0 | 552 | clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; |
ee6c7507 TK |
553 | reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; |
554 | }; | |
555 | ||
ca8a3d4e | 556 | dpll_eve_m2_ck: dpll_eve_m2_ck@294 { |
ee6c7507 TK |
557 | #clock-cells = <0>; |
558 | compatible = "ti,divider-clock"; | |
559 | clocks = <&dpll_eve_ck>; | |
560 | ti,max-div = <31>; | |
561 | ti,autoidle-shift = <8>; | |
562 | reg = <0x0294>; | |
563 | ti,index-starts-at-one; | |
564 | ti,invert-autoidle-bit; | |
565 | }; | |
566 | ||
567 | eve_dclk_div: eve_dclk_div { | |
568 | #clock-cells = <0>; | |
569 | compatible = "fixed-factor-clock"; | |
570 | clocks = <&dpll_eve_m2_ck>; | |
571 | clock-mult = <1>; | |
572 | clock-div = <1>; | |
573 | }; | |
574 | ||
ca8a3d4e | 575 | dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { |
ee6c7507 TK |
576 | #clock-cells = <0>; |
577 | compatible = "ti,divider-clock"; | |
578 | clocks = <&dpll_core_x2_ck>; | |
579 | ti,max-div = <63>; | |
580 | ti,autoidle-shift = <8>; | |
581 | reg = <0x0140>; | |
582 | ti,index-starts-at-one; | |
583 | ti,invert-autoidle-bit; | |
584 | }; | |
585 | ||
ca8a3d4e | 586 | dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { |
ee6c7507 TK |
587 | #clock-cells = <0>; |
588 | compatible = "ti,divider-clock"; | |
589 | clocks = <&dpll_core_x2_ck>; | |
590 | ti,max-div = <63>; | |
591 | ti,autoidle-shift = <8>; | |
592 | reg = <0x0144>; | |
593 | ti,index-starts-at-one; | |
594 | ti,invert-autoidle-bit; | |
595 | }; | |
596 | ||
ca8a3d4e | 597 | dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { |
ee6c7507 TK |
598 | #clock-cells = <0>; |
599 | compatible = "ti,divider-clock"; | |
600 | clocks = <&dpll_core_x2_ck>; | |
601 | ti,max-div = <63>; | |
602 | ti,autoidle-shift = <8>; | |
603 | reg = <0x0154>; | |
604 | ti,index-starts-at-one; | |
605 | ti,invert-autoidle-bit; | |
606 | }; | |
607 | ||
ca8a3d4e | 608 | dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { |
ee6c7507 TK |
609 | #clock-cells = <0>; |
610 | compatible = "ti,divider-clock"; | |
611 | clocks = <&dpll_core_x2_ck>; | |
612 | ti,max-div = <63>; | |
613 | ti,autoidle-shift = <8>; | |
614 | reg = <0x0158>; | |
615 | ti,index-starts-at-one; | |
616 | ti,invert-autoidle-bit; | |
617 | }; | |
618 | ||
ca8a3d4e | 619 | dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { |
ee6c7507 TK |
620 | #clock-cells = <0>; |
621 | compatible = "ti,divider-clock"; | |
622 | clocks = <&dpll_core_x2_ck>; | |
623 | ti,max-div = <63>; | |
624 | ti,autoidle-shift = <8>; | |
625 | reg = <0x015c>; | |
626 | ti,index-starts-at-one; | |
627 | ti,invert-autoidle-bit; | |
628 | }; | |
629 | ||
630 | dpll_ddr_x2_ck: dpll_ddr_x2_ck { | |
631 | #clock-cells = <0>; | |
632 | compatible = "ti,omap4-dpll-x2-clock"; | |
633 | clocks = <&dpll_ddr_ck>; | |
634 | }; | |
635 | ||
ca8a3d4e | 636 | dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { |
ee6c7507 TK |
637 | #clock-cells = <0>; |
638 | compatible = "ti,divider-clock"; | |
639 | clocks = <&dpll_ddr_x2_ck>; | |
640 | ti,max-div = <63>; | |
641 | ti,autoidle-shift = <8>; | |
642 | reg = <0x0228>; | |
643 | ti,index-starts-at-one; | |
644 | ti,invert-autoidle-bit; | |
645 | }; | |
646 | ||
647 | dpll_dsp_x2_ck: dpll_dsp_x2_ck { | |
648 | #clock-cells = <0>; | |
649 | compatible = "ti,omap4-dpll-x2-clock"; | |
650 | clocks = <&dpll_dsp_ck>; | |
651 | }; | |
652 | ||
ca8a3d4e | 653 | dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { |
ee6c7507 TK |
654 | #clock-cells = <0>; |
655 | compatible = "ti,divider-clock"; | |
656 | clocks = <&dpll_dsp_x2_ck>; | |
657 | ti,max-div = <31>; | |
658 | ti,autoidle-shift = <8>; | |
659 | reg = <0x0248>; | |
660 | ti,index-starts-at-one; | |
661 | ti,invert-autoidle-bit; | |
662 | }; | |
663 | ||
664 | dpll_gmac_x2_ck: dpll_gmac_x2_ck { | |
665 | #clock-cells = <0>; | |
666 | compatible = "ti,omap4-dpll-x2-clock"; | |
667 | clocks = <&dpll_gmac_ck>; | |
668 | }; | |
669 | ||
ca8a3d4e | 670 | dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { |
ee6c7507 TK |
671 | #clock-cells = <0>; |
672 | compatible = "ti,divider-clock"; | |
673 | clocks = <&dpll_gmac_x2_ck>; | |
674 | ti,max-div = <63>; | |
675 | ti,autoidle-shift = <8>; | |
676 | reg = <0x02c0>; | |
677 | ti,index-starts-at-one; | |
678 | ti,invert-autoidle-bit; | |
679 | }; | |
680 | ||
ca8a3d4e | 681 | dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { |
ee6c7507 TK |
682 | #clock-cells = <0>; |
683 | compatible = "ti,divider-clock"; | |
684 | clocks = <&dpll_gmac_x2_ck>; | |
685 | ti,max-div = <63>; | |
686 | ti,autoidle-shift = <8>; | |
687 | reg = <0x02c4>; | |
688 | ti,index-starts-at-one; | |
689 | ti,invert-autoidle-bit; | |
690 | }; | |
691 | ||
ca8a3d4e | 692 | dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { |
ee6c7507 TK |
693 | #clock-cells = <0>; |
694 | compatible = "ti,divider-clock"; | |
695 | clocks = <&dpll_gmac_x2_ck>; | |
696 | ti,max-div = <63>; | |
697 | ti,autoidle-shift = <8>; | |
698 | reg = <0x02c8>; | |
699 | ti,index-starts-at-one; | |
700 | ti,invert-autoidle-bit; | |
701 | }; | |
702 | ||
ca8a3d4e | 703 | dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { |
ee6c7507 TK |
704 | #clock-cells = <0>; |
705 | compatible = "ti,divider-clock"; | |
706 | clocks = <&dpll_gmac_x2_ck>; | |
707 | ti,max-div = <31>; | |
708 | ti,autoidle-shift = <8>; | |
709 | reg = <0x02bc>; | |
710 | ti,index-starts-at-one; | |
711 | ti,invert-autoidle-bit; | |
712 | }; | |
713 | ||
714 | gmii_m_clk_div: gmii_m_clk_div { | |
715 | #clock-cells = <0>; | |
716 | compatible = "fixed-factor-clock"; | |
717 | clocks = <&dpll_gmac_h11x2_ck>; | |
718 | clock-mult = <1>; | |
719 | clock-div = <2>; | |
720 | }; | |
721 | ||
722 | hdmi_clk2_div: hdmi_clk2_div { | |
723 | #clock-cells = <0>; | |
724 | compatible = "fixed-factor-clock"; | |
725 | clocks = <&hdmi_clkin_ck>; | |
726 | clock-mult = <1>; | |
727 | clock-div = <1>; | |
728 | }; | |
729 | ||
730 | hdmi_div_clk: hdmi_div_clk { | |
731 | #clock-cells = <0>; | |
732 | compatible = "fixed-factor-clock"; | |
733 | clocks = <&hdmi_clkin_ck>; | |
734 | clock-mult = <1>; | |
735 | clock-div = <1>; | |
736 | }; | |
737 | ||
ca8a3d4e | 738 | l3_iclk_div: l3_iclk_div@100 { |
ee6c7507 | 739 | #clock-cells = <0>; |
dd94324b RN |
740 | compatible = "ti,divider-clock"; |
741 | ti,max-div = <2>; | |
742 | ti,bit-shift = <4>; | |
743 | reg = <0x0100>; | |
ee6c7507 | 744 | clocks = <&dpll_core_h12x2_ck>; |
dd94324b | 745 | ti,index-power-of-two; |
ee6c7507 TK |
746 | }; |
747 | ||
748 | l4_root_clk_div: l4_root_clk_div { | |
749 | #clock-cells = <0>; | |
750 | compatible = "fixed-factor-clock"; | |
751 | clocks = <&l3_iclk_div>; | |
752 | clock-mult = <1>; | |
dd94324b | 753 | clock-div = <2>; |
ee6c7507 TK |
754 | }; |
755 | ||
756 | video1_clk2_div: video1_clk2_div { | |
757 | #clock-cells = <0>; | |
758 | compatible = "fixed-factor-clock"; | |
759 | clocks = <&video1_clkin_ck>; | |
760 | clock-mult = <1>; | |
761 | clock-div = <1>; | |
762 | }; | |
763 | ||
764 | video1_div_clk: video1_div_clk { | |
765 | #clock-cells = <0>; | |
766 | compatible = "fixed-factor-clock"; | |
767 | clocks = <&video1_clkin_ck>; | |
768 | clock-mult = <1>; | |
769 | clock-div = <1>; | |
770 | }; | |
771 | ||
772 | video2_clk2_div: video2_clk2_div { | |
773 | #clock-cells = <0>; | |
774 | compatible = "fixed-factor-clock"; | |
775 | clocks = <&video2_clkin_ck>; | |
776 | clock-mult = <1>; | |
777 | clock-div = <1>; | |
778 | }; | |
779 | ||
780 | video2_div_clk: video2_div_clk { | |
781 | #clock-cells = <0>; | |
782 | compatible = "fixed-factor-clock"; | |
783 | clocks = <&video2_clkin_ck>; | |
784 | clock-mult = <1>; | |
785 | clock-div = <1>; | |
786 | }; | |
787 | ||
ca8a3d4e | 788 | ipu1_gfclk_mux: ipu1_gfclk_mux@520 { |
ee6c7507 TK |
789 | #clock-cells = <0>; |
790 | compatible = "ti,mux-clock"; | |
791 | clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; | |
792 | ti,bit-shift = <24>; | |
793 | reg = <0x0520>; | |
794 | }; | |
795 | ||
ca8a3d4e | 796 | mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 { |
ee6c7507 TK |
797 | #clock-cells = <0>; |
798 | compatible = "ti,mux-clock"; | |
0cccd919 | 799 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
800 | ti,bit-shift = <28>; |
801 | reg = <0x0550>; | |
802 | }; | |
803 | ||
ca8a3d4e | 804 | mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 { |
ee6c7507 TK |
805 | #clock-cells = <0>; |
806 | compatible = "ti,mux-clock"; | |
0cccd919 | 807 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
808 | ti,bit-shift = <24>; |
809 | reg = <0x0550>; | |
810 | }; | |
811 | ||
ca8a3d4e | 812 | mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 { |
ee6c7507 TK |
813 | #clock-cells = <0>; |
814 | compatible = "ti,mux-clock"; | |
815 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
816 | ti,bit-shift = <22>; | |
817 | reg = <0x0550>; | |
818 | }; | |
819 | ||
ca8a3d4e | 820 | timer5_gfclk_mux: timer5_gfclk_mux@558 { |
ee6c7507 TK |
821 | #clock-cells = <0>; |
822 | compatible = "ti,mux-clock"; | |
823 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; | |
824 | ti,bit-shift = <24>; | |
825 | reg = <0x0558>; | |
826 | }; | |
827 | ||
ca8a3d4e | 828 | timer6_gfclk_mux: timer6_gfclk_mux@560 { |
ee6c7507 TK |
829 | #clock-cells = <0>; |
830 | compatible = "ti,mux-clock"; | |
831 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; | |
832 | ti,bit-shift = <24>; | |
833 | reg = <0x0560>; | |
834 | }; | |
835 | ||
ca8a3d4e | 836 | timer7_gfclk_mux: timer7_gfclk_mux@568 { |
ee6c7507 TK |
837 | #clock-cells = <0>; |
838 | compatible = "ti,mux-clock"; | |
839 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; | |
840 | ti,bit-shift = <24>; | |
841 | reg = <0x0568>; | |
842 | }; | |
843 | ||
ca8a3d4e | 844 | timer8_gfclk_mux: timer8_gfclk_mux@570 { |
ee6c7507 TK |
845 | #clock-cells = <0>; |
846 | compatible = "ti,mux-clock"; | |
847 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; | |
848 | ti,bit-shift = <24>; | |
849 | reg = <0x0570>; | |
850 | }; | |
851 | ||
ca8a3d4e | 852 | uart6_gfclk_mux: uart6_gfclk_mux@580 { |
ee6c7507 TK |
853 | #clock-cells = <0>; |
854 | compatible = "ti,mux-clock"; | |
855 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
856 | ti,bit-shift = <24>; | |
857 | reg = <0x0580>; | |
858 | }; | |
859 | ||
860 | dummy_ck: dummy_ck { | |
861 | #clock-cells = <0>; | |
862 | compatible = "fixed-clock"; | |
863 | clock-frequency = <0>; | |
864 | }; | |
865 | }; | |
866 | &prm_clocks { | |
ca8a3d4e | 867 | sys_clkin1: sys_clkin1@110 { |
ee6c7507 TK |
868 | #clock-cells = <0>; |
869 | compatible = "ti,mux-clock"; | |
870 | clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; | |
871 | reg = <0x0110>; | |
872 | ti,index-starts-at-one; | |
873 | }; | |
874 | ||
ca8a3d4e | 875 | abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { |
ee6c7507 TK |
876 | #clock-cells = <0>; |
877 | compatible = "ti,mux-clock"; | |
878 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
879 | reg = <0x0118>; | |
880 | }; | |
881 | ||
ca8a3d4e | 882 | abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { |
ee6c7507 TK |
883 | #clock-cells = <0>; |
884 | compatible = "ti,mux-clock"; | |
885 | clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; | |
886 | reg = <0x0114>; | |
887 | }; | |
888 | ||
ca8a3d4e | 889 | abe_dpll_clk_mux: abe_dpll_clk_mux@10c { |
ee6c7507 TK |
890 | #clock-cells = <0>; |
891 | compatible = "ti,mux-clock"; | |
892 | clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; | |
893 | reg = <0x010c>; | |
894 | }; | |
895 | ||
ca8a3d4e | 896 | abe_24m_fclk: abe_24m_fclk@11c { |
ee6c7507 TK |
897 | #clock-cells = <0>; |
898 | compatible = "ti,divider-clock"; | |
899 | clocks = <&dpll_abe_m2x2_ck>; | |
900 | reg = <0x011c>; | |
901 | ti,dividers = <8>, <16>; | |
902 | }; | |
903 | ||
ca8a3d4e | 904 | aess_fclk: aess_fclk@178 { |
ee6c7507 TK |
905 | #clock-cells = <0>; |
906 | compatible = "ti,divider-clock"; | |
907 | clocks = <&abe_clk>; | |
908 | reg = <0x0178>; | |
909 | ti,max-div = <2>; | |
910 | }; | |
911 | ||
ca8a3d4e | 912 | abe_giclk_div: abe_giclk_div@174 { |
ee6c7507 TK |
913 | #clock-cells = <0>; |
914 | compatible = "ti,divider-clock"; | |
915 | clocks = <&aess_fclk>; | |
916 | reg = <0x0174>; | |
917 | ti,max-div = <2>; | |
918 | }; | |
919 | ||
ca8a3d4e | 920 | abe_lp_clk_div: abe_lp_clk_div@1d8 { |
ee6c7507 TK |
921 | #clock-cells = <0>; |
922 | compatible = "ti,divider-clock"; | |
923 | clocks = <&dpll_abe_m2x2_ck>; | |
924 | reg = <0x01d8>; | |
925 | ti,dividers = <16>, <32>; | |
926 | }; | |
927 | ||
ca8a3d4e | 928 | abe_sys_clk_div: abe_sys_clk_div@120 { |
ee6c7507 TK |
929 | #clock-cells = <0>; |
930 | compatible = "ti,divider-clock"; | |
931 | clocks = <&sys_clkin1>; | |
932 | reg = <0x0120>; | |
933 | ti,max-div = <2>; | |
934 | }; | |
935 | ||
ca8a3d4e | 936 | adc_gfclk_mux: adc_gfclk_mux@1dc { |
ee6c7507 TK |
937 | #clock-cells = <0>; |
938 | compatible = "ti,mux-clock"; | |
939 | clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; | |
940 | reg = <0x01dc>; | |
941 | }; | |
942 | ||
ca8a3d4e | 943 | sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { |
ee6c7507 TK |
944 | #clock-cells = <0>; |
945 | compatible = "ti,divider-clock"; | |
946 | clocks = <&sys_clkin1>; | |
947 | ti,max-div = <64>; | |
948 | reg = <0x01c8>; | |
949 | ti,index-power-of-two; | |
950 | }; | |
951 | ||
ca8a3d4e | 952 | sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { |
ee6c7507 TK |
953 | #clock-cells = <0>; |
954 | compatible = "ti,divider-clock"; | |
955 | clocks = <&sys_clkin2>; | |
956 | ti,max-div = <64>; | |
957 | reg = <0x01cc>; | |
958 | ti,index-power-of-two; | |
959 | }; | |
960 | ||
ca8a3d4e | 961 | per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { |
ee6c7507 TK |
962 | #clock-cells = <0>; |
963 | compatible = "ti,divider-clock"; | |
964 | clocks = <&dpll_abe_m2_ck>; | |
965 | ti,max-div = <64>; | |
966 | reg = <0x01bc>; | |
967 | ti,index-power-of-two; | |
968 | }; | |
969 | ||
ca8a3d4e | 970 | dsp_gclk_div: dsp_gclk_div@18c { |
ee6c7507 TK |
971 | #clock-cells = <0>; |
972 | compatible = "ti,divider-clock"; | |
973 | clocks = <&dpll_dsp_m2_ck>; | |
974 | ti,max-div = <64>; | |
975 | reg = <0x018c>; | |
976 | ti,index-power-of-two; | |
977 | }; | |
978 | ||
ca8a3d4e | 979 | gpu_dclk: gpu_dclk@1a0 { |
ee6c7507 TK |
980 | #clock-cells = <0>; |
981 | compatible = "ti,divider-clock"; | |
982 | clocks = <&dpll_gpu_m2_ck>; | |
983 | ti,max-div = <64>; | |
984 | reg = <0x01a0>; | |
985 | ti,index-power-of-two; | |
986 | }; | |
987 | ||
ca8a3d4e | 988 | emif_phy_dclk_div: emif_phy_dclk_div@190 { |
ee6c7507 TK |
989 | #clock-cells = <0>; |
990 | compatible = "ti,divider-clock"; | |
991 | clocks = <&dpll_ddr_m2_ck>; | |
992 | ti,max-div = <64>; | |
993 | reg = <0x0190>; | |
994 | ti,index-power-of-two; | |
995 | }; | |
996 | ||
ca8a3d4e | 997 | gmac_250m_dclk_div: gmac_250m_dclk_div@19c { |
ee6c7507 TK |
998 | #clock-cells = <0>; |
999 | compatible = "ti,divider-clock"; | |
1000 | clocks = <&dpll_gmac_m2_ck>; | |
1001 | ti,max-div = <64>; | |
1002 | reg = <0x019c>; | |
1003 | ti,index-power-of-two; | |
1004 | }; | |
1005 | ||
c097338e GS |
1006 | gmac_main_clk: gmac_main_clk { |
1007 | #clock-cells = <0>; | |
1008 | compatible = "fixed-factor-clock"; | |
1009 | clocks = <&gmac_250m_dclk_div>; | |
1010 | clock-mult = <1>; | |
1011 | clock-div = <2>; | |
1012 | }; | |
1013 | ||
ca8a3d4e | 1014 | l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { |
ee6c7507 TK |
1015 | #clock-cells = <0>; |
1016 | compatible = "ti,divider-clock"; | |
1017 | clocks = <&dpll_usb_m2_ck>; | |
1018 | ti,max-div = <64>; | |
1019 | reg = <0x01ac>; | |
1020 | ti,index-power-of-two; | |
1021 | }; | |
1022 | ||
ca8a3d4e | 1023 | usb_otg_dclk_div: usb_otg_dclk_div@184 { |
ee6c7507 TK |
1024 | #clock-cells = <0>; |
1025 | compatible = "ti,divider-clock"; | |
1026 | clocks = <&usb_otg_clkin_ck>; | |
1027 | ti,max-div = <64>; | |
1028 | reg = <0x0184>; | |
1029 | ti,index-power-of-two; | |
1030 | }; | |
1031 | ||
ca8a3d4e | 1032 | sata_dclk_div: sata_dclk_div@1c0 { |
ee6c7507 TK |
1033 | #clock-cells = <0>; |
1034 | compatible = "ti,divider-clock"; | |
1035 | clocks = <&sys_clkin1>; | |
1036 | ti,max-div = <64>; | |
1037 | reg = <0x01c0>; | |
1038 | ti,index-power-of-two; | |
1039 | }; | |
1040 | ||
ca8a3d4e | 1041 | pcie2_dclk_div: pcie2_dclk_div@1b8 { |
ee6c7507 TK |
1042 | #clock-cells = <0>; |
1043 | compatible = "ti,divider-clock"; | |
1044 | clocks = <&dpll_pcie_ref_m2_ck>; | |
1045 | ti,max-div = <64>; | |
1046 | reg = <0x01b8>; | |
1047 | ti,index-power-of-two; | |
1048 | }; | |
1049 | ||
ca8a3d4e | 1050 | pcie_dclk_div: pcie_dclk_div@1b4 { |
ee6c7507 TK |
1051 | #clock-cells = <0>; |
1052 | compatible = "ti,divider-clock"; | |
1053 | clocks = <&apll_pcie_m2_ck>; | |
1054 | ti,max-div = <64>; | |
1055 | reg = <0x01b4>; | |
1056 | ti,index-power-of-two; | |
1057 | }; | |
1058 | ||
ca8a3d4e | 1059 | emu_dclk_div: emu_dclk_div@194 { |
ee6c7507 TK |
1060 | #clock-cells = <0>; |
1061 | compatible = "ti,divider-clock"; | |
1062 | clocks = <&sys_clkin1>; | |
1063 | ti,max-div = <64>; | |
1064 | reg = <0x0194>; | |
1065 | ti,index-power-of-two; | |
1066 | }; | |
1067 | ||
ca8a3d4e | 1068 | secure_32k_dclk_div: secure_32k_dclk_div@1c4 { |
ee6c7507 TK |
1069 | #clock-cells = <0>; |
1070 | compatible = "ti,divider-clock"; | |
1071 | clocks = <&secure_32k_clk_src_ck>; | |
1072 | ti,max-div = <64>; | |
1073 | reg = <0x01c4>; | |
1074 | ti,index-power-of-two; | |
1075 | }; | |
1076 | ||
ca8a3d4e | 1077 | clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { |
ee6c7507 TK |
1078 | #clock-cells = <0>; |
1079 | compatible = "ti,mux-clock"; | |
1080 | clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; | |
1081 | reg = <0x0158>; | |
1082 | }; | |
1083 | ||
ca8a3d4e | 1084 | clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { |
ee6c7507 TK |
1085 | #clock-cells = <0>; |
1086 | compatible = "ti,mux-clock"; | |
1087 | clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; | |
1088 | reg = <0x015c>; | |
1089 | }; | |
1090 | ||
ca8a3d4e | 1091 | clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { |
ee6c7507 TK |
1092 | #clock-cells = <0>; |
1093 | compatible = "ti,mux-clock"; | |
1094 | clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; | |
1095 | reg = <0x0160>; | |
1096 | }; | |
1097 | ||
1098 | custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { | |
1099 | #clock-cells = <0>; | |
1100 | compatible = "fixed-factor-clock"; | |
1101 | clocks = <&sys_clkin1>; | |
1102 | clock-mult = <1>; | |
1103 | clock-div = <2>; | |
1104 | }; | |
1105 | ||
ca8a3d4e | 1106 | eve_clk: eve_clk@180 { |
ee6c7507 TK |
1107 | #clock-cells = <0>; |
1108 | compatible = "ti,mux-clock"; | |
1109 | clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; | |
1110 | reg = <0x0180>; | |
1111 | }; | |
1112 | ||
ca8a3d4e | 1113 | hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { |
ee6c7507 TK |
1114 | #clock-cells = <0>; |
1115 | compatible = "ti,mux-clock"; | |
1116 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
e671538d | 1117 | reg = <0x0164>; |
ee6c7507 TK |
1118 | }; |
1119 | ||
ca8a3d4e | 1120 | mlb_clk: mlb_clk@134 { |
ee6c7507 TK |
1121 | #clock-cells = <0>; |
1122 | compatible = "ti,divider-clock"; | |
1123 | clocks = <&mlb_clkin_ck>; | |
1124 | ti,max-div = <64>; | |
1125 | reg = <0x0134>; | |
1126 | ti,index-power-of-two; | |
1127 | }; | |
1128 | ||
ca8a3d4e | 1129 | mlbp_clk: mlbp_clk@130 { |
ee6c7507 TK |
1130 | #clock-cells = <0>; |
1131 | compatible = "ti,divider-clock"; | |
1132 | clocks = <&mlbp_clkin_ck>; | |
1133 | ti,max-div = <64>; | |
1134 | reg = <0x0130>; | |
1135 | ti,index-power-of-two; | |
1136 | }; | |
1137 | ||
ca8a3d4e | 1138 | per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { |
ee6c7507 TK |
1139 | #clock-cells = <0>; |
1140 | compatible = "ti,divider-clock"; | |
1141 | clocks = <&dpll_abe_m2_ck>; | |
1142 | ti,max-div = <64>; | |
1143 | reg = <0x0138>; | |
1144 | ti,index-power-of-two; | |
1145 | }; | |
1146 | ||
ca8a3d4e | 1147 | timer_sys_clk_div: timer_sys_clk_div@144 { |
ee6c7507 TK |
1148 | #clock-cells = <0>; |
1149 | compatible = "ti,divider-clock"; | |
1150 | clocks = <&sys_clkin1>; | |
1151 | reg = <0x0144>; | |
1152 | ti,max-div = <2>; | |
1153 | }; | |
1154 | ||
ca8a3d4e | 1155 | video1_dpll_clk_mux: video1_dpll_clk_mux@168 { |
ee6c7507 TK |
1156 | #clock-cells = <0>; |
1157 | compatible = "ti,mux-clock"; | |
1158 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
e671538d | 1159 | reg = <0x0168>; |
ee6c7507 TK |
1160 | }; |
1161 | ||
ca8a3d4e | 1162 | video2_dpll_clk_mux: video2_dpll_clk_mux@16c { |
ee6c7507 TK |
1163 | #clock-cells = <0>; |
1164 | compatible = "ti,mux-clock"; | |
1165 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
e671538d | 1166 | reg = <0x016c>; |
ee6c7507 TK |
1167 | }; |
1168 | ||
ca8a3d4e | 1169 | wkupaon_iclk_mux: wkupaon_iclk_mux@108 { |
ee6c7507 TK |
1170 | #clock-cells = <0>; |
1171 | compatible = "ti,mux-clock"; | |
1172 | clocks = <&sys_clkin1>, <&abe_lp_clk_div>; | |
1173 | reg = <0x0108>; | |
1174 | }; | |
1175 | ||
ca8a3d4e | 1176 | gpio1_dbclk: gpio1_dbclk@1838 { |
ee6c7507 TK |
1177 | #clock-cells = <0>; |
1178 | compatible = "ti,gate-clock"; | |
1179 | clocks = <&sys_32k_ck>; | |
1180 | ti,bit-shift = <8>; | |
1181 | reg = <0x1838>; | |
1182 | }; | |
1183 | ||
ca8a3d4e | 1184 | dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 { |
ee6c7507 TK |
1185 | #clock-cells = <0>; |
1186 | compatible = "ti,mux-clock"; | |
1187 | clocks = <&sys_clkin1>, <&sys_clkin2>; | |
1188 | ti,bit-shift = <24>; | |
1189 | reg = <0x1888>; | |
1190 | }; | |
1191 | ||
ca8a3d4e | 1192 | timer1_gfclk_mux: timer1_gfclk_mux@1840 { |
ee6c7507 TK |
1193 | #clock-cells = <0>; |
1194 | compatible = "ti,mux-clock"; | |
1195 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
1196 | ti,bit-shift = <24>; | |
1197 | reg = <0x1840>; | |
1198 | }; | |
1199 | ||
ca8a3d4e | 1200 | uart10_gfclk_mux: uart10_gfclk_mux@1880 { |
ee6c7507 TK |
1201 | #clock-cells = <0>; |
1202 | compatible = "ti,mux-clock"; | |
1203 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
1204 | ti,bit-shift = <24>; | |
1205 | reg = <0x1880>; | |
1206 | }; | |
1207 | }; | |
1208 | &cm_core_clocks { | |
ca8a3d4e | 1209 | dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { |
ee6c7507 TK |
1210 | #clock-cells = <0>; |
1211 | compatible = "ti,omap4-dpll-clock"; | |
1212 | clocks = <&sys_clkin1>, <&sys_clkin1>; | |
1213 | reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; | |
1214 | }; | |
1215 | ||
ca8a3d4e | 1216 | dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { |
ee6c7507 TK |
1217 | #clock-cells = <0>; |
1218 | compatible = "ti,divider-clock"; | |
1219 | clocks = <&dpll_pcie_ref_ck>; | |
1220 | ti,max-div = <31>; | |
1221 | ti,autoidle-shift = <8>; | |
1222 | reg = <0x0210>; | |
1223 | ti,index-starts-at-one; | |
1224 | ti,invert-autoidle-bit; | |
1225 | }; | |
1226 | ||
7d138d3a K |
1227 | apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { |
1228 | compatible = "ti,mux-clock"; | |
4310e908 | 1229 | clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; |
7d138d3a K |
1230 | #clock-cells = <0>; |
1231 | reg = <0x021c 0x4>; | |
1232 | ti,bit-shift = <7>; | |
1233 | }; | |
1234 | ||
ca8a3d4e | 1235 | apll_pcie_ck: apll_pcie_ck@21c { |
ee6c7507 | 1236 | #clock-cells = <0>; |
7d138d3a K |
1237 | compatible = "ti,dra7-apll-clock"; |
1238 | clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; | |
1239 | reg = <0x021c>, <0x0220>; | |
ee6c7507 TK |
1240 | }; |
1241 | ||
b700f42c | 1242 | optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { |
ba5137b2 KVA |
1243 | compatible = "ti,gate-clock"; |
1244 | clocks = <&sys_32k_ck>; | |
1245 | #clock-cells = <0>; | |
1246 | reg = <0x13b0>; | |
1247 | ti,bit-shift = <8>; | |
1248 | }; | |
1249 | ||
00b0af5b KVA |
1250 | optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 { |
1251 | compatible = "ti,gate-clock"; | |
1252 | clocks = <&sys_32k_ck>; | |
1253 | #clock-cells = <0>; | |
1254 | reg = <0x13b8>; | |
1255 | ti,bit-shift = <8>; | |
1256 | }; | |
1257 | ||
a0289f91 K |
1258 | optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { |
1259 | compatible = "ti,divider-clock"; | |
1260 | clocks = <&apll_pcie_ck>; | |
1261 | #clock-cells = <0>; | |
1262 | reg = <0x021c>; | |
147e5413 | 1263 | ti,dividers = <2>, <1>; |
a0289f91 K |
1264 | ti,bit-shift = <8>; |
1265 | ti,max-div = <2>; | |
1266 | }; | |
1267 | ||
b700f42c | 1268 | optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { |
a0289f91 K |
1269 | compatible = "ti,gate-clock"; |
1270 | clocks = <&apll_pcie_ck>; | |
1271 | #clock-cells = <0>; | |
1272 | reg = <0x13b0>; | |
1273 | ti,bit-shift = <9>; | |
1274 | }; | |
1275 | ||
00b0af5b KVA |
1276 | optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 { |
1277 | compatible = "ti,gate-clock"; | |
1278 | clocks = <&apll_pcie_ck>; | |
1279 | #clock-cells = <0>; | |
1280 | reg = <0x13b8>; | |
1281 | ti,bit-shift = <9>; | |
1282 | }; | |
1283 | ||
b700f42c | 1284 | optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { |
a0289f91 K |
1285 | compatible = "ti,gate-clock"; |
1286 | clocks = <&optfclk_pciephy_div>; | |
1287 | #clock-cells = <0>; | |
1288 | reg = <0x13b0>; | |
1289 | ti,bit-shift = <10>; | |
1290 | }; | |
1291 | ||
00b0af5b KVA |
1292 | optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 { |
1293 | compatible = "ti,gate-clock"; | |
1294 | clocks = <&optfclk_pciephy_div>; | |
1295 | #clock-cells = <0>; | |
1296 | reg = <0x13b8>; | |
1297 | ti,bit-shift = <10>; | |
1298 | }; | |
1299 | ||
ee6c7507 TK |
1300 | apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { |
1301 | #clock-cells = <0>; | |
1302 | compatible = "fixed-factor-clock"; | |
1303 | clocks = <&apll_pcie_ck>; | |
1304 | clock-mult = <1>; | |
1305 | clock-div = <1>; | |
1306 | }; | |
1307 | ||
1308 | apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { | |
1309 | #clock-cells = <0>; | |
1310 | compatible = "fixed-factor-clock"; | |
1311 | clocks = <&apll_pcie_ck>; | |
1312 | clock-mult = <1>; | |
1313 | clock-div = <1>; | |
1314 | }; | |
1315 | ||
1316 | apll_pcie_m2_ck: apll_pcie_m2_ck { | |
1317 | #clock-cells = <0>; | |
c3be7acd | 1318 | compatible = "fixed-factor-clock"; |
ee6c7507 | 1319 | clocks = <&apll_pcie_ck>; |
c3be7acd K |
1320 | clock-mult = <1>; |
1321 | clock-div = <1>; | |
ee6c7507 TK |
1322 | }; |
1323 | ||
ca8a3d4e | 1324 | dpll_per_byp_mux: dpll_per_byp_mux@14c { |
d2192ea0 RK |
1325 | #clock-cells = <0>; |
1326 | compatible = "ti,mux-clock"; | |
1327 | clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; | |
1328 | ti,bit-shift = <23>; | |
1329 | reg = <0x014c>; | |
1330 | }; | |
1331 | ||
ca8a3d4e | 1332 | dpll_per_ck: dpll_per_ck@140 { |
ee6c7507 TK |
1333 | #clock-cells = <0>; |
1334 | compatible = "ti,omap4-dpll-clock"; | |
d2192ea0 | 1335 | clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; |
ee6c7507 TK |
1336 | reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; |
1337 | }; | |
1338 | ||
ca8a3d4e | 1339 | dpll_per_m2_ck: dpll_per_m2_ck@150 { |
ee6c7507 TK |
1340 | #clock-cells = <0>; |
1341 | compatible = "ti,divider-clock"; | |
1342 | clocks = <&dpll_per_ck>; | |
1343 | ti,max-div = <31>; | |
1344 | ti,autoidle-shift = <8>; | |
1345 | reg = <0x0150>; | |
1346 | ti,index-starts-at-one; | |
1347 | ti,invert-autoidle-bit; | |
1348 | }; | |
1349 | ||
1350 | func_96m_aon_dclk_div: func_96m_aon_dclk_div { | |
1351 | #clock-cells = <0>; | |
1352 | compatible = "fixed-factor-clock"; | |
1353 | clocks = <&dpll_per_m2_ck>; | |
1354 | clock-mult = <1>; | |
1355 | clock-div = <1>; | |
1356 | }; | |
1357 | ||
ca8a3d4e | 1358 | dpll_usb_byp_mux: dpll_usb_byp_mux@18c { |
d2192ea0 RK |
1359 | #clock-cells = <0>; |
1360 | compatible = "ti,mux-clock"; | |
1361 | clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; | |
1362 | ti,bit-shift = <23>; | |
1363 | reg = <0x018c>; | |
1364 | }; | |
1365 | ||
ca8a3d4e | 1366 | dpll_usb_ck: dpll_usb_ck@180 { |
ee6c7507 TK |
1367 | #clock-cells = <0>; |
1368 | compatible = "ti,omap4-dpll-j-type-clock"; | |
d2192ea0 | 1369 | clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; |
ee6c7507 TK |
1370 | reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; |
1371 | }; | |
1372 | ||
ca8a3d4e | 1373 | dpll_usb_m2_ck: dpll_usb_m2_ck@190 { |
ee6c7507 TK |
1374 | #clock-cells = <0>; |
1375 | compatible = "ti,divider-clock"; | |
1376 | clocks = <&dpll_usb_ck>; | |
1377 | ti,max-div = <127>; | |
1378 | ti,autoidle-shift = <8>; | |
1379 | reg = <0x0190>; | |
1380 | ti,index-starts-at-one; | |
1381 | ti,invert-autoidle-bit; | |
1382 | }; | |
1383 | ||
ca8a3d4e | 1384 | dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { |
ee6c7507 TK |
1385 | #clock-cells = <0>; |
1386 | compatible = "ti,divider-clock"; | |
1387 | clocks = <&dpll_pcie_ref_ck>; | |
1388 | ti,max-div = <127>; | |
1389 | ti,autoidle-shift = <8>; | |
1390 | reg = <0x0210>; | |
1391 | ti,index-starts-at-one; | |
1392 | ti,invert-autoidle-bit; | |
1393 | }; | |
1394 | ||
1395 | dpll_per_x2_ck: dpll_per_x2_ck { | |
1396 | #clock-cells = <0>; | |
1397 | compatible = "ti,omap4-dpll-x2-clock"; | |
1398 | clocks = <&dpll_per_ck>; | |
1399 | }; | |
1400 | ||
ca8a3d4e | 1401 | dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { |
ee6c7507 TK |
1402 | #clock-cells = <0>; |
1403 | compatible = "ti,divider-clock"; | |
1404 | clocks = <&dpll_per_x2_ck>; | |
1405 | ti,max-div = <63>; | |
1406 | ti,autoidle-shift = <8>; | |
1407 | reg = <0x0158>; | |
1408 | ti,index-starts-at-one; | |
1409 | ti,invert-autoidle-bit; | |
1410 | }; | |
1411 | ||
ca8a3d4e | 1412 | dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { |
ee6c7507 TK |
1413 | #clock-cells = <0>; |
1414 | compatible = "ti,divider-clock"; | |
1415 | clocks = <&dpll_per_x2_ck>; | |
1416 | ti,max-div = <63>; | |
1417 | ti,autoidle-shift = <8>; | |
1418 | reg = <0x015c>; | |
1419 | ti,index-starts-at-one; | |
1420 | ti,invert-autoidle-bit; | |
1421 | }; | |
1422 | ||
ca8a3d4e | 1423 | dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { |
ee6c7507 TK |
1424 | #clock-cells = <0>; |
1425 | compatible = "ti,divider-clock"; | |
1426 | clocks = <&dpll_per_x2_ck>; | |
1427 | ti,max-div = <63>; | |
1428 | ti,autoidle-shift = <8>; | |
1429 | reg = <0x0160>; | |
1430 | ti,index-starts-at-one; | |
1431 | ti,invert-autoidle-bit; | |
1432 | }; | |
1433 | ||
ca8a3d4e | 1434 | dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { |
ee6c7507 TK |
1435 | #clock-cells = <0>; |
1436 | compatible = "ti,divider-clock"; | |
1437 | clocks = <&dpll_per_x2_ck>; | |
1438 | ti,max-div = <63>; | |
1439 | ti,autoidle-shift = <8>; | |
1440 | reg = <0x0164>; | |
1441 | ti,index-starts-at-one; | |
1442 | ti,invert-autoidle-bit; | |
1443 | }; | |
1444 | ||
ca8a3d4e | 1445 | dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { |
ee6c7507 TK |
1446 | #clock-cells = <0>; |
1447 | compatible = "ti,divider-clock"; | |
1448 | clocks = <&dpll_per_x2_ck>; | |
1449 | ti,max-div = <31>; | |
1450 | ti,autoidle-shift = <8>; | |
1451 | reg = <0x0150>; | |
1452 | ti,index-starts-at-one; | |
1453 | ti,invert-autoidle-bit; | |
1454 | }; | |
1455 | ||
1456 | dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { | |
1457 | #clock-cells = <0>; | |
1458 | compatible = "fixed-factor-clock"; | |
1459 | clocks = <&dpll_usb_ck>; | |
1460 | clock-mult = <1>; | |
1461 | clock-div = <1>; | |
1462 | }; | |
1463 | ||
1464 | func_128m_clk: func_128m_clk { | |
1465 | #clock-cells = <0>; | |
1466 | compatible = "fixed-factor-clock"; | |
1467 | clocks = <&dpll_per_h11x2_ck>; | |
1468 | clock-mult = <1>; | |
1469 | clock-div = <2>; | |
1470 | }; | |
1471 | ||
1472 | func_12m_fclk: func_12m_fclk { | |
1473 | #clock-cells = <0>; | |
1474 | compatible = "fixed-factor-clock"; | |
1475 | clocks = <&dpll_per_m2x2_ck>; | |
1476 | clock-mult = <1>; | |
1477 | clock-div = <16>; | |
1478 | }; | |
1479 | ||
1480 | func_24m_clk: func_24m_clk { | |
1481 | #clock-cells = <0>; | |
1482 | compatible = "fixed-factor-clock"; | |
1483 | clocks = <&dpll_per_m2_ck>; | |
1484 | clock-mult = <1>; | |
1485 | clock-div = <4>; | |
1486 | }; | |
1487 | ||
1488 | func_48m_fclk: func_48m_fclk { | |
1489 | #clock-cells = <0>; | |
1490 | compatible = "fixed-factor-clock"; | |
1491 | clocks = <&dpll_per_m2x2_ck>; | |
1492 | clock-mult = <1>; | |
1493 | clock-div = <4>; | |
1494 | }; | |
1495 | ||
1496 | func_96m_fclk: func_96m_fclk { | |
1497 | #clock-cells = <0>; | |
1498 | compatible = "fixed-factor-clock"; | |
1499 | clocks = <&dpll_per_m2x2_ck>; | |
1500 | clock-mult = <1>; | |
1501 | clock-div = <2>; | |
1502 | }; | |
1503 | ||
ca8a3d4e | 1504 | l3init_60m_fclk: l3init_60m_fclk@104 { |
ee6c7507 TK |
1505 | #clock-cells = <0>; |
1506 | compatible = "ti,divider-clock"; | |
1507 | clocks = <&dpll_usb_m2_ck>; | |
1508 | reg = <0x0104>; | |
1509 | ti,dividers = <1>, <8>; | |
1510 | }; | |
1511 | ||
ca8a3d4e | 1512 | clkout2_clk: clkout2_clk@6b0 { |
a7390ebe PU |
1513 | #clock-cells = <0>; |
1514 | compatible = "ti,gate-clock"; | |
1515 | clocks = <&clkoutmux2_clk_mux>; | |
1516 | ti,bit-shift = <8>; | |
1517 | reg = <0x06b0>; | |
1518 | }; | |
1519 | ||
ca8a3d4e | 1520 | l3init_960m_gfclk: l3init_960m_gfclk@6c0 { |
032d7745 RQ |
1521 | #clock-cells = <0>; |
1522 | compatible = "ti,gate-clock"; | |
1523 | clocks = <&dpll_usb_clkdcoldo>; | |
1524 | ti,bit-shift = <8>; | |
1525 | reg = <0x06c0>; | |
1526 | }; | |
1527 | ||
ca8a3d4e | 1528 | dss_32khz_clk: dss_32khz_clk@1120 { |
ee6c7507 TK |
1529 | #clock-cells = <0>; |
1530 | compatible = "ti,gate-clock"; | |
1531 | clocks = <&sys_32k_ck>; | |
1532 | ti,bit-shift = <11>; | |
1533 | reg = <0x1120>; | |
1534 | }; | |
1535 | ||
ca8a3d4e | 1536 | dss_48mhz_clk: dss_48mhz_clk@1120 { |
ee6c7507 TK |
1537 | #clock-cells = <0>; |
1538 | compatible = "ti,gate-clock"; | |
1539 | clocks = <&func_48m_fclk>; | |
1540 | ti,bit-shift = <9>; | |
1541 | reg = <0x1120>; | |
1542 | }; | |
1543 | ||
ca8a3d4e | 1544 | dss_dss_clk: dss_dss_clk@1120 { |
ee6c7507 TK |
1545 | #clock-cells = <0>; |
1546 | compatible = "ti,gate-clock"; | |
1547 | clocks = <&dpll_per_h12x2_ck>; | |
1548 | ti,bit-shift = <8>; | |
1549 | reg = <0x1120>; | |
b21a9c3e | 1550 | ti,set-rate-parent; |
ee6c7507 TK |
1551 | }; |
1552 | ||
ca8a3d4e | 1553 | dss_hdmi_clk: dss_hdmi_clk@1120 { |
ee6c7507 TK |
1554 | #clock-cells = <0>; |
1555 | compatible = "ti,gate-clock"; | |
1556 | clocks = <&hdmi_dpll_clk_mux>; | |
1557 | ti,bit-shift = <10>; | |
1558 | reg = <0x1120>; | |
1559 | }; | |
1560 | ||
ca8a3d4e | 1561 | dss_video1_clk: dss_video1_clk@1120 { |
ee6c7507 TK |
1562 | #clock-cells = <0>; |
1563 | compatible = "ti,gate-clock"; | |
1564 | clocks = <&video1_dpll_clk_mux>; | |
1565 | ti,bit-shift = <12>; | |
1566 | reg = <0x1120>; | |
1567 | }; | |
1568 | ||
ca8a3d4e | 1569 | dss_video2_clk: dss_video2_clk@1120 { |
ee6c7507 TK |
1570 | #clock-cells = <0>; |
1571 | compatible = "ti,gate-clock"; | |
1572 | clocks = <&video2_dpll_clk_mux>; | |
1573 | ti,bit-shift = <13>; | |
1574 | reg = <0x1120>; | |
1575 | }; | |
1576 | ||
ca8a3d4e | 1577 | gpio2_dbclk: gpio2_dbclk@1760 { |
ee6c7507 TK |
1578 | #clock-cells = <0>; |
1579 | compatible = "ti,gate-clock"; | |
1580 | clocks = <&sys_32k_ck>; | |
1581 | ti,bit-shift = <8>; | |
1582 | reg = <0x1760>; | |
1583 | }; | |
1584 | ||
ca8a3d4e | 1585 | gpio3_dbclk: gpio3_dbclk@1768 { |
ee6c7507 TK |
1586 | #clock-cells = <0>; |
1587 | compatible = "ti,gate-clock"; | |
1588 | clocks = <&sys_32k_ck>; | |
1589 | ti,bit-shift = <8>; | |
1590 | reg = <0x1768>; | |
1591 | }; | |
1592 | ||
ca8a3d4e | 1593 | gpio4_dbclk: gpio4_dbclk@1770 { |
ee6c7507 TK |
1594 | #clock-cells = <0>; |
1595 | compatible = "ti,gate-clock"; | |
1596 | clocks = <&sys_32k_ck>; | |
1597 | ti,bit-shift = <8>; | |
1598 | reg = <0x1770>; | |
1599 | }; | |
1600 | ||
ca8a3d4e | 1601 | gpio5_dbclk: gpio5_dbclk@1778 { |
ee6c7507 TK |
1602 | #clock-cells = <0>; |
1603 | compatible = "ti,gate-clock"; | |
1604 | clocks = <&sys_32k_ck>; | |
1605 | ti,bit-shift = <8>; | |
1606 | reg = <0x1778>; | |
1607 | }; | |
1608 | ||
ca8a3d4e | 1609 | gpio6_dbclk: gpio6_dbclk@1780 { |
ee6c7507 TK |
1610 | #clock-cells = <0>; |
1611 | compatible = "ti,gate-clock"; | |
1612 | clocks = <&sys_32k_ck>; | |
1613 | ti,bit-shift = <8>; | |
1614 | reg = <0x1780>; | |
1615 | }; | |
1616 | ||
ca8a3d4e | 1617 | gpio7_dbclk: gpio7_dbclk@1810 { |
ee6c7507 TK |
1618 | #clock-cells = <0>; |
1619 | compatible = "ti,gate-clock"; | |
1620 | clocks = <&sys_32k_ck>; | |
1621 | ti,bit-shift = <8>; | |
1622 | reg = <0x1810>; | |
1623 | }; | |
1624 | ||
ca8a3d4e | 1625 | gpio8_dbclk: gpio8_dbclk@1818 { |
ee6c7507 TK |
1626 | #clock-cells = <0>; |
1627 | compatible = "ti,gate-clock"; | |
1628 | clocks = <&sys_32k_ck>; | |
1629 | ti,bit-shift = <8>; | |
1630 | reg = <0x1818>; | |
1631 | }; | |
1632 | ||
ca8a3d4e | 1633 | mmc1_clk32k: mmc1_clk32k@1328 { |
ee6c7507 TK |
1634 | #clock-cells = <0>; |
1635 | compatible = "ti,gate-clock"; | |
1636 | clocks = <&sys_32k_ck>; | |
1637 | ti,bit-shift = <8>; | |
1638 | reg = <0x1328>; | |
1639 | }; | |
1640 | ||
ca8a3d4e | 1641 | mmc2_clk32k: mmc2_clk32k@1330 { |
ee6c7507 TK |
1642 | #clock-cells = <0>; |
1643 | compatible = "ti,gate-clock"; | |
1644 | clocks = <&sys_32k_ck>; | |
1645 | ti,bit-shift = <8>; | |
1646 | reg = <0x1330>; | |
1647 | }; | |
1648 | ||
ca8a3d4e | 1649 | mmc3_clk32k: mmc3_clk32k@1820 { |
ee6c7507 TK |
1650 | #clock-cells = <0>; |
1651 | compatible = "ti,gate-clock"; | |
1652 | clocks = <&sys_32k_ck>; | |
1653 | ti,bit-shift = <8>; | |
1654 | reg = <0x1820>; | |
1655 | }; | |
1656 | ||
ca8a3d4e | 1657 | mmc4_clk32k: mmc4_clk32k@1828 { |
ee6c7507 TK |
1658 | #clock-cells = <0>; |
1659 | compatible = "ti,gate-clock"; | |
1660 | clocks = <&sys_32k_ck>; | |
1661 | ti,bit-shift = <8>; | |
1662 | reg = <0x1828>; | |
1663 | }; | |
1664 | ||
ca8a3d4e | 1665 | sata_ref_clk: sata_ref_clk@1388 { |
ee6c7507 TK |
1666 | #clock-cells = <0>; |
1667 | compatible = "ti,gate-clock"; | |
1668 | clocks = <&sys_clkin1>; | |
1669 | ti,bit-shift = <8>; | |
1670 | reg = <0x1388>; | |
1671 | }; | |
1672 | ||
ca8a3d4e | 1673 | usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 { |
ee6c7507 TK |
1674 | #clock-cells = <0>; |
1675 | compatible = "ti,gate-clock"; | |
032d7745 | 1676 | clocks = <&l3init_960m_gfclk>; |
ee6c7507 TK |
1677 | ti,bit-shift = <8>; |
1678 | reg = <0x13f0>; | |
1679 | }; | |
1680 | ||
ca8a3d4e | 1681 | usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 { |
ee6c7507 TK |
1682 | #clock-cells = <0>; |
1683 | compatible = "ti,gate-clock"; | |
032d7745 | 1684 | clocks = <&l3init_960m_gfclk>; |
ee6c7507 TK |
1685 | ti,bit-shift = <8>; |
1686 | reg = <0x1340>; | |
1687 | }; | |
1688 | ||
ca8a3d4e | 1689 | usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { |
ee6c7507 TK |
1690 | #clock-cells = <0>; |
1691 | compatible = "ti,gate-clock"; | |
1692 | clocks = <&sys_32k_ck>; | |
1693 | ti,bit-shift = <8>; | |
1694 | reg = <0x0640>; | |
1695 | }; | |
1696 | ||
ca8a3d4e | 1697 | usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { |
ee6c7507 TK |
1698 | #clock-cells = <0>; |
1699 | compatible = "ti,gate-clock"; | |
1700 | clocks = <&sys_32k_ck>; | |
1701 | ti,bit-shift = <8>; | |
1702 | reg = <0x0688>; | |
1703 | }; | |
1704 | ||
ca8a3d4e | 1705 | usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { |
ee6c7507 TK |
1706 | #clock-cells = <0>; |
1707 | compatible = "ti,gate-clock"; | |
1708 | clocks = <&sys_32k_ck>; | |
1709 | ti,bit-shift = <8>; | |
1710 | reg = <0x0698>; | |
1711 | }; | |
1712 | ||
ca8a3d4e | 1713 | atl_dpll_clk_mux: atl_dpll_clk_mux@c00 { |
ee6c7507 TK |
1714 | #clock-cells = <0>; |
1715 | compatible = "ti,mux-clock"; | |
1716 | clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>; | |
1717 | ti,bit-shift = <24>; | |
1718 | reg = <0x0c00>; | |
1719 | }; | |
1720 | ||
ca8a3d4e | 1721 | atl_gfclk_mux: atl_gfclk_mux@c00 { |
ee6c7507 TK |
1722 | #clock-cells = <0>; |
1723 | compatible = "ti,mux-clock"; | |
1724 | clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>; | |
1725 | ti,bit-shift = <26>; | |
1726 | reg = <0x0c00>; | |
1727 | }; | |
1728 | ||
dbb9c196 | 1729 | rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { |
ee6c7507 | 1730 | #clock-cells = <0>; |
dbb9c196 S |
1731 | compatible = "ti,mux-clock"; |
1732 | clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; | |
ee6c7507 TK |
1733 | ti,bit-shift = <24>; |
1734 | reg = <0x13d0>; | |
dbb9c196 S |
1735 | }; |
1736 | ||
ca8a3d4e | 1737 | gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { |
ee6c7507 TK |
1738 | #clock-cells = <0>; |
1739 | compatible = "ti,mux-clock"; | |
1740 | clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>; | |
1741 | ti,bit-shift = <25>; | |
1742 | reg = <0x13d0>; | |
1743 | }; | |
1744 | ||
ca8a3d4e | 1745 | gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { |
ee6c7507 TK |
1746 | #clock-cells = <0>; |
1747 | compatible = "ti,mux-clock"; | |
1748 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; | |
1749 | ti,bit-shift = <24>; | |
1750 | reg = <0x1220>; | |
1751 | }; | |
1752 | ||
ca8a3d4e | 1753 | gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { |
ee6c7507 TK |
1754 | #clock-cells = <0>; |
1755 | compatible = "ti,mux-clock"; | |
1756 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; | |
1757 | ti,bit-shift = <26>; | |
1758 | reg = <0x1220>; | |
1759 | }; | |
1760 | ||
ca8a3d4e | 1761 | l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { |
ee6c7507 TK |
1762 | #clock-cells = <0>; |
1763 | compatible = "ti,divider-clock"; | |
1764 | clocks = <&wkupaon_iclk_mux>; | |
1765 | ti,bit-shift = <24>; | |
1766 | reg = <0x0e50>; | |
1767 | ti,dividers = <8>, <16>, <32>; | |
1768 | }; | |
1769 | ||
ca8a3d4e | 1770 | mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 { |
ee6c7507 TK |
1771 | #clock-cells = <0>; |
1772 | compatible = "ti,mux-clock"; | |
0cccd919 | 1773 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
1774 | ti,bit-shift = <28>; |
1775 | reg = <0x1860>; | |
1776 | }; | |
1777 | ||
ca8a3d4e | 1778 | mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 { |
ee6c7507 TK |
1779 | #clock-cells = <0>; |
1780 | compatible = "ti,mux-clock"; | |
0cccd919 | 1781 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
8c0b4fd8 | 1782 | ti,bit-shift = <24>; |
ee6c7507 TK |
1783 | reg = <0x1860>; |
1784 | }; | |
1785 | ||
ca8a3d4e | 1786 | mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 { |
ee6c7507 TK |
1787 | #clock-cells = <0>; |
1788 | compatible = "ti,mux-clock"; | |
1789 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
1790 | ti,bit-shift = <22>; | |
1791 | reg = <0x1860>; | |
1792 | }; | |
1793 | ||
ca8a3d4e | 1794 | mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 { |
ee6c7507 TK |
1795 | #clock-cells = <0>; |
1796 | compatible = "ti,mux-clock"; | |
0cccd919 | 1797 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
1798 | ti,bit-shift = <24>; |
1799 | reg = <0x1868>; | |
1800 | }; | |
1801 | ||
ca8a3d4e | 1802 | mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 { |
ee6c7507 TK |
1803 | #clock-cells = <0>; |
1804 | compatible = "ti,mux-clock"; | |
1805 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
1806 | ti,bit-shift = <22>; | |
1807 | reg = <0x1868>; | |
1808 | }; | |
1809 | ||
ca8a3d4e | 1810 | mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 { |
ee6c7507 TK |
1811 | #clock-cells = <0>; |
1812 | compatible = "ti,mux-clock"; | |
0cccd919 | 1813 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
1814 | ti,bit-shift = <24>; |
1815 | reg = <0x1898>; | |
1816 | }; | |
1817 | ||
ca8a3d4e | 1818 | mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 { |
ee6c7507 TK |
1819 | #clock-cells = <0>; |
1820 | compatible = "ti,mux-clock"; | |
1821 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
1822 | ti,bit-shift = <22>; | |
1823 | reg = <0x1898>; | |
1824 | }; | |
1825 | ||
ca8a3d4e | 1826 | mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 { |
ee6c7507 TK |
1827 | #clock-cells = <0>; |
1828 | compatible = "ti,mux-clock"; | |
0cccd919 | 1829 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
1830 | ti,bit-shift = <24>; |
1831 | reg = <0x1878>; | |
1832 | }; | |
1833 | ||
ca8a3d4e | 1834 | mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 { |
ee6c7507 TK |
1835 | #clock-cells = <0>; |
1836 | compatible = "ti,mux-clock"; | |
1837 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
1838 | ti,bit-shift = <22>; | |
1839 | reg = <0x1878>; | |
1840 | }; | |
1841 | ||
ca8a3d4e | 1842 | mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 { |
ee6c7507 TK |
1843 | #clock-cells = <0>; |
1844 | compatible = "ti,mux-clock"; | |
0cccd919 | 1845 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
1846 | ti,bit-shift = <24>; |
1847 | reg = <0x1904>; | |
1848 | }; | |
1849 | ||
ca8a3d4e | 1850 | mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 { |
ee6c7507 TK |
1851 | #clock-cells = <0>; |
1852 | compatible = "ti,mux-clock"; | |
1853 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
1854 | ti,bit-shift = <22>; | |
1855 | reg = <0x1904>; | |
1856 | }; | |
1857 | ||
ca8a3d4e | 1858 | mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 { |
ee6c7507 TK |
1859 | #clock-cells = <0>; |
1860 | compatible = "ti,mux-clock"; | |
0cccd919 | 1861 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
1862 | ti,bit-shift = <24>; |
1863 | reg = <0x1908>; | |
1864 | }; | |
1865 | ||
ca8a3d4e | 1866 | mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 { |
ee6c7507 TK |
1867 | #clock-cells = <0>; |
1868 | compatible = "ti,mux-clock"; | |
1869 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
1870 | ti,bit-shift = <22>; | |
1871 | reg = <0x1908>; | |
1872 | }; | |
1873 | ||
e56700b8 | 1874 | mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 { |
ee6c7507 TK |
1875 | #clock-cells = <0>; |
1876 | compatible = "ti,mux-clock"; | |
0cccd919 | 1877 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
ee6c7507 TK |
1878 | ti,bit-shift = <22>; |
1879 | reg = <0x1890>; | |
1880 | }; | |
1881 | ||
ca8a3d4e | 1882 | mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 { |
ee6c7507 TK |
1883 | #clock-cells = <0>; |
1884 | compatible = "ti,mux-clock"; | |
1885 | clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; | |
1886 | ti,bit-shift = <24>; | |
1887 | reg = <0x1890>; | |
1888 | }; | |
1889 | ||
ca8a3d4e | 1890 | mmc1_fclk_mux: mmc1_fclk_mux@1328 { |
ee6c7507 TK |
1891 | #clock-cells = <0>; |
1892 | compatible = "ti,mux-clock"; | |
1893 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
1894 | ti,bit-shift = <24>; | |
1895 | reg = <0x1328>; | |
1896 | }; | |
1897 | ||
ca8a3d4e | 1898 | mmc1_fclk_div: mmc1_fclk_div@1328 { |
ee6c7507 TK |
1899 | #clock-cells = <0>; |
1900 | compatible = "ti,divider-clock"; | |
1901 | clocks = <&mmc1_fclk_mux>; | |
1902 | ti,bit-shift = <25>; | |
1903 | ti,max-div = <4>; | |
1904 | reg = <0x1328>; | |
1905 | ti,index-power-of-two; | |
1906 | }; | |
1907 | ||
ca8a3d4e | 1908 | mmc2_fclk_mux: mmc2_fclk_mux@1330 { |
ee6c7507 TK |
1909 | #clock-cells = <0>; |
1910 | compatible = "ti,mux-clock"; | |
1911 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
1912 | ti,bit-shift = <24>; | |
1913 | reg = <0x1330>; | |
1914 | }; | |
1915 | ||
ca8a3d4e | 1916 | mmc2_fclk_div: mmc2_fclk_div@1330 { |
ee6c7507 TK |
1917 | #clock-cells = <0>; |
1918 | compatible = "ti,divider-clock"; | |
1919 | clocks = <&mmc2_fclk_mux>; | |
1920 | ti,bit-shift = <25>; | |
1921 | ti,max-div = <4>; | |
1922 | reg = <0x1330>; | |
1923 | ti,index-power-of-two; | |
1924 | }; | |
1925 | ||
ca8a3d4e | 1926 | mmc3_gfclk_mux: mmc3_gfclk_mux@1820 { |
ee6c7507 TK |
1927 | #clock-cells = <0>; |
1928 | compatible = "ti,mux-clock"; | |
1929 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
1930 | ti,bit-shift = <24>; | |
1931 | reg = <0x1820>; | |
1932 | }; | |
1933 | ||
ca8a3d4e | 1934 | mmc3_gfclk_div: mmc3_gfclk_div@1820 { |
ee6c7507 TK |
1935 | #clock-cells = <0>; |
1936 | compatible = "ti,divider-clock"; | |
1937 | clocks = <&mmc3_gfclk_mux>; | |
1938 | ti,bit-shift = <25>; | |
1939 | ti,max-div = <4>; | |
1940 | reg = <0x1820>; | |
1941 | ti,index-power-of-two; | |
1942 | }; | |
1943 | ||
ca8a3d4e | 1944 | mmc4_gfclk_mux: mmc4_gfclk_mux@1828 { |
ee6c7507 TK |
1945 | #clock-cells = <0>; |
1946 | compatible = "ti,mux-clock"; | |
1947 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
1948 | ti,bit-shift = <24>; | |
1949 | reg = <0x1828>; | |
1950 | }; | |
1951 | ||
ca8a3d4e | 1952 | mmc4_gfclk_div: mmc4_gfclk_div@1828 { |
ee6c7507 TK |
1953 | #clock-cells = <0>; |
1954 | compatible = "ti,divider-clock"; | |
1955 | clocks = <&mmc4_gfclk_mux>; | |
1956 | ti,bit-shift = <25>; | |
1957 | ti,max-div = <4>; | |
1958 | reg = <0x1828>; | |
1959 | ti,index-power-of-two; | |
1960 | }; | |
1961 | ||
ca8a3d4e | 1962 | qspi_gfclk_mux: qspi_gfclk_mux@1838 { |
ee6c7507 TK |
1963 | #clock-cells = <0>; |
1964 | compatible = "ti,mux-clock"; | |
1965 | clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>; | |
1966 | ti,bit-shift = <24>; | |
1967 | reg = <0x1838>; | |
1968 | }; | |
1969 | ||
ca8a3d4e | 1970 | qspi_gfclk_div: qspi_gfclk_div@1838 { |
ee6c7507 TK |
1971 | #clock-cells = <0>; |
1972 | compatible = "ti,divider-clock"; | |
1973 | clocks = <&qspi_gfclk_mux>; | |
1974 | ti,bit-shift = <25>; | |
1975 | ti,max-div = <4>; | |
1976 | reg = <0x1838>; | |
1977 | ti,index-power-of-two; | |
1978 | }; | |
1979 | ||
ca8a3d4e | 1980 | timer10_gfclk_mux: timer10_gfclk_mux@1728 { |
ee6c7507 TK |
1981 | #clock-cells = <0>; |
1982 | compatible = "ti,mux-clock"; | |
1983 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
1984 | ti,bit-shift = <24>; | |
1985 | reg = <0x1728>; | |
1986 | }; | |
1987 | ||
ca8a3d4e | 1988 | timer11_gfclk_mux: timer11_gfclk_mux@1730 { |
ee6c7507 TK |
1989 | #clock-cells = <0>; |
1990 | compatible = "ti,mux-clock"; | |
1991 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
1992 | ti,bit-shift = <24>; | |
1993 | reg = <0x1730>; | |
1994 | }; | |
1995 | ||
ca8a3d4e | 1996 | timer13_gfclk_mux: timer13_gfclk_mux@17c8 { |
ee6c7507 TK |
1997 | #clock-cells = <0>; |
1998 | compatible = "ti,mux-clock"; | |
1999 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
2000 | ti,bit-shift = <24>; | |
2001 | reg = <0x17c8>; | |
2002 | }; | |
2003 | ||
ca8a3d4e | 2004 | timer14_gfclk_mux: timer14_gfclk_mux@17d0 { |
ee6c7507 TK |
2005 | #clock-cells = <0>; |
2006 | compatible = "ti,mux-clock"; | |
2007 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
2008 | ti,bit-shift = <24>; | |
2009 | reg = <0x17d0>; | |
2010 | }; | |
2011 | ||
ca8a3d4e | 2012 | timer15_gfclk_mux: timer15_gfclk_mux@17d8 { |
ee6c7507 TK |
2013 | #clock-cells = <0>; |
2014 | compatible = "ti,mux-clock"; | |
2015 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
2016 | ti,bit-shift = <24>; | |
2017 | reg = <0x17d8>; | |
2018 | }; | |
2019 | ||
ca8a3d4e | 2020 | timer16_gfclk_mux: timer16_gfclk_mux@1830 { |
ee6c7507 TK |
2021 | #clock-cells = <0>; |
2022 | compatible = "ti,mux-clock"; | |
2023 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
2024 | ti,bit-shift = <24>; | |
2025 | reg = <0x1830>; | |
2026 | }; | |
2027 | ||
ca8a3d4e | 2028 | timer2_gfclk_mux: timer2_gfclk_mux@1738 { |
ee6c7507 TK |
2029 | #clock-cells = <0>; |
2030 | compatible = "ti,mux-clock"; | |
2031 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
2032 | ti,bit-shift = <24>; | |
2033 | reg = <0x1738>; | |
2034 | }; | |
2035 | ||
ca8a3d4e | 2036 | timer3_gfclk_mux: timer3_gfclk_mux@1740 { |
ee6c7507 TK |
2037 | #clock-cells = <0>; |
2038 | compatible = "ti,mux-clock"; | |
2039 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
2040 | ti,bit-shift = <24>; | |
2041 | reg = <0x1740>; | |
2042 | }; | |
2043 | ||
ca8a3d4e | 2044 | timer4_gfclk_mux: timer4_gfclk_mux@1748 { |
ee6c7507 TK |
2045 | #clock-cells = <0>; |
2046 | compatible = "ti,mux-clock"; | |
2047 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
2048 | ti,bit-shift = <24>; | |
2049 | reg = <0x1748>; | |
2050 | }; | |
2051 | ||
ca8a3d4e | 2052 | timer9_gfclk_mux: timer9_gfclk_mux@1750 { |
ee6c7507 TK |
2053 | #clock-cells = <0>; |
2054 | compatible = "ti,mux-clock"; | |
2055 | clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; | |
2056 | ti,bit-shift = <24>; | |
2057 | reg = <0x1750>; | |
2058 | }; | |
2059 | ||
ca8a3d4e | 2060 | uart1_gfclk_mux: uart1_gfclk_mux@1840 { |
ee6c7507 TK |
2061 | #clock-cells = <0>; |
2062 | compatible = "ti,mux-clock"; | |
2063 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
2064 | ti,bit-shift = <24>; | |
2065 | reg = <0x1840>; | |
2066 | }; | |
2067 | ||
ca8a3d4e | 2068 | uart2_gfclk_mux: uart2_gfclk_mux@1848 { |
ee6c7507 TK |
2069 | #clock-cells = <0>; |
2070 | compatible = "ti,mux-clock"; | |
2071 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
2072 | ti,bit-shift = <24>; | |
2073 | reg = <0x1848>; | |
2074 | }; | |
2075 | ||
ca8a3d4e | 2076 | uart3_gfclk_mux: uart3_gfclk_mux@1850 { |
ee6c7507 TK |
2077 | #clock-cells = <0>; |
2078 | compatible = "ti,mux-clock"; | |
2079 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
2080 | ti,bit-shift = <24>; | |
2081 | reg = <0x1850>; | |
2082 | }; | |
2083 | ||
ca8a3d4e | 2084 | uart4_gfclk_mux: uart4_gfclk_mux@1858 { |
ee6c7507 TK |
2085 | #clock-cells = <0>; |
2086 | compatible = "ti,mux-clock"; | |
2087 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
2088 | ti,bit-shift = <24>; | |
2089 | reg = <0x1858>; | |
2090 | }; | |
2091 | ||
ca8a3d4e | 2092 | uart5_gfclk_mux: uart5_gfclk_mux@1870 { |
ee6c7507 TK |
2093 | #clock-cells = <0>; |
2094 | compatible = "ti,mux-clock"; | |
2095 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
2096 | ti,bit-shift = <24>; | |
2097 | reg = <0x1870>; | |
2098 | }; | |
2099 | ||
ca8a3d4e | 2100 | uart7_gfclk_mux: uart7_gfclk_mux@18d0 { |
ee6c7507 TK |
2101 | #clock-cells = <0>; |
2102 | compatible = "ti,mux-clock"; | |
2103 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
2104 | ti,bit-shift = <24>; | |
2105 | reg = <0x18d0>; | |
2106 | }; | |
2107 | ||
ca8a3d4e | 2108 | uart8_gfclk_mux: uart8_gfclk_mux@18e0 { |
ee6c7507 TK |
2109 | #clock-cells = <0>; |
2110 | compatible = "ti,mux-clock"; | |
2111 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
2112 | ti,bit-shift = <24>; | |
2113 | reg = <0x18e0>; | |
2114 | }; | |
2115 | ||
ca8a3d4e | 2116 | uart9_gfclk_mux: uart9_gfclk_mux@18e8 { |
ee6c7507 TK |
2117 | #clock-cells = <0>; |
2118 | compatible = "ti,mux-clock"; | |
2119 | clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; | |
2120 | ti,bit-shift = <24>; | |
2121 | reg = <0x18e8>; | |
2122 | }; | |
2123 | ||
ca8a3d4e | 2124 | vip1_gclk_mux: vip1_gclk_mux@1020 { |
ee6c7507 TK |
2125 | #clock-cells = <0>; |
2126 | compatible = "ti,mux-clock"; | |
2127 | clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; | |
2128 | ti,bit-shift = <24>; | |
2129 | reg = <0x1020>; | |
2130 | }; | |
2131 | ||
ca8a3d4e | 2132 | vip2_gclk_mux: vip2_gclk_mux@1028 { |
ee6c7507 TK |
2133 | #clock-cells = <0>; |
2134 | compatible = "ti,mux-clock"; | |
2135 | clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; | |
2136 | ti,bit-shift = <24>; | |
2137 | reg = <0x1028>; | |
2138 | }; | |
2139 | ||
ca8a3d4e | 2140 | vip3_gclk_mux: vip3_gclk_mux@1030 { |
ee6c7507 TK |
2141 | #clock-cells = <0>; |
2142 | compatible = "ti,mux-clock"; | |
2143 | clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; | |
2144 | ti,bit-shift = <24>; | |
2145 | reg = <0x1030>; | |
2146 | }; | |
2147 | }; | |
2148 | ||
2149 | &cm_core_clockdomains { | |
2150 | coreaon_clkdm: coreaon_clkdm { | |
2151 | compatible = "ti,clockdomain"; | |
2152 | clocks = <&dpll_usb_ck>; | |
2153 | }; | |
2154 | }; | |
2d5a3c80 TV |
2155 | |
2156 | &scm_conf_clocks { | |
ca8a3d4e | 2157 | dss_deshdcp_clk: dss_deshdcp_clk@558 { |
2d5a3c80 TV |
2158 | #clock-cells = <0>; |
2159 | compatible = "ti,gate-clock"; | |
2160 | clocks = <&l3_iclk_div>; | |
2161 | ti,bit-shift = <0>; | |
2162 | reg = <0x558>; | |
2163 | }; | |
c60f9e29 | 2164 | |
ca8a3d4e | 2165 | ehrpwm0_tbclk: ehrpwm0_tbclk@558 { |
c60f9e29 V |
2166 | #clock-cells = <0>; |
2167 | compatible = "ti,gate-clock"; | |
2168 | clocks = <&l4_root_clk_div>; | |
2169 | ti,bit-shift = <20>; | |
2170 | reg = <0x0558>; | |
2171 | }; | |
2172 | ||
ca8a3d4e | 2173 | ehrpwm1_tbclk: ehrpwm1_tbclk@558 { |
c60f9e29 V |
2174 | #clock-cells = <0>; |
2175 | compatible = "ti,gate-clock"; | |
2176 | clocks = <&l4_root_clk_div>; | |
2177 | ti,bit-shift = <21>; | |
2178 | reg = <0x0558>; | |
2179 | }; | |
2180 | ||
ca8a3d4e | 2181 | ehrpwm2_tbclk: ehrpwm2_tbclk@558 { |
c60f9e29 V |
2182 | #clock-cells = <0>; |
2183 | compatible = "ti,gate-clock"; | |
2184 | clocks = <&l4_root_clk_div>; | |
2185 | ti,bit-shift = <22>; | |
2186 | reg = <0x0558>; | |
2187 | }; | |
eea08802 K |
2188 | |
2189 | sys_32k_ck: sys_32k_ck { | |
2190 | #clock-cells = <0>; | |
2191 | compatible = "ti,mux-clock"; | |
2192 | clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; | |
2193 | ti,bit-shift = <8>; | |
2194 | reg = <0x6c4>; | |
2195 | }; | |
2d5a3c80 | 2196 | }; |