[linux-2.6-block.git] / arch / arm / boot / dts / dra72-evm-common.dtsi

/*
 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>

/ {
	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";

	aliases {
		display0 = &hdmi0;
	};

	chosen {
		stdout-path = &uart1;
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_5v0: fixedregulator-evm5v0 {
		/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_3v3_sw: fixedregulator-evm_3v3 {
		/* TPS22965DSG */
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vsys_3v3>;
		regulator-always-on;
		regulator-boot-on;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		/* TPS77018DBVT */
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd";
		vin-supply = <&evm_3v3_sw>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	evm_3v3_sd: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_3v3_sw>;
		enable-active-high;
		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb1: extcon_usb1 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb2: extcon_usb2 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	};

	hdmi0: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};

	tpd12s015: encoder {
		compatible = "ti,tpd12s015";

		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	sound0: sound0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-EVM";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line Out",
			"Microphone", "Mic Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",       "HPLOUT",
			"Headphone Jack",       "HPROUT",
			"Line Out",		"LLOUT",
			"Line Out",		"RLOUT",
			"MIC3L",		"Mic Jack",
			"MIC3R",		"Mic Jack",
			"Mic Jack",		"Mic Bias",
			"LINE1L",               "Line In",
			"LINE1R",               "Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound0_master>;
		simple-audio-card,frame-master = <&sound0_master>;
		simple-audio-card,bitclock-inversion;

		sound0_master: simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
			system-clock-frequency = <5644800>;
		};

		simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			clocks = <&atl_clkin2_ck>;
		};
	};
};

&dra7_pmx_core {
	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)	/* mmc1sdcd.gpio219 */
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
			DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
		>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
			DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP)	/* wakeup0.off */
		>;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_lcd: gpio@20 {
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	pcf_gpio_21: gpio@21 {
		compatible = "ti,pcf8575", "nxp,pcf8575";
		reg = <0x21>;
		lines-initial-states = <0x1408>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	tlv320aic3106: tlv320aic3106@19 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x19>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		/* 2.0V */
		status = "okay";

		/* Regulators */
		AVDD-supply = <&evm_3v3_sw>;
		IOVDD-supply = <&evm_3v3_sw>;
		DRVDD-supply = <&evm_3v3_sw>;
		DVDD-supply = <&aic_dvdd>;
	};
};

&i2c5 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_hdmi: pcf8575@26 {
		compatible = "ti,pcf8575", "nxp,pcf8575";
		reg = <0x26>;
		gpio-controller;
		#gpio-cells = <2>;
		/*
		 * initial state is used here to keep the mdio interface
		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
		 * VIN2_S0 driven high otherwise Ethernet stops working
		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
		 */
		lines-initial-states = <0x0f2b>;

		p1 {
			/* vin6_sel_s0: high: VIN6, low: audio */
			gpio-hog;
			gpios = <1 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "vin6_sel_s0";
		};
	};
};

&uart1 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			      <&dra7_pmx_core 0x3e0>;
};

&elm {
	status = "okay";
};

&gpmc {
	/*
	 * For the existing IOdelay configuration via U-Boot we don't
	 * support NAND on dra72-evm. Keep it disabled. Enabling it
	 * requires a different configuration by U-Boot.
	 */
	status = "disabled";
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		/* To use NAND, DIP switch SW5 must be set like so:
		 * SW5.1 (NAND_SELn) = ON (LOW)
		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
		 */
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x000020000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00020000 0x00020000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00040000 0x00020000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x00060000 0x00020000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00080000 0x00040000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x000c0000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x001c0000 0x00020000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x001e0000 0x00020000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00200000 0x00800000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x0f600000>;
		};
	};
};

&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&usb1 {
	dr_mode = "otg";
	extcon = <&extcon_usb1>;
};

&usb2 {
	dr_mode = "host";
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins_default>;
	vmmc-supply = <&evm_3v3_sd>;
	bus-width = <4>;
	/*
	 * SDCD signal is not being used here - using the fact that GPIO mode
	 * is a viable alternative
	 */
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	max-frequency = <192000000>;
};

&mmc2 {
	/* SW5-3 in ON position */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins_default>;
	bus-width = <8>;
	ti,non-removable;
	max-frequency = <192000000>;
};

&mac {
	status = "okay";
};

&dcan1 {
	status = "ok";
	pinctrl-names = "default", "sleep", "active";
	pinctrl-0 = <&dcan1_pins_sleep>;
	pinctrl-1 = <&dcan1_pins_sleep>;
	pinctrl-2 = <&dcan1_pins_default>;
};

&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	m25p80@0 {
		compatible = "s25fl256s1";
		spi-max-frequency = <76800000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000010000>;
		};
		partition@1 {
			label = "QSPI.SPL.backup1";
			reg = <0x00010000 0x00010000>;
		};
		partition@2 {
			label = "QSPI.SPL.backup2";
			reg = <0x00020000 0x00010000>;
		};
		partition@3 {
			label = "QSPI.SPL.backup3";
			reg = <0x00030000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@5 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@6 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@7 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@8 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@9 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x01620000>;
		};
	};
};

&dss {
	status = "ok";
};

&hdmi {
	status = "ok";

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_gfclk_mux>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp3 {
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp3_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	status = "okay";

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializer */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "okay";
	};
};
Commit	Line	Data
a4240d3a NM	1	/*
	2	* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	/dts-v1/;
	9
	10	#include "dra72x.dtsi"
	11	#include <dt-bindings/gpio/gpio.h>
	12	#include <dt-bindings/clk/ti-dra7-atl.h>
	13
	14	/ {
	15	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
	16
	17	aliases {
	18	display0 = &hdmi0;
	19	};
	20
220fbc13 LV	21	chosen {
	22	stdout-path = &uart1;
	23	};
	24
e9a05fbd LV	25	evm_12v0: fixedregulator-evm12v0 {
	26	/* main supply */
	27	compatible = "regulator-fixed";
	28	regulator-name = "evm_12v0";
	29	regulator-min-microvolt = <12000000>;
	30	regulator-max-microvolt = <12000000>;
	31	regulator-always-on;
	32	regulator-boot-on;
	33	};
	34
	35	evm_5v0: fixedregulator-evm5v0 {
6eebfeb9 NM	36	/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
6eebfeb9 NM	37	/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
e9a05fbd LV	38	compatible = "regulator-fixed";
	39	regulator-name = "evm_5v0";
	40	regulator-min-microvolt = <5000000>;
	41	regulator-max-microvolt = <5000000>;
	42	vin-supply = <&evm_12v0>;
	43	regulator-always-on;
	44	regulator-boot-on;
	45	};
	46
	47	vsys_3v3: fixedregulator-vsys3v3 {
6eebfeb9 NM	48	/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
6eebfeb9 NM	49	/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
e9a05fbd LV	50	compatible = "regulator-fixed";
	51	regulator-name = "vsys_3v3";
	52	regulator-min-microvolt = <3300000>;
	53	regulator-max-microvolt = <3300000>;
	54	vin-supply = <&evm_12v0>;
	55	regulator-always-on;
	56	regulator-boot-on;
	57	};
	58
7172e745	59	evm_3v3_sw: fixedregulator-evm_3v3 {
e9a05fbd	60	/* TPS22965DSG */
a4240d3a NM	61	compatible = "regulator-fixed";
	62	regulator-name = "evm_3v3";
	63	regulator-min-microvolt = <3300000>;
	64	regulator-max-microvolt = <3300000>;
e9a05fbd LV	65	vin-supply = <&vsys_3v3>;
	66	regulator-always-on;
	67	regulator-boot-on;
a4240d3a NM	68	};
	69
	70	aic_dvdd: fixedregulator-aic_dvdd {
	71	/* TPS77018DBVT */
	72	compatible = "regulator-fixed";
	73	regulator-name = "aic_dvdd";
7172e745	74	vin-supply = <&evm_3v3_sw>;
a4240d3a NM	75	regulator-min-microvolt = <1800000>;
	76	regulator-max-microvolt = <1800000>;
	77	};
	78
	79	evm_3v3_sd: fixedregulator-sd {
	80	compatible = "regulator-fixed";
	81	regulator-name = "evm_3v3_sd";
	82	regulator-min-microvolt = <3300000>;
	83	regulator-max-microvolt = <3300000>;
e9a05fbd	84	vin-supply = <&evm_3v3_sw>;
a4240d3a NM	85	enable-active-high;
	86	gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
	87	};
	88
	89	extcon_usb1: extcon_usb1 {
	90	compatible = "linux,extcon-usb-gpio";
	91	id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
	92	};
	93
	94	extcon_usb2: extcon_usb2 {
	95	compatible = "linux,extcon-usb-gpio";
	96	id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	97	};
	98
	99	hdmi0: connector {
	100	compatible = "hdmi-connector";
	101	label = "hdmi";
	102
	103	type = "a";
	104
	105	port {
	106	hdmi_connector_in: endpoint {
	107	remote-endpoint = <&tpd12s015_out>;
	108	};
	109	};
	110	};
	111
	112	tpd12s015: encoder {
	113	compatible = "ti,tpd12s015";
	114
a4240d3a NM	115	gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
	116	<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
	117	<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
	118
	119	ports {
	120	#address-cells = <1>;
	121	#size-cells = <0>;
	122
	123	port@0 {
	124	reg = <0>;
	125
	126	tpd12s015_in: endpoint {
	127	remote-endpoint = <&hdmi_out>;
	128	};
	129	};
	130
	131	port@1 {
	132	reg = <1>;
	133
	134	tpd12s015_out: endpoint {
	135	remote-endpoint = <&hdmi_connector_in>;
	136	};
	137	};
	138	};
	139	};
	140
	141	sound0: sound0 {
	142	compatible = "simple-audio-card";
	143	simple-audio-card,name = "DRA7xx-EVM";
	144	simple-audio-card,widgets =
	145	"Headphone", "Headphone Jack",
	146	"Line", "Line Out",
	147	"Microphone", "Mic Jack",
	148	"Line", "Line In";
	149	simple-audio-card,routing =
	150	"Headphone Jack", "HPLOUT",
	151	"Headphone Jack", "HPROUT",
	152	"Line Out", "LLOUT",
	153	"Line Out", "RLOUT",
	154	"MIC3L", "Mic Jack",
	155	"MIC3R", "Mic Jack",
	156	"Mic Jack", "Mic Bias",
	157	"LINE1L", "Line In",
	158	"LINE1R", "Line In";
	159	simple-audio-card,format = "dsp_b";
	160	simple-audio-card,bitclock-master = <&sound0_master>;
	161	simple-audio-card,frame-master = <&sound0_master>;
	162	simple-audio-card,bitclock-inversion;
	163
	164	sound0_master: simple-audio-card,cpu {
	165	sound-dai = <&mcasp3>;
	166	system-clock-frequency = <5644800>;
	167	};
	168
	169	simple-audio-card,codec {
	170	sound-dai = <&tlv320aic3106>;
	171	clocks = <&atl_clkin2_ck>;
	172	};
	173	};
	174	};
	175
	176	&dra7_pmx_core {
a4240d3a NM	177	mmc1_pins_default: mmc1_pins_default {
	178	pinctrl-single,pins = <
	179	DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT \| MUX_MODE14) /* mmc1sdcd.gpio219 */
	180	DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_clk.clk */
	181	DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_cmd.cmd */
	182	DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat0.dat0 */
	183	DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat1.dat1 */
	184	DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat2.dat2 */
	185	DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat3.dat3 */
	186	>;
	187	};
	188
	189	mmc2_pins_default: mmc2_pins_default {
	190	pinctrl-single,pins = <
	191	DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk */
	192	DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
	193	DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
	194	DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
	195	DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
	196	DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
	197	DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
	198	DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
	199	DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
	200	DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
	201	>;
	202	};
	203
	204	dcan1_pins_default: dcan1_pins_default {
	205	pinctrl-single,pins = <
	206	DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* dcan1_tx */
	207	DRA7XX_CORE_IOPAD(0x3818, PULL_UP \| MUX_MODE1) /* wakeup0.dcan1_rx */
	208	>;
	209	};
	210
	211	dcan1_pins_sleep: dcan1_pins_sleep {
	212	pinctrl-single,pins = <
	213	DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 \| PULL_UP) /* dcan1_tx.off */
	214	DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 \| PULL_UP) /* wakeup0.off */
	215	>;
	216	};
a4240d3a NM	217	};
	218
	219	&i2c1 {
	220	status = "okay";
a4240d3a NM	221	clock-frequency = <400000>;
a4240d3a NM	222
d8e166b4 TV	223	pcf_lcd: gpio@20 {
	224	compatible = "nxp,pcf8575";
	225	reg = <0x20>;
	226	gpio-controller;
	227	#gpio-cells = <2>;
	228	interrupt-controller;
	229	#interrupt-cells = <2>;
	230	};
	231
a4240d3a	232	pcf_gpio_21: gpio@21 {
86f196f8	233	compatible = "ti,pcf8575", "nxp,pcf8575";
a4240d3a NM	234	reg = <0x21>;
	235	lines-initial-states = <0x1408>;
	236	gpio-controller;
	237	#gpio-cells = <2>;
	238	interrupt-controller;
	239	#interrupt-cells = <2>;
	240	};
	241
	242	tlv320aic3106: tlv320aic3106@19 {
	243	#sound-dai-cells = <0>;
	244	compatible = "ti,tlv320aic3106";
	245	reg = <0x19>;
	246	adc-settle-ms = <40>;
	247	ai3x-micbias-vg = <1>; /* 2.0V */
	248	status = "okay";
	249
	250	/* Regulators */
7172e745 MLC	251	AVDD-supply = <&evm_3v3_sw>;
	252	IOVDD-supply = <&evm_3v3_sw>;
	253	DRVDD-supply = <&evm_3v3_sw>;
a4240d3a NM	254	DVDD-supply = <&aic_dvdd>;
	255	};
	256	};
	257
	258	&i2c5 {
	259	status = "okay";
a4240d3a NM	260	clock-frequency = <400000>;
	261
	262	pcf_hdmi: pcf8575@26 {
86f196f8	263	compatible = "ti,pcf8575", "nxp,pcf8575";
a4240d3a NM	264	reg = <0x26>;
	265	gpio-controller;
	266	#gpio-cells = <2>;
	267	/*
	268	* initial state is used here to keep the mdio interface
	269	* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
	270	* VIN2_S0 driven high otherwise Ethernet stops working
	271	* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
	272	*/
	273	lines-initial-states = <0x0f2b>;
	274
	275	p1 {
	276	/* vin6_sel_s0: high: VIN6, low: audio */
	277	gpio-hog;
	278	gpios = <1 GPIO_ACTIVE_HIGH>;
	279	output-low;
	280	line-name = "vin6_sel_s0";
	281	};
	282	};
	283	};
	284
	285	&uart1 {
	286	status = "okay";
	287	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	288	<&dra7_pmx_core 0x3e0>;
	289	};
	290
	291	&elm {
	292	status = "okay";
	293	};
	294
	295	&gpmc {
1a8eca7f SN	296	/*
	297	* For the existing IOdelay configuration via U-Boot we don't
	298	* support NAND on dra72-evm. Keep it disabled. Enabling it
	299	* requires a different configuration by U-Boot.
	300	*/
	301	status = "disabled";
a4240d3a NM	302	ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
	303	nand@0,0 {
	304	/* To use NAND, DIP switch SW5 must be set like so:
	305	* SW5.1 (NAND_SELn) = ON (LOW)
	306	* SW5.9 (GPMC_WPN) = OFF (HIGH)
	307	*/
	308	compatible = "ti,omap2-nand";
	309	reg = <0 0 4>; /* device IO registers */
	310	interrupt-parent = <&gpmc>;
	311	interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
	312	<1 IRQ_TYPE_NONE>; /* termcount */
	313	rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
	314	ti,nand-ecc-opt = "bch8";
	315	ti,elm-id = <&elm>;
	316	nand-bus-width = <16>;
	317	gpmc,device-width = <2>;
	318	gpmc,sync-clk-ps = <0>;
	319	gpmc,cs-on-ns = <0>;
	320	gpmc,cs-rd-off-ns = <80>;
	321	gpmc,cs-wr-off-ns = <80>;
	322	gpmc,adv-on-ns = <0>;
	323	gpmc,adv-rd-off-ns = <60>;
	324	gpmc,adv-wr-off-ns = <60>;
	325	gpmc,we-on-ns = <10>;
	326	gpmc,we-off-ns = <50>;
	327	gpmc,oe-on-ns = <4>;
	328	gpmc,oe-off-ns = <40>;
	329	gpmc,access-ns = <40>;
	330	gpmc,wr-access-ns = <80>;
	331	gpmc,rd-cycle-ns = <80>;
	332	gpmc,wr-cycle-ns = <80>;
	333	gpmc,bus-turnaround-ns = <0>;
	334	gpmc,cycle2cycle-delay-ns = <0>;
	335	gpmc,clk-activation-ns = <0>;
	336	gpmc,wr-data-mux-bus-ns = <0>;
	337	/* MTD partition table */
	338	/* All SPL-* partitions are sized to minimal length
	339	* which can be independently programmable. For
	340	* NAND flash this is equal to size of erase-block */
	341	#address-cells = <1>;
	342	#size-cells = <1>;
	343	partition@0 {
	344	label = "NAND.SPL";
	345	reg = <0x00000000 0x000020000>;
	346	};
	347	partition@1 {
	348	label = "NAND.SPL.backup1";
	349	reg = <0x00020000 0x00020000>;
	350	};
	351	partition@2 {
	352	label = "NAND.SPL.backup2";
	353	reg = <0x00040000 0x00020000>;
	354	};
	355	partition@3 {
	356	label = "NAND.SPL.backup3";
	357	reg = <0x00060000 0x00020000>;
	358	};
	359	partition@4 {
	360	label = "NAND.u-boot-spl-os";
	361	reg = <0x00080000 0x00040000>;
	362	};
	363	partition@5 {
	364	label = "NAND.u-boot";
	365	reg = <0x000c0000 0x00100000>;
366	};
367	partition@6 {
368	label = "NAND.u-boot-env";
369	reg = <0x001c0000 0x00020000>;
370	};
371	partition@7 {
372	label = "NAND.u-boot-env.backup1";
373	reg = <0x001e0000 0x00020000>;
374	};
375	partition@8 {
376	label = "NAND.kernel";
377	reg = <0x00200000 0x00800000>;
378	};
379	partition@9 {
380	label = "NAND.file-system";
381	reg = <0x00a00000 0x0f600000>;
382	};
383	};
384	};
385
a4240d3a NM	386	&omap_dwc3_1 {
	387	extcon = <&extcon_usb1>;
	388	};
	389
	390	&omap_dwc3_2 {
	391	extcon = <&extcon_usb2>;
	392	};
	393
	394	&usb1 {
a6f627e2 RQ	395	dr_mode = "otg";
a6f627e2 RQ	396	extcon = <&extcon_usb1>;
a4240d3a NM	397	};
	398
	399	&usb2 {
	400	dr_mode = "host";
a4240d3a NM	401	};
	402
	403	&mmc1 {
	404	status = "okay";
	405	pinctrl-names = "default";
	406	pinctrl-0 = <&mmc1_pins_default>;
	407	vmmc-supply = <&evm_3v3_sd>;
a4240d3a NM	408	bus-width = <4>;
	409	/*
	410	* SDCD signal is not being used here - using the fact that GPIO mode
	411	* is a viable alternative
	412	*/
	413	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	414	max-frequency = <192000000>;
	415	};
	416
	417	&mmc2 {
	418	/* SW5-3 in ON position */
	419	status = "okay";
	420	pinctrl-names = "default";
	421	pinctrl-0 = <&mmc2_pins_default>;
a4240d3a NM	422	bus-width = <8>;
	423	ti,non-removable;
	424	max-frequency = <192000000>;
	425	};
	426
a4240d3a NM	427	&mac {
a4240d3a NM	428	status = "okay";
a4240d3a NM	429	};
	430
	431	&dcan1 {
	432	status = "ok";
	433	pinctrl-names = "default", "sleep", "active";
	434	pinctrl-0 = <&dcan1_pins_sleep>;
	435	pinctrl-1 = <&dcan1_pins_sleep>;
	436	pinctrl-2 = <&dcan1_pins_default>;
	437	};
	438
	439	&qspi {
	440	status = "okay";
a4240d3a	441
a0b83af0	442	spi-max-frequency = <76800000>;
a4240d3a NM	443	m25p80@0 {
a4240d3a NM	444	compatible = "s25fl256s1";
a0b83af0	445	spi-max-frequency = <76800000>;
a4240d3a NM	446	reg = <0>;
	447	spi-tx-bus-width = <1>;
	448	spi-rx-bus-width = <4>;
a4240d3a NM	449	#address-cells = <1>;
	450	#size-cells = <1>;
	451
	452	/* MTD partition table.
	453	* The ROM checks the first four physical blocks
	454	* for a valid file to boot and the flash here is
	455	* 64KiB block size.
	456	*/
	457	partition@0 {
	458	label = "QSPI.SPL";
	459	reg = <0x00000000 0x000010000>;
	460	};
	461	partition@1 {
	462	label = "QSPI.SPL.backup1";
	463	reg = <0x00010000 0x00010000>;
	464	};
	465	partition@2 {
	466	label = "QSPI.SPL.backup2";
	467	reg = <0x00020000 0x00010000>;
	468	};
	469	partition@3 {
	470	label = "QSPI.SPL.backup3";
	471	reg = <0x00030000 0x00010000>;
	472	};
	473	partition@4 {
	474	label = "QSPI.u-boot";
	475	reg = <0x00040000 0x00100000>;
	476	};
	477	partition@5 {
	478	label = "QSPI.u-boot-spl-os";
	479	reg = <0x00140000 0x00080000>;
	480	};
	481	partition@6 {
	482	label = "QSPI.u-boot-env";
	483	reg = <0x001c0000 0x00010000>;
	484	};
	485	partition@7 {
	486	label = "QSPI.u-boot-env.backup1";
	487	reg = <0x001d0000 0x0010000>;
	488	};
	489	partition@8 {
	490	label = "QSPI.kernel";
	491	reg = <0x001e0000 0x0800000>;
	492	};
	493	partition@9 {
	494	label = "QSPI.file-system";
	495	reg = <0x009e0000 0x01620000>;
	496	};
	497	};
	498	};
	499
	500	&dss {
	501	status = "ok";
a4240d3a NM	502	};
	503
	504	&hdmi {
	505	status = "ok";
	506
a4240d3a NM	507	port {
	508	hdmi_out: endpoint {
	509	remote-endpoint = <&tpd12s015_in>;
	510	};
	511	};
	512	};
	513
	514	&atl {
a4240d3a NM	515	assigned-clocks = <&abe_dpll_sys_clk_mux>,
	516	<&atl_gfclk_mux>,
	517	<&dpll_abe_ck>,
	518	<&dpll_abe_m2x2_ck>,
	519	<&atl_clkin2_ck>;
	520	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	521	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
	522
	523	status = "okay";
	524
	525	atl2 {
	526	bws = <DRA7_ATL_WS_MCASP2_FSX>;
	527	aws = <DRA7_ATL_WS_MCASP3_FSX>;
	528	};
	529	};
	530
	531	&mcasp3 {
	532	#sound-dai-cells = <0>;
a4240d3a NM	533
	534	assigned-clocks = <&mcasp3_ahclkx_mux>;
	535	assigned-clock-parents = <&atl_clkin2_ck>;
	536
	537	status = "okay";
	538
	539	op-mode = <0>; /* MCASP_IIS_MODE */
	540	tdm-slots = <2>;
	541	/* 4 serializer */
	542	serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
	543	1 2 0 0
	544	>;
	545	tx-num-evt = <32>;
	546	rx-num-evt = <32>;
	547	};
	548
	549	&mailbox5 {
	550	status = "okay";
	551	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
	552	status = "okay";
	553	};
	554	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
	555	status = "okay";
	556	};
	557	};
	558
	559	&mailbox6 {
	560	status = "okay";
	561	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
	562	status = "okay";
	563	};
	564	};