Commit | Line | Data |
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6e58b8f1 S |
1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
11 | #include <dt-bindings/pinctrl/dra.h> | |
12 | ||
13 | #include "skeleton.dtsi" | |
14 | ||
a46631c4 | 15 | #define MAX_SOURCES 400 |
a46631c4 | 16 | |
6e58b8f1 | 17 | / { |
dae320ec LV |
18 | #address-cells = <2>; |
19 | #size-cells = <2>; | |
6e58b8f1 S |
20 | |
21 | compatible = "ti,dra7xx"; | |
783d3186 | 22 | interrupt-parent = <&crossbar_mpu>; |
6e58b8f1 S |
23 | |
24 | aliases { | |
20b80942 NM |
25 | i2c0 = &i2c1; |
26 | i2c1 = &i2c2; | |
27 | i2c2 = &i2c3; | |
28 | i2c3 = &i2c4; | |
29 | i2c4 = &i2c5; | |
6e58b8f1 S |
30 | serial0 = &uart1; |
31 | serial1 = &uart2; | |
32 | serial2 = &uart3; | |
33 | serial3 = &uart4; | |
34 | serial4 = &uart5; | |
35 | serial5 = &uart6; | |
065bd7fe NM |
36 | serial6 = &uart7; |
37 | serial7 = &uart8; | |
38 | serial8 = &uart9; | |
39 | serial9 = &uart10; | |
ef9c5b69 M |
40 | ethernet0 = &cpsw_emac0; |
41 | ethernet1 = &cpsw_emac1; | |
9ec49b9f RQ |
42 | d_can0 = &dcan1; |
43 | d_can1 = &dcan2; | |
480b2b32 | 44 | spi0 = &qspi; |
6e58b8f1 S |
45 | }; |
46 | ||
6e58b8f1 S |
47 | timer { |
48 | compatible = "arm,armv7-timer"; | |
49 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
50 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
51 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
52 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
783d3186 | 53 | interrupt-parent = <&gic>; |
6e58b8f1 S |
54 | }; |
55 | ||
56 | gic: interrupt-controller@48211000 { | |
57 | compatible = "arm,cortex-a15-gic"; | |
58 | interrupt-controller; | |
59 | #interrupt-cells = <3>; | |
dae320ec LV |
60 | reg = <0x0 0x48211000 0x0 0x1000>, |
61 | <0x0 0x48212000 0x0 0x1000>, | |
62 | <0x0 0x48214000 0x0 0x2000>, | |
63 | <0x0 0x48216000 0x0 0x2000>; | |
6e58b8f1 | 64 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
783d3186 | 65 | interrupt-parent = <&gic>; |
6e58b8f1 S |
66 | }; |
67 | ||
7136d457 MZ |
68 | wakeupgen: interrupt-controller@48281000 { |
69 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; | |
70 | interrupt-controller; | |
71 | #interrupt-cells = <3>; | |
dae320ec | 72 | reg = <0x0 0x48281000 0x0 0x1000>; |
7136d457 | 73 | interrupt-parent = <&gic>; |
6e58b8f1 S |
74 | }; |
75 | ||
b82ffb33 DG |
76 | cpus { |
77 | #address-cells = <1>; | |
78 | #size-cells = <0>; | |
79 | ||
80 | cpu0: cpu@0 { | |
81 | device_type = "cpu"; | |
82 | compatible = "arm,cortex-a15"; | |
83 | reg = <0>; | |
84 | ||
f80bc97f DG |
85 | operating-points-v2 = <&cpu0_opp_table>; |
86 | ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>; | |
87 | ti,syscon-rev = <&scm_wkup 0x204>; | |
b82ffb33 DG |
88 | |
89 | clocks = <&dpll_mpu_ck>; | |
90 | clock-names = "cpu"; | |
91 | ||
92 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
93 | ||
94 | /* cooling options */ | |
95 | cooling-min-level = <0>; | |
96 | cooling-max-level = <2>; | |
97 | #cooling-cells = <2>; /* min followed by max */ | |
98 | }; | |
99 | }; | |
100 | ||
f80bc97f DG |
101 | cpu0_opp_table: opp_table0 { |
102 | compatible = "operating-points-v2"; | |
103 | opp-shared; | |
104 | ||
105 | opp_nom@1000000000 { | |
106 | opp-hz = /bits/ 64 <1000000000>; | |
107 | opp-microvolt = <1060000 850000 1150000>; | |
108 | opp-supported-hw = <0xFF 0x01>; | |
109 | opp-suspend; | |
110 | }; | |
111 | ||
112 | opp_od@1176000000 { | |
113 | opp-hz = /bits/ 64 <1176000000>; | |
114 | opp-microvolt = <1160000 885000 1160000>; | |
115 | opp-supported-hw = <0xFF 0x02>; | |
116 | }; | |
117 | }; | |
118 | ||
6e58b8f1 | 119 | /* |
5c5be9db | 120 | * The soc node represents the soc top level view. It is used for IPs |
6e58b8f1 S |
121 | * that are not memory mapped in the MPU view or for the MPU itself. |
122 | */ | |
123 | soc { | |
124 | compatible = "ti,omap-infra"; | |
125 | mpu { | |
126 | compatible = "ti,omap5-mpu"; | |
127 | ti,hwmods = "mpu"; | |
128 | }; | |
129 | }; | |
130 | ||
131 | /* | |
132 | * XXX: Use a flat representation of the SOC interconnect. | |
133 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 134 | * Since it will not bring real advantage to represent that in DT for |
6e58b8f1 S |
135 | * the moment, just use a fake OCP bus entry to represent the whole bus |
136 | * hierarchy. | |
137 | */ | |
138 | ocp { | |
fba387a6 | 139 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
6e58b8f1 S |
140 | #address-cells = <1>; |
141 | #size-cells = <1>; | |
dae320ec | 142 | ranges = <0x0 0x0 0x0 0xc0000000>; |
6e58b8f1 | 143 | ti,hwmods = "l3_main_1", "l3_main_2"; |
dae320ec LV |
144 | reg = <0x0 0x44000000 0x0 0x1000000>, |
145 | <0x0 0x45000000 0x0 0x1000>; | |
783d3186 | 146 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
7136d457 | 147 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 148 | |
d919501f TK |
149 | l4_cfg: l4@4a000000 { |
150 | compatible = "ti,dra7-l4-cfg", "simple-bus"; | |
151 | #address-cells = <1>; | |
152 | #size-cells = <1>; | |
153 | ranges = <0 0x4a000000 0x22c000>; | |
ee6c7507 | 154 | |
d919501f TK |
155 | scm: scm@2000 { |
156 | compatible = "ti,dra7-scm-core", "simple-bus"; | |
157 | reg = <0x2000 0x2000>; | |
ee6c7507 | 158 | #address-cells = <1>; |
d919501f TK |
159 | #size-cells = <1>; |
160 | ranges = <0 0x2000 0x2000>; | |
161 | ||
162 | scm_conf: scm_conf@0 { | |
cd455673 | 163 | compatible = "syscon", "simple-bus"; |
d919501f TK |
164 | reg = <0x0 0x1400>; |
165 | #address-cells = <1>; | |
166 | #size-cells = <1>; | |
9a5e3f27 | 167 | ranges = <0 0x0 0x1400>; |
d919501f | 168 | |
308cfdaf | 169 | pbias_regulator: pbias_regulator@e00 { |
737f146f | 170 | compatible = "ti,pbias-dra7", "ti,pbias-omap"; |
d919501f TK |
171 | reg = <0xe00 0x4>; |
172 | syscon = <&scm_conf>; | |
173 | pbias_mmc_reg: pbias_mmc_omap5 { | |
174 | regulator-name = "pbias_mmc_omap5"; | |
175 | regulator-min-microvolt = <1800000>; | |
176 | regulator-max-microvolt = <3000000>; | |
177 | }; | |
178 | }; | |
2d5a3c80 TV |
179 | |
180 | scm_conf_clocks: clocks { | |
181 | #address-cells = <1>; | |
182 | #size-cells = <0>; | |
183 | }; | |
d919501f TK |
184 | }; |
185 | ||
186 | dra7_pmx_core: pinmux@1400 { | |
187 | compatible = "ti,dra7-padconf", | |
188 | "pinctrl-single"; | |
1c5cb6fd | 189 | reg = <0x1400 0x0468>; |
d919501f TK |
190 | #address-cells = <1>; |
191 | #size-cells = <0>; | |
192 | #interrupt-cells = <1>; | |
193 | interrupt-controller; | |
194 | pinctrl-single,register-width = <32>; | |
195 | pinctrl-single,function-mask = <0x3fffffff>; | |
196 | }; | |
33cb3a13 RQ |
197 | |
198 | scm_conf1: scm_conf@1c04 { | |
199 | compatible = "syscon"; | |
200 | reg = <0x1c04 0x0020>; | |
201 | }; | |
43acf169 KVA |
202 | |
203 | scm_conf_pcie: scm_conf@1c24 { | |
204 | compatible = "syscon"; | |
205 | reg = <0x1c24 0x0024>; | |
206 | }; | |
3d2a58bc PU |
207 | |
208 | sdma_xbar: dma-router@b78 { | |
209 | compatible = "ti,dra7-dma-crossbar"; | |
210 | reg = <0xb78 0xfc>; | |
211 | #dma-cells = <1>; | |
212 | dma-requests = <205>; | |
213 | ti,dma-safe-map = <0>; | |
214 | dma-masters = <&sdma>; | |
215 | }; | |
248948fb PU |
216 | |
217 | edma_xbar: dma-router@c78 { | |
218 | compatible = "ti,dra7-dma-crossbar"; | |
219 | reg = <0xc78 0x7c>; | |
220 | #dma-cells = <2>; | |
221 | dma-requests = <204>; | |
222 | ti,dma-safe-map = <0>; | |
223 | dma-masters = <&edma>; | |
224 | }; | |
d919501f TK |
225 | }; |
226 | ||
227 | cm_core_aon: cm_core_aon@5000 { | |
228 | compatible = "ti,dra7-cm-core-aon"; | |
229 | reg = <0x5000 0x2000>; | |
230 | ||
231 | cm_core_aon_clocks: clocks { | |
232 | #address-cells = <1>; | |
233 | #size-cells = <0>; | |
234 | }; | |
235 | ||
236 | cm_core_aon_clockdomains: clockdomains { | |
237 | }; | |
ee6c7507 TK |
238 | }; |
239 | ||
d919501f TK |
240 | cm_core: cm_core@8000 { |
241 | compatible = "ti,dra7-cm-core"; | |
242 | reg = <0x8000 0x3000>; | |
243 | ||
244 | cm_core_clocks: clocks { | |
245 | #address-cells = <1>; | |
246 | #size-cells = <0>; | |
247 | }; | |
248 | ||
249 | cm_core_clockdomains: clockdomains { | |
250 | }; | |
ee6c7507 | 251 | }; |
d919501f | 252 | }; |
ee6c7507 | 253 | |
d919501f TK |
254 | l4_wkup: l4@4ae00000 { |
255 | compatible = "ti,dra7-l4-wkup", "simple-bus"; | |
256 | #address-cells = <1>; | |
257 | #size-cells = <1>; | |
258 | ranges = <0 0x4ae00000 0x3f000>; | |
259 | ||
260 | counter32k: counter@4000 { | |
261 | compatible = "ti,omap-counter32k"; | |
262 | reg = <0x4000 0x40>; | |
263 | ti,hwmods = "counter_32k"; | |
264 | }; | |
265 | ||
266 | prm: prm@6000 { | |
267 | compatible = "ti,dra7-prm"; | |
268 | reg = <0x6000 0x3000>; | |
269 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
270 | ||
271 | prm_clocks: clocks { | |
272 | #address-cells = <1>; | |
273 | #size-cells = <0>; | |
274 | }; | |
275 | ||
276 | prm_clockdomains: clockdomains { | |
277 | }; | |
ee6c7507 | 278 | }; |
62e4feed DG |
279 | |
280 | scm_wkup: scm_conf@c000 { | |
281 | compatible = "syscon"; | |
282 | reg = <0xc000 0x1000>; | |
283 | }; | |
ee6c7507 TK |
284 | }; |
285 | ||
18dcd79d KVA |
286 | axi@0 { |
287 | compatible = "simple-bus"; | |
288 | #size-cells = <1>; | |
289 | #address-cells = <1>; | |
290 | ranges = <0x51000000 0x51000000 0x3000 | |
291 | 0x0 0x20000000 0x10000000>; | |
73c8f0cb | 292 | pcie1: pcie@51000000 { |
18dcd79d KVA |
293 | compatible = "ti,dra7-pcie"; |
294 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; | |
295 | reg-names = "rc_dbics", "ti_conf", "config"; | |
296 | interrupts = <0 232 0x4>, <0 233 0x4>; | |
297 | #address-cells = <3>; | |
298 | #size-cells = <2>; | |
299 | device_type = "pci"; | |
300 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
301 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; | |
302 | #interrupt-cells = <1>; | |
303 | num-lanes = <1>; | |
304 | ti,hwmods = "pcie1"; | |
305 | phys = <&pcie1_phy>; | |
306 | phy-names = "pcie-phy0"; | |
307 | interrupt-map-mask = <0 0 0 7>; | |
308 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, | |
309 | <0 0 0 2 &pcie1_intc 2>, | |
310 | <0 0 0 3 &pcie1_intc 3>, | |
311 | <0 0 0 4 &pcie1_intc 4>; | |
312 | pcie1_intc: interrupt-controller { | |
313 | interrupt-controller; | |
314 | #address-cells = <0>; | |
315 | #interrupt-cells = <1>; | |
316 | }; | |
317 | }; | |
318 | }; | |
319 | ||
320 | axi@1 { | |
321 | compatible = "simple-bus"; | |
322 | #size-cells = <1>; | |
323 | #address-cells = <1>; | |
324 | ranges = <0x51800000 0x51800000 0x3000 | |
325 | 0x0 0x30000000 0x10000000>; | |
326 | status = "disabled"; | |
327 | pcie@51000000 { | |
328 | compatible = "ti,dra7-pcie"; | |
329 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; | |
330 | reg-names = "rc_dbics", "ti_conf", "config"; | |
331 | interrupts = <0 355 0x4>, <0 356 0x4>; | |
332 | #address-cells = <3>; | |
333 | #size-cells = <2>; | |
334 | device_type = "pci"; | |
335 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
336 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; | |
337 | #interrupt-cells = <1>; | |
338 | num-lanes = <1>; | |
339 | ti,hwmods = "pcie2"; | |
340 | phys = <&pcie2_phy>; | |
341 | phy-names = "pcie-phy0"; | |
342 | interrupt-map-mask = <0 0 0 7>; | |
343 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, | |
344 | <0 0 0 2 &pcie2_intc 2>, | |
345 | <0 0 0 3 &pcie2_intc 3>, | |
346 | <0 0 0 4 &pcie2_intc 4>; | |
347 | pcie2_intc: interrupt-controller { | |
348 | interrupt-controller; | |
349 | #address-cells = <0>; | |
350 | #interrupt-cells = <1>; | |
351 | }; | |
352 | }; | |
353 | }; | |
354 | ||
a5fa09b6 DG |
355 | ocmcram1: ocmcram@40300000 { |
356 | compatible = "mmio-sram"; | |
357 | reg = <0x40300000 0x80000>; | |
358 | ranges = <0x0 0x40300000 0x80000>; | |
359 | #address-cells = <1>; | |
360 | #size-cells = <1>; | |
fae3a9f0 DG |
361 | /* |
362 | * This is a placeholder for an optional reserved | |
363 | * region for use by secure software. The size | |
364 | * of this region is not known until runtime so it | |
365 | * is set as zero to either be updated to reserve | |
366 | * space or left unchanged to leave all SRAM for use. | |
367 | * On HS parts that that require the reserved region | |
368 | * either the bootloader can update the size to | |
369 | * the required amount or the node can be overridden | |
370 | * from the board dts file for the secure platform. | |
371 | */ | |
372 | sram-hs@0 { | |
373 | compatible = "ti,secure-ram"; | |
374 | reg = <0x0 0x0>; | |
375 | }; | |
a5fa09b6 DG |
376 | }; |
377 | ||
378 | /* | |
379 | * NOTE: ocmcram2 and ocmcram3 are not available on all | |
380 | * DRA7xx and AM57xx variants. Confirm availability in | |
381 | * the data manual for the exact part number in use | |
382 | * before enabling these nodes in the board dts file. | |
383 | */ | |
384 | ocmcram2: ocmcram@40400000 { | |
385 | status = "disabled"; | |
386 | compatible = "mmio-sram"; | |
387 | reg = <0x40400000 0x100000>; | |
388 | ranges = <0x0 0x40400000 0x100000>; | |
389 | #address-cells = <1>; | |
390 | #size-cells = <1>; | |
391 | }; | |
392 | ||
393 | ocmcram3: ocmcram@40500000 { | |
394 | status = "disabled"; | |
395 | compatible = "mmio-sram"; | |
396 | reg = <0x40500000 0x100000>; | |
397 | ranges = <0x0 0x40500000 0x100000>; | |
398 | #address-cells = <1>; | |
399 | #size-cells = <1>; | |
400 | }; | |
401 | ||
f7397edf K |
402 | bandgap: bandgap@4a0021e0 { |
403 | reg = <0x4a0021e0 0xc | |
404 | 0x4a00232c 0xc | |
405 | 0x4a002380 0x2c | |
406 | 0x4a0023C0 0x3c | |
407 | 0x4a002564 0x8 | |
408 | 0x4a002574 0x50>; | |
409 | compatible = "ti,dra752-bandgap"; | |
410 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
411 | #thermal-sensor-cells = <1>; | |
412 | }; | |
413 | ||
99639ace SA |
414 | dsp1_system: dsp_system@40d00000 { |
415 | compatible = "syscon"; | |
416 | reg = <0x40d00000 0x100>; | |
417 | }; | |
418 | ||
6e58b8f1 S |
419 | sdma: dma-controller@4a056000 { |
420 | compatible = "ti,omap4430-sdma"; | |
421 | reg = <0x4a056000 0x1000>; | |
a46631c4 S |
422 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
423 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
424 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
425 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
6e58b8f1 | 426 | #dma-cells = <1>; |
08d9b327 PU |
427 | dma-channels = <32>; |
428 | dma-requests = <127>; | |
6e58b8f1 S |
429 | }; |
430 | ||
248948fb PU |
431 | edma: edma@43300000 { |
432 | compatible = "ti,edma3-tpcc"; | |
433 | ti,hwmods = "tpcc"; | |
434 | reg = <0x43300000 0x100000>; | |
435 | reg-names = "edma3_cc"; | |
436 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, | |
437 | <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, | |
438 | <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
a5206553 | 439 | interrupt-names = "edma3_ccint", "edma3_mperr", |
248948fb PU |
440 | "edma3_ccerrint"; |
441 | dma-requests = <64>; | |
442 | #dma-cells = <2>; | |
443 | ||
444 | ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; | |
445 | ||
446 | /* | |
447 | * memcpy is disabled, can be enabled with: | |
448 | * ti,edma-memcpy-channels = <20 21>; | |
449 | * for example. Note that these channels need to be | |
450 | * masked in the xbar as well. | |
451 | */ | |
452 | }; | |
453 | ||
454 | edma_tptc0: tptc@43400000 { | |
455 | compatible = "ti,edma3-tptc"; | |
456 | ti,hwmods = "tptc0"; | |
457 | reg = <0x43400000 0x100000>; | |
458 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; | |
459 | interrupt-names = "edma3_tcerrint"; | |
460 | }; | |
461 | ||
462 | edma_tptc1: tptc@43500000 { | |
463 | compatible = "ti,edma3-tptc"; | |
464 | ti,hwmods = "tptc1"; | |
465 | reg = <0x43500000 0x100000>; | |
466 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; | |
467 | interrupt-names = "edma3_tcerrint"; | |
468 | }; | |
469 | ||
6e58b8f1 S |
470 | gpio1: gpio@4ae10000 { |
471 | compatible = "ti,omap4-gpio"; | |
472 | reg = <0x4ae10000 0x200>; | |
a46631c4 | 473 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
474 | ti,hwmods = "gpio1"; |
475 | gpio-controller; | |
476 | #gpio-cells = <2>; | |
477 | interrupt-controller; | |
e49d519c | 478 | #interrupt-cells = <2>; |
6e58b8f1 S |
479 | }; |
480 | ||
481 | gpio2: gpio@48055000 { | |
482 | compatible = "ti,omap4-gpio"; | |
483 | reg = <0x48055000 0x200>; | |
a46631c4 | 484 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
485 | ti,hwmods = "gpio2"; |
486 | gpio-controller; | |
487 | #gpio-cells = <2>; | |
488 | interrupt-controller; | |
e49d519c | 489 | #interrupt-cells = <2>; |
6e58b8f1 S |
490 | }; |
491 | ||
492 | gpio3: gpio@48057000 { | |
493 | compatible = "ti,omap4-gpio"; | |
494 | reg = <0x48057000 0x200>; | |
a46631c4 | 495 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
496 | ti,hwmods = "gpio3"; |
497 | gpio-controller; | |
498 | #gpio-cells = <2>; | |
499 | interrupt-controller; | |
e49d519c | 500 | #interrupt-cells = <2>; |
6e58b8f1 S |
501 | }; |
502 | ||
503 | gpio4: gpio@48059000 { | |
504 | compatible = "ti,omap4-gpio"; | |
505 | reg = <0x48059000 0x200>; | |
a46631c4 | 506 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
507 | ti,hwmods = "gpio4"; |
508 | gpio-controller; | |
509 | #gpio-cells = <2>; | |
510 | interrupt-controller; | |
e49d519c | 511 | #interrupt-cells = <2>; |
6e58b8f1 S |
512 | }; |
513 | ||
514 | gpio5: gpio@4805b000 { | |
515 | compatible = "ti,omap4-gpio"; | |
516 | reg = <0x4805b000 0x200>; | |
a46631c4 | 517 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
518 | ti,hwmods = "gpio5"; |
519 | gpio-controller; | |
520 | #gpio-cells = <2>; | |
521 | interrupt-controller; | |
e49d519c | 522 | #interrupt-cells = <2>; |
6e58b8f1 S |
523 | }; |
524 | ||
525 | gpio6: gpio@4805d000 { | |
526 | compatible = "ti,omap4-gpio"; | |
527 | reg = <0x4805d000 0x200>; | |
a46631c4 | 528 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
529 | ti,hwmods = "gpio6"; |
530 | gpio-controller; | |
531 | #gpio-cells = <2>; | |
532 | interrupt-controller; | |
e49d519c | 533 | #interrupt-cells = <2>; |
6e58b8f1 S |
534 | }; |
535 | ||
536 | gpio7: gpio@48051000 { | |
537 | compatible = "ti,omap4-gpio"; | |
538 | reg = <0x48051000 0x200>; | |
a46631c4 | 539 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
540 | ti,hwmods = "gpio7"; |
541 | gpio-controller; | |
542 | #gpio-cells = <2>; | |
543 | interrupt-controller; | |
e49d519c | 544 | #interrupt-cells = <2>; |
6e58b8f1 S |
545 | }; |
546 | ||
547 | gpio8: gpio@48053000 { | |
548 | compatible = "ti,omap4-gpio"; | |
549 | reg = <0x48053000 0x200>; | |
a46631c4 | 550 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
551 | ti,hwmods = "gpio8"; |
552 | gpio-controller; | |
553 | #gpio-cells = <2>; | |
554 | interrupt-controller; | |
e49d519c | 555 | #interrupt-cells = <2>; |
6e58b8f1 S |
556 | }; |
557 | ||
558 | uart1: serial@4806a000 { | |
2a0e5ef6 | 559 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 560 | reg = <0x4806a000 0x100>; |
783d3186 | 561 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
562 | ti,hwmods = "uart1"; |
563 | clock-frequency = <48000000>; | |
564 | status = "disabled"; | |
3a0830de | 565 | dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; |
f0199a29 | 566 | dma-names = "tx", "rx"; |
6e58b8f1 S |
567 | }; |
568 | ||
569 | uart2: serial@4806c000 { | |
2a0e5ef6 | 570 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 571 | reg = <0x4806c000 0x100>; |
783d3186 | 572 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
573 | ti,hwmods = "uart2"; |
574 | clock-frequency = <48000000>; | |
575 | status = "disabled"; | |
3a0830de | 576 | dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; |
f0199a29 | 577 | dma-names = "tx", "rx"; |
6e58b8f1 S |
578 | }; |
579 | ||
580 | uart3: serial@48020000 { | |
2a0e5ef6 | 581 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 582 | reg = <0x48020000 0x100>; |
783d3186 | 583 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
584 | ti,hwmods = "uart3"; |
585 | clock-frequency = <48000000>; | |
586 | status = "disabled"; | |
3a0830de | 587 | dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; |
f0199a29 | 588 | dma-names = "tx", "rx"; |
6e58b8f1 S |
589 | }; |
590 | ||
591 | uart4: serial@4806e000 { | |
2a0e5ef6 | 592 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 593 | reg = <0x4806e000 0x100>; |
783d3186 | 594 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
595 | ti,hwmods = "uart4"; |
596 | clock-frequency = <48000000>; | |
597 | status = "disabled"; | |
3a0830de | 598 | dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; |
f0199a29 | 599 | dma-names = "tx", "rx"; |
6e58b8f1 S |
600 | }; |
601 | ||
602 | uart5: serial@48066000 { | |
2a0e5ef6 | 603 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 604 | reg = <0x48066000 0x100>; |
783d3186 | 605 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
606 | ti,hwmods = "uart5"; |
607 | clock-frequency = <48000000>; | |
608 | status = "disabled"; | |
3a0830de | 609 | dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; |
f0199a29 | 610 | dma-names = "tx", "rx"; |
6e58b8f1 S |
611 | }; |
612 | ||
613 | uart6: serial@48068000 { | |
2a0e5ef6 | 614 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 615 | reg = <0x48068000 0x100>; |
783d3186 | 616 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
617 | ti,hwmods = "uart6"; |
618 | clock-frequency = <48000000>; | |
619 | status = "disabled"; | |
3a0830de | 620 | dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; |
f0199a29 | 621 | dma-names = "tx", "rx"; |
6e58b8f1 S |
622 | }; |
623 | ||
624 | uart7: serial@48420000 { | |
2a0e5ef6 | 625 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 626 | reg = <0x48420000 0x100>; |
783d3186 | 627 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
628 | ti,hwmods = "uart7"; |
629 | clock-frequency = <48000000>; | |
630 | status = "disabled"; | |
631 | }; | |
632 | ||
633 | uart8: serial@48422000 { | |
2a0e5ef6 | 634 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 635 | reg = <0x48422000 0x100>; |
783d3186 | 636 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
637 | ti,hwmods = "uart8"; |
638 | clock-frequency = <48000000>; | |
639 | status = "disabled"; | |
640 | }; | |
641 | ||
642 | uart9: serial@48424000 { | |
2a0e5ef6 | 643 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 644 | reg = <0x48424000 0x100>; |
783d3186 | 645 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
646 | ti,hwmods = "uart9"; |
647 | clock-frequency = <48000000>; | |
648 | status = "disabled"; | |
649 | }; | |
650 | ||
651 | uart10: serial@4ae2b000 { | |
2a0e5ef6 | 652 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
6e58b8f1 | 653 | reg = <0x4ae2b000 0x100>; |
783d3186 | 654 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
655 | ti,hwmods = "uart10"; |
656 | clock-frequency = <48000000>; | |
657 | status = "disabled"; | |
658 | }; | |
659 | ||
38baefb3 SA |
660 | mailbox1: mailbox@4a0f4000 { |
661 | compatible = "ti,omap4-mailbox"; | |
662 | reg = <0x4a0f4000 0x200>; | |
b46a6ae6 SA |
663 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
664 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
665 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 666 | ti,hwmods = "mailbox1"; |
24df0453 | 667 | #mbox-cells = <1>; |
38baefb3 SA |
668 | ti,mbox-num-users = <3>; |
669 | ti,mbox-num-fifos = <8>; | |
670 | status = "disabled"; | |
671 | }; | |
672 | ||
673 | mailbox2: mailbox@4883a000 { | |
674 | compatible = "ti,omap4-mailbox"; | |
675 | reg = <0x4883a000 0x200>; | |
b46a6ae6 SA |
676 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
677 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, | |
678 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
679 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 680 | ti,hwmods = "mailbox2"; |
24df0453 | 681 | #mbox-cells = <1>; |
38baefb3 SA |
682 | ti,mbox-num-users = <4>; |
683 | ti,mbox-num-fifos = <12>; | |
684 | status = "disabled"; | |
685 | }; | |
686 | ||
687 | mailbox3: mailbox@4883c000 { | |
688 | compatible = "ti,omap4-mailbox"; | |
689 | reg = <0x4883c000 0x200>; | |
b46a6ae6 SA |
690 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
691 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
692 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, | |
693 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 694 | ti,hwmods = "mailbox3"; |
24df0453 | 695 | #mbox-cells = <1>; |
38baefb3 SA |
696 | ti,mbox-num-users = <4>; |
697 | ti,mbox-num-fifos = <12>; | |
698 | status = "disabled"; | |
699 | }; | |
700 | ||
701 | mailbox4: mailbox@4883e000 { | |
702 | compatible = "ti,omap4-mailbox"; | |
703 | reg = <0x4883e000 0x200>; | |
b46a6ae6 SA |
704 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
705 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
706 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
707 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 708 | ti,hwmods = "mailbox4"; |
24df0453 | 709 | #mbox-cells = <1>; |
38baefb3 SA |
710 | ti,mbox-num-users = <4>; |
711 | ti,mbox-num-fifos = <12>; | |
712 | status = "disabled"; | |
713 | }; | |
714 | ||
715 | mailbox5: mailbox@48840000 { | |
716 | compatible = "ti,omap4-mailbox"; | |
717 | reg = <0x48840000 0x200>; | |
b46a6ae6 SA |
718 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
719 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
720 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
721 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 722 | ti,hwmods = "mailbox5"; |
24df0453 | 723 | #mbox-cells = <1>; |
38baefb3 SA |
724 | ti,mbox-num-users = <4>; |
725 | ti,mbox-num-fifos = <12>; | |
726 | status = "disabled"; | |
727 | }; | |
728 | ||
729 | mailbox6: mailbox@48842000 { | |
730 | compatible = "ti,omap4-mailbox"; | |
731 | reg = <0x48842000 0x200>; | |
b46a6ae6 SA |
732 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
733 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
734 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
735 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 736 | ti,hwmods = "mailbox6"; |
24df0453 | 737 | #mbox-cells = <1>; |
38baefb3 SA |
738 | ti,mbox-num-users = <4>; |
739 | ti,mbox-num-fifos = <12>; | |
740 | status = "disabled"; | |
741 | }; | |
742 | ||
743 | mailbox7: mailbox@48844000 { | |
744 | compatible = "ti,omap4-mailbox"; | |
745 | reg = <0x48844000 0x200>; | |
b46a6ae6 SA |
746 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
747 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
748 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
749 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 750 | ti,hwmods = "mailbox7"; |
24df0453 | 751 | #mbox-cells = <1>; |
38baefb3 SA |
752 | ti,mbox-num-users = <4>; |
753 | ti,mbox-num-fifos = <12>; | |
754 | status = "disabled"; | |
755 | }; | |
756 | ||
757 | mailbox8: mailbox@48846000 { | |
758 | compatible = "ti,omap4-mailbox"; | |
759 | reg = <0x48846000 0x200>; | |
b46a6ae6 SA |
760 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
761 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, | |
762 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, | |
763 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 764 | ti,hwmods = "mailbox8"; |
24df0453 | 765 | #mbox-cells = <1>; |
38baefb3 SA |
766 | ti,mbox-num-users = <4>; |
767 | ti,mbox-num-fifos = <12>; | |
768 | status = "disabled"; | |
769 | }; | |
770 | ||
771 | mailbox9: mailbox@4885e000 { | |
772 | compatible = "ti,omap4-mailbox"; | |
773 | reg = <0x4885e000 0x200>; | |
b46a6ae6 SA |
774 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
775 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, | |
776 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, | |
777 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 778 | ti,hwmods = "mailbox9"; |
24df0453 | 779 | #mbox-cells = <1>; |
38baefb3 SA |
780 | ti,mbox-num-users = <4>; |
781 | ti,mbox-num-fifos = <12>; | |
782 | status = "disabled"; | |
783 | }; | |
784 | ||
785 | mailbox10: mailbox@48860000 { | |
786 | compatible = "ti,omap4-mailbox"; | |
787 | reg = <0x48860000 0x200>; | |
b46a6ae6 SA |
788 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
789 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, | |
790 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, | |
791 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 792 | ti,hwmods = "mailbox10"; |
24df0453 | 793 | #mbox-cells = <1>; |
38baefb3 SA |
794 | ti,mbox-num-users = <4>; |
795 | ti,mbox-num-fifos = <12>; | |
796 | status = "disabled"; | |
797 | }; | |
798 | ||
799 | mailbox11: mailbox@48862000 { | |
800 | compatible = "ti,omap4-mailbox"; | |
801 | reg = <0x48862000 0x200>; | |
b46a6ae6 SA |
802 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
803 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, | |
804 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, | |
805 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 806 | ti,hwmods = "mailbox11"; |
24df0453 | 807 | #mbox-cells = <1>; |
38baefb3 SA |
808 | ti,mbox-num-users = <4>; |
809 | ti,mbox-num-fifos = <12>; | |
810 | status = "disabled"; | |
811 | }; | |
812 | ||
813 | mailbox12: mailbox@48864000 { | |
814 | compatible = "ti,omap4-mailbox"; | |
815 | reg = <0x48864000 0x200>; | |
b46a6ae6 SA |
816 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
817 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, | |
818 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
819 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 820 | ti,hwmods = "mailbox12"; |
24df0453 | 821 | #mbox-cells = <1>; |
38baefb3 SA |
822 | ti,mbox-num-users = <4>; |
823 | ti,mbox-num-fifos = <12>; | |
824 | status = "disabled"; | |
825 | }; | |
826 | ||
827 | mailbox13: mailbox@48802000 { | |
828 | compatible = "ti,omap4-mailbox"; | |
829 | reg = <0x48802000 0x200>; | |
b46a6ae6 SA |
830 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
831 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, | |
832 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, | |
833 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 834 | ti,hwmods = "mailbox13"; |
24df0453 | 835 | #mbox-cells = <1>; |
38baefb3 SA |
836 | ti,mbox-num-users = <4>; |
837 | ti,mbox-num-fifos = <12>; | |
838 | status = "disabled"; | |
839 | }; | |
840 | ||
6e58b8f1 S |
841 | timer1: timer@4ae18000 { |
842 | compatible = "ti,omap5430-timer"; | |
843 | reg = <0x4ae18000 0x80>; | |
a46631c4 | 844 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
845 | ti,hwmods = "timer1"; |
846 | ti,timer-alwon; | |
847 | }; | |
848 | ||
849 | timer2: timer@48032000 { | |
850 | compatible = "ti,omap5430-timer"; | |
851 | reg = <0x48032000 0x80>; | |
a46631c4 | 852 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
853 | ti,hwmods = "timer2"; |
854 | }; | |
855 | ||
856 | timer3: timer@48034000 { | |
857 | compatible = "ti,omap5430-timer"; | |
858 | reg = <0x48034000 0x80>; | |
a46631c4 | 859 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
860 | ti,hwmods = "timer3"; |
861 | }; | |
862 | ||
863 | timer4: timer@48036000 { | |
864 | compatible = "ti,omap5430-timer"; | |
865 | reg = <0x48036000 0x80>; | |
a46631c4 | 866 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
867 | ti,hwmods = "timer4"; |
868 | }; | |
869 | ||
870 | timer5: timer@48820000 { | |
871 | compatible = "ti,omap5430-timer"; | |
872 | reg = <0x48820000 0x80>; | |
a46631c4 | 873 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 874 | ti,hwmods = "timer5"; |
6e58b8f1 S |
875 | }; |
876 | ||
877 | timer6: timer@48822000 { | |
878 | compatible = "ti,omap5430-timer"; | |
879 | reg = <0x48822000 0x80>; | |
a46631c4 | 880 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 881 | ti,hwmods = "timer6"; |
6e58b8f1 S |
882 | }; |
883 | ||
884 | timer7: timer@48824000 { | |
885 | compatible = "ti,omap5430-timer"; | |
886 | reg = <0x48824000 0x80>; | |
a46631c4 | 887 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 888 | ti,hwmods = "timer7"; |
6e58b8f1 S |
889 | }; |
890 | ||
891 | timer8: timer@48826000 { | |
892 | compatible = "ti,omap5430-timer"; | |
893 | reg = <0x48826000 0x80>; | |
a46631c4 | 894 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 895 | ti,hwmods = "timer8"; |
6e58b8f1 S |
896 | }; |
897 | ||
898 | timer9: timer@4803e000 { | |
899 | compatible = "ti,omap5430-timer"; | |
900 | reg = <0x4803e000 0x80>; | |
a46631c4 | 901 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
902 | ti,hwmods = "timer9"; |
903 | }; | |
904 | ||
905 | timer10: timer@48086000 { | |
906 | compatible = "ti,omap5430-timer"; | |
907 | reg = <0x48086000 0x80>; | |
a46631c4 | 908 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
909 | ti,hwmods = "timer10"; |
910 | }; | |
911 | ||
912 | timer11: timer@48088000 { | |
913 | compatible = "ti,omap5430-timer"; | |
914 | reg = <0x48088000 0x80>; | |
a46631c4 | 915 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 916 | ti,hwmods = "timer11"; |
6e58b8f1 S |
917 | }; |
918 | ||
d79852a7 SA |
919 | timer12: timer@4ae20000 { |
920 | compatible = "ti,omap5430-timer"; | |
921 | reg = <0x4ae20000 0x80>; | |
922 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
923 | ti,hwmods = "timer12"; | |
924 | ti,timer-alwon; | |
925 | ti,timer-secure; | |
926 | }; | |
927 | ||
6e58b8f1 S |
928 | timer13: timer@48828000 { |
929 | compatible = "ti,omap5430-timer"; | |
930 | reg = <0x48828000 0x80>; | |
a46631c4 | 931 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 932 | ti,hwmods = "timer13"; |
6e58b8f1 S |
933 | }; |
934 | ||
935 | timer14: timer@4882a000 { | |
936 | compatible = "ti,omap5430-timer"; | |
937 | reg = <0x4882a000 0x80>; | |
a46631c4 | 938 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 939 | ti,hwmods = "timer14"; |
6e58b8f1 S |
940 | }; |
941 | ||
942 | timer15: timer@4882c000 { | |
943 | compatible = "ti,omap5430-timer"; | |
944 | reg = <0x4882c000 0x80>; | |
a46631c4 | 945 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 946 | ti,hwmods = "timer15"; |
6e58b8f1 S |
947 | }; |
948 | ||
949 | timer16: timer@4882e000 { | |
950 | compatible = "ti,omap5430-timer"; | |
951 | reg = <0x4882e000 0x80>; | |
a46631c4 | 952 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 953 | ti,hwmods = "timer16"; |
6e58b8f1 S |
954 | }; |
955 | ||
956 | wdt2: wdt@4ae14000 { | |
be668835 | 957 | compatible = "ti,omap3-wdt"; |
6e58b8f1 | 958 | reg = <0x4ae14000 0x80>; |
a46631c4 | 959 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
960 | ti,hwmods = "wd_timer2"; |
961 | }; | |
962 | ||
dbd7c191 SA |
963 | hwspinlock: spinlock@4a0f6000 { |
964 | compatible = "ti,omap4-hwspinlock"; | |
965 | reg = <0x4a0f6000 0x1000>; | |
966 | ti,hwmods = "spinlock"; | |
967 | #hwlock-cells = <1>; | |
968 | }; | |
969 | ||
1a5fe3ca AT |
970 | dmm@4e000000 { |
971 | compatible = "ti,omap5-dmm"; | |
972 | reg = <0x4e000000 0x800>; | |
a46631c4 | 973 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
1a5fe3ca AT |
974 | ti,hwmods = "dmm"; |
975 | }; | |
976 | ||
6e58b8f1 S |
977 | i2c1: i2c@48070000 { |
978 | compatible = "ti,omap4-i2c"; | |
979 | reg = <0x48070000 0x100>; | |
a46631c4 | 980 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
981 | #address-cells = <1>; |
982 | #size-cells = <0>; | |
983 | ti,hwmods = "i2c1"; | |
984 | status = "disabled"; | |
985 | }; | |
986 | ||
987 | i2c2: i2c@48072000 { | |
988 | compatible = "ti,omap4-i2c"; | |
989 | reg = <0x48072000 0x100>; | |
a46631c4 | 990 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
991 | #address-cells = <1>; |
992 | #size-cells = <0>; | |
993 | ti,hwmods = "i2c2"; | |
994 | status = "disabled"; | |
995 | }; | |
996 | ||
997 | i2c3: i2c@48060000 { | |
998 | compatible = "ti,omap4-i2c"; | |
999 | reg = <0x48060000 0x100>; | |
a46631c4 | 1000 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1001 | #address-cells = <1>; |
1002 | #size-cells = <0>; | |
1003 | ti,hwmods = "i2c3"; | |
1004 | status = "disabled"; | |
1005 | }; | |
1006 | ||
1007 | i2c4: i2c@4807a000 { | |
1008 | compatible = "ti,omap4-i2c"; | |
1009 | reg = <0x4807a000 0x100>; | |
a46631c4 | 1010 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1011 | #address-cells = <1>; |
1012 | #size-cells = <0>; | |
1013 | ti,hwmods = "i2c4"; | |
1014 | status = "disabled"; | |
1015 | }; | |
1016 | ||
1017 | i2c5: i2c@4807c000 { | |
1018 | compatible = "ti,omap4-i2c"; | |
1019 | reg = <0x4807c000 0x100>; | |
a46631c4 | 1020 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1021 | #address-cells = <1>; |
1022 | #size-cells = <0>; | |
1023 | ti,hwmods = "i2c5"; | |
1024 | status = "disabled"; | |
1025 | }; | |
1026 | ||
1027 | mmc1: mmc@4809c000 { | |
1028 | compatible = "ti,omap4-hsmmc"; | |
1029 | reg = <0x4809c000 0x400>; | |
a46631c4 | 1030 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1031 | ti,hwmods = "mmc1"; |
1032 | ti,dual-volt; | |
1033 | ti,needs-special-reset; | |
3a0830de | 1034 | dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; |
6e58b8f1 S |
1035 | dma-names = "tx", "rx"; |
1036 | status = "disabled"; | |
cd042fe5 | 1037 | pbias-supply = <&pbias_mmc_reg>; |
6e58b8f1 S |
1038 | }; |
1039 | ||
1040 | mmc2: mmc@480b4000 { | |
1041 | compatible = "ti,omap4-hsmmc"; | |
1042 | reg = <0x480b4000 0x400>; | |
a46631c4 | 1043 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1044 | ti,hwmods = "mmc2"; |
1045 | ti,needs-special-reset; | |
3a0830de | 1046 | dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; |
6e58b8f1 S |
1047 | dma-names = "tx", "rx"; |
1048 | status = "disabled"; | |
1049 | }; | |
1050 | ||
1051 | mmc3: mmc@480ad000 { | |
1052 | compatible = "ti,omap4-hsmmc"; | |
1053 | reg = <0x480ad000 0x400>; | |
a46631c4 | 1054 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1055 | ti,hwmods = "mmc3"; |
1056 | ti,needs-special-reset; | |
3a0830de | 1057 | dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; |
6e58b8f1 S |
1058 | dma-names = "tx", "rx"; |
1059 | status = "disabled"; | |
1060 | }; | |
1061 | ||
1062 | mmc4: mmc@480d1000 { | |
1063 | compatible = "ti,omap4-hsmmc"; | |
1064 | reg = <0x480d1000 0x400>; | |
a46631c4 | 1065 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1066 | ti,hwmods = "mmc4"; |
1067 | ti,needs-special-reset; | |
3a0830de | 1068 | dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; |
6e58b8f1 S |
1069 | dma-names = "tx", "rx"; |
1070 | status = "disabled"; | |
1071 | }; | |
1072 | ||
2c7e07c5 SA |
1073 | mmu0_dsp1: mmu@40d01000 { |
1074 | compatible = "ti,dra7-dsp-iommu"; | |
1075 | reg = <0x40d01000 0x100>; | |
1076 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
1077 | ti,hwmods = "mmu0_dsp1"; | |
1078 | #iommu-cells = <0>; | |
1079 | ti,syscon-mmuconfig = <&dsp1_system 0x0>; | |
1080 | status = "disabled"; | |
1081 | }; | |
1082 | ||
1083 | mmu1_dsp1: mmu@40d02000 { | |
1084 | compatible = "ti,dra7-dsp-iommu"; | |
1085 | reg = <0x40d02000 0x100>; | |
1086 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
1087 | ti,hwmods = "mmu1_dsp1"; | |
1088 | #iommu-cells = <0>; | |
1089 | ti,syscon-mmuconfig = <&dsp1_system 0x1>; | |
1090 | status = "disabled"; | |
1091 | }; | |
1092 | ||
1093 | mmu_ipu1: mmu@58882000 { | |
1094 | compatible = "ti,dra7-iommu"; | |
1095 | reg = <0x58882000 0x100>; | |
1096 | interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; | |
1097 | ti,hwmods = "mmu_ipu1"; | |
1098 | #iommu-cells = <0>; | |
1099 | ti,iommu-bus-err-back; | |
1100 | status = "disabled"; | |
1101 | }; | |
1102 | ||
1103 | mmu_ipu2: mmu@55082000 { | |
1104 | compatible = "ti,dra7-iommu"; | |
1105 | reg = <0x55082000 0x100>; | |
1106 | interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; | |
1107 | ti,hwmods = "mmu_ipu2"; | |
1108 | #iommu-cells = <0>; | |
1109 | ti,iommu-bus-err-back; | |
1110 | status = "disabled"; | |
1111 | }; | |
1112 | ||
a1b8ee10 NM |
1113 | abb_mpu: regulator-abb-mpu { |
1114 | compatible = "ti,abb-v3"; | |
1115 | regulator-name = "abb_mpu"; | |
1116 | #address-cells = <0>; | |
1117 | #size-cells = <0>; | |
1118 | clocks = <&sys_clkin1>; | |
1119 | ti,settling-time = <50>; | |
1120 | ti,clock-cycles = <16>; | |
1121 | ||
1122 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, | |
18227346 | 1123 | <0x4ae06014 0x4>, <0x4a003b20 0xc>, |
a1b8ee10 NM |
1124 | <0x4ae0c158 0x4>; |
1125 | reg-names = "setup-address", "control-address", | |
1126 | "int-address", "efuse-address", | |
1127 | "ldo-address"; | |
1128 | ti,tranxdone-status-mask = <0x80>; | |
1129 | /* LDOVBBMPU_FBB_MUX_CTRL */ | |
1130 | ti,ldovbb-override-mask = <0x400>; | |
1131 | /* LDOVBBMPU_FBB_VSET_OUT */ | |
1132 | ti,ldovbb-vset-mask = <0x1F>; | |
1133 | ||
1134 | /* | |
1135 | * NOTE: only FBB mode used but actual vset will | |
1136 | * determine final biasing | |
1137 | */ | |
1138 | ti,abb_info = < | |
1139 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1140 | 1060000 0 0x0 0 0x02000000 0x01F00000 | |
1141 | 1160000 0 0x4 0 0x02000000 0x01F00000 | |
1142 | 1210000 0 0x8 0 0x02000000 0x01F00000 | |
1143 | >; | |
1144 | }; | |
1145 | ||
1146 | abb_ivahd: regulator-abb-ivahd { | |
1147 | compatible = "ti,abb-v3"; | |
1148 | regulator-name = "abb_ivahd"; | |
1149 | #address-cells = <0>; | |
1150 | #size-cells = <0>; | |
1151 | clocks = <&sys_clkin1>; | |
1152 | ti,settling-time = <50>; | |
1153 | ti,clock-cycles = <16>; | |
1154 | ||
1155 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, | |
18227346 | 1156 | <0x4ae06010 0x4>, <0x4a0025cc 0xc>, |
a1b8ee10 NM |
1157 | <0x4a002470 0x4>; |
1158 | reg-names = "setup-address", "control-address", | |
1159 | "int-address", "efuse-address", | |
1160 | "ldo-address"; | |
1161 | ti,tranxdone-status-mask = <0x40000000>; | |
1162 | /* LDOVBBIVA_FBB_MUX_CTRL */ | |
1163 | ti,ldovbb-override-mask = <0x400>; | |
1164 | /* LDOVBBIVA_FBB_VSET_OUT */ | |
1165 | ti,ldovbb-vset-mask = <0x1F>; | |
1166 | ||
1167 | /* | |
1168 | * NOTE: only FBB mode used but actual vset will | |
1169 | * determine final biasing | |
1170 | */ | |
1171 | ti,abb_info = < | |
1172 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1173 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
1174 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
1175 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
1176 | >; | |
1177 | }; | |
1178 | ||
1179 | abb_dspeve: regulator-abb-dspeve { | |
1180 | compatible = "ti,abb-v3"; | |
1181 | regulator-name = "abb_dspeve"; | |
1182 | #address-cells = <0>; | |
1183 | #size-cells = <0>; | |
1184 | clocks = <&sys_clkin1>; | |
1185 | ti,settling-time = <50>; | |
1186 | ti,clock-cycles = <16>; | |
1187 | ||
1188 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, | |
18227346 | 1189 | <0x4ae06010 0x4>, <0x4a0025e0 0xc>, |
a1b8ee10 NM |
1190 | <0x4a00246c 0x4>; |
1191 | reg-names = "setup-address", "control-address", | |
1192 | "int-address", "efuse-address", | |
1193 | "ldo-address"; | |
1194 | ti,tranxdone-status-mask = <0x20000000>; | |
1195 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ | |
1196 | ti,ldovbb-override-mask = <0x400>; | |
1197 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ | |
1198 | ti,ldovbb-vset-mask = <0x1F>; | |
1199 | ||
1200 | /* | |
1201 | * NOTE: only FBB mode used but actual vset will | |
1202 | * determine final biasing | |
1203 | */ | |
1204 | ti,abb_info = < | |
1205 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1206 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
1207 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
1208 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
1209 | >; | |
1210 | }; | |
1211 | ||
1212 | abb_gpu: regulator-abb-gpu { | |
1213 | compatible = "ti,abb-v3"; | |
1214 | regulator-name = "abb_gpu"; | |
1215 | #address-cells = <0>; | |
1216 | #size-cells = <0>; | |
1217 | clocks = <&sys_clkin1>; | |
1218 | ti,settling-time = <50>; | |
1219 | ti,clock-cycles = <16>; | |
1220 | ||
1221 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, | |
18227346 | 1222 | <0x4ae06010 0x4>, <0x4a003b08 0xc>, |
a1b8ee10 NM |
1223 | <0x4ae0c154 0x4>; |
1224 | reg-names = "setup-address", "control-address", | |
1225 | "int-address", "efuse-address", | |
1226 | "ldo-address"; | |
1227 | ti,tranxdone-status-mask = <0x10000000>; | |
1228 | /* LDOVBBGPU_FBB_MUX_CTRL */ | |
1229 | ti,ldovbb-override-mask = <0x400>; | |
1230 | /* LDOVBBGPU_FBB_VSET_OUT */ | |
1231 | ti,ldovbb-vset-mask = <0x1F>; | |
1232 | ||
1233 | /* | |
1234 | * NOTE: only FBB mode used but actual vset will | |
1235 | * determine final biasing | |
1236 | */ | |
1237 | ti,abb_info = < | |
1238 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1239 | 1090000 0 0x0 0 0x02000000 0x01F00000 | |
1240 | 1210000 0 0x4 0 0x02000000 0x01F00000 | |
1241 | 1280000 0 0x8 0 0x02000000 0x01F00000 | |
1242 | >; | |
1243 | }; | |
1244 | ||
6e58b8f1 S |
1245 | mcspi1: spi@48098000 { |
1246 | compatible = "ti,omap4-mcspi"; | |
1247 | reg = <0x48098000 0x200>; | |
a46631c4 | 1248 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1249 | #address-cells = <1>; |
1250 | #size-cells = <0>; | |
1251 | ti,hwmods = "mcspi1"; | |
1252 | ti,spi-num-cs = <4>; | |
3a0830de PU |
1253 | dmas = <&sdma_xbar 35>, |
1254 | <&sdma_xbar 36>, | |
1255 | <&sdma_xbar 37>, | |
1256 | <&sdma_xbar 38>, | |
1257 | <&sdma_xbar 39>, | |
1258 | <&sdma_xbar 40>, | |
1259 | <&sdma_xbar 41>, | |
1260 | <&sdma_xbar 42>; | |
6e58b8f1 S |
1261 | dma-names = "tx0", "rx0", "tx1", "rx1", |
1262 | "tx2", "rx2", "tx3", "rx3"; | |
1263 | status = "disabled"; | |
1264 | }; | |
1265 | ||
1266 | mcspi2: spi@4809a000 { | |
1267 | compatible = "ti,omap4-mcspi"; | |
1268 | reg = <0x4809a000 0x200>; | |
a46631c4 | 1269 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1270 | #address-cells = <1>; |
1271 | #size-cells = <0>; | |
1272 | ti,hwmods = "mcspi2"; | |
1273 | ti,spi-num-cs = <2>; | |
3a0830de PU |
1274 | dmas = <&sdma_xbar 43>, |
1275 | <&sdma_xbar 44>, | |
1276 | <&sdma_xbar 45>, | |
1277 | <&sdma_xbar 46>; | |
6e58b8f1 S |
1278 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
1279 | status = "disabled"; | |
1280 | }; | |
1281 | ||
1282 | mcspi3: spi@480b8000 { | |
1283 | compatible = "ti,omap4-mcspi"; | |
1284 | reg = <0x480b8000 0x200>; | |
a46631c4 | 1285 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1286 | #address-cells = <1>; |
1287 | #size-cells = <0>; | |
1288 | ti,hwmods = "mcspi3"; | |
1289 | ti,spi-num-cs = <2>; | |
3a0830de | 1290 | dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; |
6e58b8f1 S |
1291 | dma-names = "tx0", "rx0"; |
1292 | status = "disabled"; | |
1293 | }; | |
1294 | ||
1295 | mcspi4: spi@480ba000 { | |
1296 | compatible = "ti,omap4-mcspi"; | |
1297 | reg = <0x480ba000 0x200>; | |
a46631c4 | 1298 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1299 | #address-cells = <1>; |
1300 | #size-cells = <0>; | |
1301 | ti,hwmods = "mcspi4"; | |
1302 | ti,spi-num-cs = <1>; | |
3a0830de | 1303 | dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; |
6e58b8f1 S |
1304 | dma-names = "tx0", "rx0"; |
1305 | status = "disabled"; | |
1306 | }; | |
dc2dd5b8 SP |
1307 | |
1308 | qspi: qspi@4b300000 { | |
1309 | compatible = "ti,dra7xxx-qspi"; | |
1929d0b5 V |
1310 | reg = <0x4b300000 0x100>, |
1311 | <0x5c000000 0x4000000>; | |
1312 | reg-names = "qspi_base", "qspi_mmap"; | |
1313 | syscon-chipselects = <&scm_conf 0x558>; | |
dc2dd5b8 SP |
1314 | #address-cells = <1>; |
1315 | #size-cells = <0>; | |
1316 | ti,hwmods = "qspi"; | |
1317 | clocks = <&qspi_gfclk_div>; | |
1318 | clock-names = "fck"; | |
1319 | num-cs = <4>; | |
a46631c4 | 1320 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
dc2dd5b8 SP |
1321 | status = "disabled"; |
1322 | }; | |
7be80569 | 1323 | |
7be80569 B |
1324 | /* OCP2SCP3 */ |
1325 | ocp2scp@4a090000 { | |
1326 | compatible = "ti,omap-ocp2scp"; | |
1327 | #address-cells = <1>; | |
1328 | #size-cells = <1>; | |
1329 | ranges; | |
1330 | reg = <0x4a090000 0x20>; | |
1331 | ti,hwmods = "ocp2scp3"; | |
1332 | sata_phy: phy@4A096000 { | |
1333 | compatible = "ti,phy-pipe3-sata"; | |
1334 | reg = <0x4A096000 0x80>, /* phy_rx */ | |
1335 | <0x4A096400 0x64>, /* phy_tx */ | |
1336 | <0x4A096800 0x40>; /* pll_ctrl */ | |
1337 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
2338c76a | 1338 | syscon-phy-power = <&scm_conf 0x374>; |
773c5a0f RQ |
1339 | clocks = <&sys_clkin1>, <&sata_ref_clk>; |
1340 | clock-names = "sysclk", "refclk"; | |
257d5d9a | 1341 | syscon-pllreset = <&scm_conf 0x3fc>; |
7be80569 B |
1342 | #phy-cells = <0>; |
1343 | }; | |
692df0ef KVA |
1344 | |
1345 | pcie1_phy: pciephy@4a094000 { | |
1346 | compatible = "ti,phy-pipe3-pcie"; | |
1347 | reg = <0x4a094000 0x80>, /* phy_rx */ | |
1348 | <0x4a094400 0x64>; /* phy_tx */ | |
1349 | reg-names = "phy_rx", "phy_tx"; | |
6921e58b KVA |
1350 | syscon-phy-power = <&scm_conf_pcie 0x1c>; |
1351 | syscon-pcs = <&scm_conf_pcie 0x10>; | |
692df0ef KVA |
1352 | clocks = <&dpll_pcie_ref_ck>, |
1353 | <&dpll_pcie_ref_m2ldo_ck>, | |
1354 | <&optfclk_pciephy1_32khz>, | |
1355 | <&optfclk_pciephy1_clk>, | |
1356 | <&optfclk_pciephy1_div_clk>, | |
6921e58b KVA |
1357 | <&optfclk_pciephy_div>, |
1358 | <&sys_clkin1>; | |
692df0ef KVA |
1359 | clock-names = "dpll_ref", "dpll_ref_m2", |
1360 | "wkupclk", "refclk", | |
6921e58b | 1361 | "div-clk", "phy-div", "sysclk"; |
692df0ef | 1362 | #phy-cells = <0>; |
692df0ef KVA |
1363 | }; |
1364 | ||
1365 | pcie2_phy: pciephy@4a095000 { | |
1366 | compatible = "ti,phy-pipe3-pcie"; | |
1367 | reg = <0x4a095000 0x80>, /* phy_rx */ | |
1368 | <0x4a095400 0x64>; /* phy_tx */ | |
1369 | reg-names = "phy_rx", "phy_tx"; | |
6921e58b KVA |
1370 | syscon-phy-power = <&scm_conf_pcie 0x20>; |
1371 | syscon-pcs = <&scm_conf_pcie 0x10>; | |
692df0ef KVA |
1372 | clocks = <&dpll_pcie_ref_ck>, |
1373 | <&dpll_pcie_ref_m2ldo_ck>, | |
1374 | <&optfclk_pciephy2_32khz>, | |
1375 | <&optfclk_pciephy2_clk>, | |
1376 | <&optfclk_pciephy2_div_clk>, | |
6921e58b KVA |
1377 | <&optfclk_pciephy_div>, |
1378 | <&sys_clkin1>; | |
692df0ef KVA |
1379 | clock-names = "dpll_ref", "dpll_ref_m2", |
1380 | "wkupclk", "refclk", | |
6921e58b | 1381 | "div-clk", "phy-div", "sysclk"; |
692df0ef | 1382 | #phy-cells = <0>; |
692df0ef KVA |
1383 | status = "disabled"; |
1384 | }; | |
7be80569 B |
1385 | }; |
1386 | ||
1387 | sata: sata@4a141100 { | |
1388 | compatible = "snps,dwc-ahci"; | |
1389 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | |
a46631c4 | 1390 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
7be80569 B |
1391 | phys = <&sata_phy>; |
1392 | phy-names = "sata-phy"; | |
1393 | clocks = <&sata_ref_clk>; | |
1394 | ti,hwmods = "sata"; | |
1395 | }; | |
fbf3e552 | 1396 | |
00edd317 | 1397 | rtc: rtc@48838000 { |
bc078316 LV |
1398 | compatible = "ti,am3352-rtc"; |
1399 | reg = <0x48838000 0x100>; | |
1400 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, | |
1401 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; | |
1402 | ti,hwmods = "rtcss"; | |
1403 | clocks = <&sys_32k_ck>; | |
1404 | }; | |
1405 | ||
fbf3e552 RQ |
1406 | /* OCP2SCP1 */ |
1407 | ocp2scp@4a080000 { | |
1408 | compatible = "ti,omap-ocp2scp"; | |
1409 | #address-cells = <1>; | |
1410 | #size-cells = <1>; | |
1411 | ranges; | |
1412 | reg = <0x4a080000 0x20>; | |
1413 | ti,hwmods = "ocp2scp1"; | |
1414 | ||
1415 | usb2_phy1: phy@4a084000 { | |
1416 | compatible = "ti,omap-usb2"; | |
1417 | reg = <0x4a084000 0x400>; | |
2338c76a | 1418 | syscon-phy-power = <&scm_conf 0x300>; |
fbf3e552 RQ |
1419 | clocks = <&usb_phy1_always_on_clk32k>, |
1420 | <&usb_otg_ss1_refclk960m>; | |
1421 | clock-names = "wkupclk", | |
1422 | "refclk"; | |
1423 | #phy-cells = <0>; | |
1424 | }; | |
1425 | ||
1426 | usb2_phy2: phy@4a085000 { | |
4b4f52ed KVA |
1427 | compatible = "ti,dra7x-usb2-phy2", |
1428 | "ti,omap-usb2"; | |
fbf3e552 | 1429 | reg = <0x4a085000 0x400>; |
2338c76a | 1430 | syscon-phy-power = <&scm_conf 0xe74>; |
fbf3e552 RQ |
1431 | clocks = <&usb_phy2_always_on_clk32k>, |
1432 | <&usb_otg_ss2_refclk960m>; | |
1433 | clock-names = "wkupclk", | |
1434 | "refclk"; | |
1435 | #phy-cells = <0>; | |
1436 | }; | |
1437 | ||
1438 | usb3_phy1: phy@4a084400 { | |
1439 | compatible = "ti,omap-usb3"; | |
1440 | reg = <0x4a084400 0x80>, | |
1441 | <0x4a084800 0x64>, | |
1442 | <0x4a084c00 0x40>; | |
1443 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
2338c76a | 1444 | syscon-phy-power = <&scm_conf 0x370>; |
fbf3e552 RQ |
1445 | clocks = <&usb_phy3_always_on_clk32k>, |
1446 | <&sys_clkin1>, | |
1447 | <&usb_otg_ss1_refclk960m>; | |
1448 | clock-names = "wkupclk", | |
1449 | "sysclk", | |
1450 | "refclk"; | |
1451 | #phy-cells = <0>; | |
1452 | }; | |
1453 | }; | |
1454 | ||
4f6dec70 | 1455 | omap_dwc3_1: omap_dwc3_1@48880000 { |
fbf3e552 RQ |
1456 | compatible = "ti,dwc3"; |
1457 | ti,hwmods = "usb_otg_ss1"; | |
1458 | reg = <0x48880000 0x10000>; | |
a46631c4 | 1459 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1460 | #address-cells = <1>; |
1461 | #size-cells = <1>; | |
1462 | utmi-mode = <2>; | |
1463 | ranges; | |
1464 | usb1: usb@48890000 { | |
1465 | compatible = "snps,dwc3"; | |
1466 | reg = <0x48890000 0x17000>; | |
964927f3 RQ |
1467 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, |
1468 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, | |
1469 | <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
1470 | interrupt-names = "peripheral", | |
1471 | "host", | |
1472 | "otg"; | |
fbf3e552 RQ |
1473 | phys = <&usb2_phy1>, <&usb3_phy1>; |
1474 | phy-names = "usb2-phy", "usb3-phy"; | |
fbf3e552 RQ |
1475 | maximum-speed = "super-speed"; |
1476 | dr_mode = "otg"; | |
8c606735 FB |
1477 | snps,dis_u3_susphy_quirk; |
1478 | snps,dis_u2_susphy_quirk; | |
fbf3e552 RQ |
1479 | }; |
1480 | }; | |
1481 | ||
4f6dec70 | 1482 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
fbf3e552 RQ |
1483 | compatible = "ti,dwc3"; |
1484 | ti,hwmods = "usb_otg_ss2"; | |
1485 | reg = <0x488c0000 0x10000>; | |
a46631c4 | 1486 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1487 | #address-cells = <1>; |
1488 | #size-cells = <1>; | |
1489 | utmi-mode = <2>; | |
1490 | ranges; | |
1491 | usb2: usb@488d0000 { | |
1492 | compatible = "snps,dwc3"; | |
1493 | reg = <0x488d0000 0x17000>; | |
964927f3 RQ |
1494 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
1495 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
1496 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
1497 | interrupt-names = "peripheral", | |
1498 | "host", | |
1499 | "otg"; | |
fbf3e552 RQ |
1500 | phys = <&usb2_phy2>; |
1501 | phy-names = "usb2-phy"; | |
fbf3e552 RQ |
1502 | maximum-speed = "high-speed"; |
1503 | dr_mode = "otg"; | |
8c606735 FB |
1504 | snps,dis_u3_susphy_quirk; |
1505 | snps,dis_u2_susphy_quirk; | |
fbf3e552 RQ |
1506 | }; |
1507 | }; | |
1508 | ||
1509 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ | |
4f6dec70 | 1510 | omap_dwc3_3: omap_dwc3_3@48900000 { |
fbf3e552 RQ |
1511 | compatible = "ti,dwc3"; |
1512 | ti,hwmods = "usb_otg_ss3"; | |
1513 | reg = <0x48900000 0x10000>; | |
a46631c4 | 1514 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1515 | #address-cells = <1>; |
1516 | #size-cells = <1>; | |
1517 | utmi-mode = <2>; | |
1518 | ranges; | |
1519 | status = "disabled"; | |
1520 | usb3: usb@48910000 { | |
1521 | compatible = "snps,dwc3"; | |
1522 | reg = <0x48910000 0x17000>; | |
964927f3 RQ |
1523 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
1524 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, | |
1525 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; | |
1526 | interrupt-names = "peripheral", | |
1527 | "host", | |
1528 | "otg"; | |
fbf3e552 RQ |
1529 | maximum-speed = "high-speed"; |
1530 | dr_mode = "otg"; | |
8c606735 FB |
1531 | snps,dis_u3_susphy_quirk; |
1532 | snps,dis_u2_susphy_quirk; | |
fbf3e552 RQ |
1533 | }; |
1534 | }; | |
1535 | ||
ff66a3c8 MS |
1536 | elm: elm@48078000 { |
1537 | compatible = "ti,am3352-elm"; | |
1538 | reg = <0x48078000 0xfc0>; /* device IO registers */ | |
a46631c4 | 1539 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
ff66a3c8 MS |
1540 | ti,hwmods = "elm"; |
1541 | status = "disabled"; | |
1542 | }; | |
1543 | ||
1544 | gpmc: gpmc@50000000 { | |
1545 | compatible = "ti,am3352-gpmc"; | |
1546 | ti,hwmods = "gpmc"; | |
1547 | reg = <0x50000000 0x37c>; /* device IO registers */ | |
a46631c4 | 1548 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
ff66a3c8 MS |
1549 | gpmc,num-cs = <8>; |
1550 | gpmc,num-waitpins = <2>; | |
1551 | #address-cells = <2>; | |
1552 | #size-cells = <1>; | |
488f270d RQ |
1553 | interrupt-controller; |
1554 | #interrupt-cells = <2>; | |
845b1a26 RQ |
1555 | gpio-controller; |
1556 | #gpio-cells = <2>; | |
ff66a3c8 MS |
1557 | status = "disabled"; |
1558 | }; | |
2ca0945f PU |
1559 | |
1560 | atl: atl@4843c000 { | |
1561 | compatible = "ti,dra7-atl"; | |
1562 | reg = <0x4843c000 0x3ff>; | |
1563 | ti,hwmods = "atl"; | |
1564 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, | |
1565 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; | |
1566 | clocks = <&atl_gfclk_mux>; | |
1567 | clock-names = "fck"; | |
1568 | status = "disabled"; | |
1569 | }; | |
412a9bbd | 1570 | |
296ea972 PU |
1571 | mcasp1: mcasp@48460000 { |
1572 | compatible = "ti,dra7-mcasp-audio"; | |
1573 | ti,hwmods = "mcasp1"; | |
1574 | reg = <0x48460000 0x2000>, | |
1575 | <0x45800000 0x1000>; | |
1576 | reg-names = "mpu","dat"; | |
1577 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
1578 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
1579 | interrupt-names = "tx", "rx"; | |
1580 | dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; | |
1581 | dma-names = "tx", "rx"; | |
1582 | clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, | |
1583 | <&mcasp1_ahclkr_mux>; | |
1584 | clock-names = "fck", "ahclkx", "ahclkr"; | |
1585 | status = "disabled"; | |
1586 | }; | |
1587 | ||
1588 | mcasp2: mcasp@48464000 { | |
1589 | compatible = "ti,dra7-mcasp-audio"; | |
1590 | ti,hwmods = "mcasp2"; | |
1591 | reg = <0x48464000 0x2000>, | |
1592 | <0x45c00000 0x1000>; | |
1593 | reg-names = "mpu","dat"; | |
1594 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
1595 | <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
1596 | interrupt-names = "tx", "rx"; | |
1597 | dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; | |
1598 | dma-names = "tx", "rx"; | |
1599 | clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, | |
1600 | <&mcasp2_ahclkr_mux>; | |
1601 | clock-names = "fck", "ahclkx", "ahclkr"; | |
1602 | status = "disabled"; | |
1603 | }; | |
1604 | ||
026d4d6d PU |
1605 | mcasp3: mcasp@48468000 { |
1606 | compatible = "ti,dra7-mcasp-audio"; | |
1607 | ti,hwmods = "mcasp3"; | |
0c92de2c MLC |
1608 | reg = <0x48468000 0x2000>, |
1609 | <0x46000000 0x1000>; | |
1610 | reg-names = "mpu","dat"; | |
026d4d6d PU |
1611 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
1612 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
1613 | interrupt-names = "tx", "rx"; | |
0c92de2c | 1614 | dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; |
026d4d6d | 1615 | dma-names = "tx", "rx"; |
bf05c2c2 | 1616 | clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; |
296ea972 PU |
1617 | clock-names = "fck", "ahclkx"; |
1618 | status = "disabled"; | |
1619 | }; | |
1620 | ||
1621 | mcasp4: mcasp@4846c000 { | |
1622 | compatible = "ti,dra7-mcasp-audio"; | |
1623 | ti,hwmods = "mcasp4"; | |
1624 | reg = <0x4846c000 0x2000>, | |
1625 | <0x48436000 0x1000>; | |
1626 | reg-names = "mpu","dat"; | |
1627 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
1628 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
1629 | interrupt-names = "tx", "rx"; | |
1630 | dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; | |
1631 | dma-names = "tx", "rx"; | |
1632 | clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; | |
1633 | clock-names = "fck", "ahclkx"; | |
1634 | status = "disabled"; | |
1635 | }; | |
1636 | ||
1637 | mcasp5: mcasp@48470000 { | |
1638 | compatible = "ti,dra7-mcasp-audio"; | |
1639 | ti,hwmods = "mcasp5"; | |
1640 | reg = <0x48470000 0x2000>, | |
1641 | <0x4843a000 0x1000>; | |
1642 | reg-names = "mpu","dat"; | |
1643 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, | |
1644 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
1645 | interrupt-names = "tx", "rx"; | |
1646 | dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; | |
1647 | dma-names = "tx", "rx"; | |
1648 | clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; | |
1649 | clock-names = "fck", "ahclkx"; | |
1650 | status = "disabled"; | |
1651 | }; | |
1652 | ||
1653 | mcasp6: mcasp@48474000 { | |
1654 | compatible = "ti,dra7-mcasp-audio"; | |
1655 | ti,hwmods = "mcasp6"; | |
1656 | reg = <0x48474000 0x2000>, | |
1657 | <0x4844c000 0x1000>; | |
1658 | reg-names = "mpu","dat"; | |
1659 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
1660 | <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
1661 | interrupt-names = "tx", "rx"; | |
1662 | dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; | |
1663 | dma-names = "tx", "rx"; | |
1664 | clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; | |
1665 | clock-names = "fck", "ahclkx"; | |
1666 | status = "disabled"; | |
1667 | }; | |
1668 | ||
1669 | mcasp7: mcasp@48478000 { | |
1670 | compatible = "ti,dra7-mcasp-audio"; | |
1671 | ti,hwmods = "mcasp7"; | |
1672 | reg = <0x48478000 0x2000>, | |
1673 | <0x48450000 0x1000>; | |
1674 | reg-names = "mpu","dat"; | |
1675 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, | |
1676 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
1677 | interrupt-names = "tx", "rx"; | |
1678 | dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; | |
1679 | dma-names = "tx", "rx"; | |
1680 | clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; | |
1681 | clock-names = "fck", "ahclkx"; | |
1682 | status = "disabled"; | |
1683 | }; | |
1684 | ||
1685 | mcasp8: mcasp@4847c000 { | |
1686 | compatible = "ti,dra7-mcasp-audio"; | |
1687 | ti,hwmods = "mcasp8"; | |
1688 | reg = <0x4847c000 0x2000>, | |
1689 | <0x48454000 0x1000>; | |
1690 | reg-names = "mpu","dat"; | |
1691 | interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, | |
1692 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; | |
1693 | interrupt-names = "tx", "rx"; | |
1694 | dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; | |
1695 | dma-names = "tx", "rx"; | |
1696 | clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; | |
bf05c2c2 | 1697 | clock-names = "fck", "ahclkx"; |
026d4d6d PU |
1698 | status = "disabled"; |
1699 | }; | |
1700 | ||
783d3186 | 1701 | crossbar_mpu: crossbar@4a002a48 { |
a46631c4 S |
1702 | compatible = "ti,irq-crossbar"; |
1703 | reg = <0x4a002a48 0x130>; | |
783d3186 | 1704 | interrupt-controller; |
7136d457 | 1705 | interrupt-parent = <&wakeupgen>; |
783d3186 | 1706 | #interrupt-cells = <3>; |
a46631c4 S |
1707 | ti,max-irqs = <160>; |
1708 | ti,max-crossbar-sources = <MAX_SOURCES>; | |
1709 | ti,reg-size = <2>; | |
1710 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; | |
1711 | ti,irqs-skip = <10 133 139 140>; | |
1712 | ti,irqs-safe-map = <0>; | |
1713 | }; | |
ef9c5b69 | 1714 | |
c263a5b8 | 1715 | mac: ethernet@48484000 { |
e2095318 | 1716 | compatible = "ti,dra7-cpsw","ti,cpsw"; |
ef9c5b69 M |
1717 | ti,hwmods = "gmac"; |
1718 | clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; | |
1719 | clock-names = "fck", "cpts"; | |
1720 | cpdma_channels = <8>; | |
1721 | ale_entries = <1024>; | |
1722 | bd_ram_size = <0x2000>; | |
1723 | no_bd_ram = <0>; | |
1724 | rx_descs = <64>; | |
1725 | mac_control = <0x20>; | |
1726 | slaves = <2>; | |
1727 | active_slave = <0>; | |
1728 | cpts_clock_mult = <0x80000000>; | |
1729 | cpts_clock_shift = <29>; | |
1730 | reg = <0x48484000 0x1000 | |
1731 | 0x48485200 0x2E00>; | |
1732 | #address-cells = <1>; | |
1733 | #size-cells = <1>; | |
0f514e69 M |
1734 | |
1735 | /* | |
1736 | * Do not allow gating of cpsw clock as workaround | |
1737 | * for errata i877. Keeping internal clock disabled | |
1738 | * causes the device switching characteristics | |
1739 | * to degrade over time and eventually fail to meet | |
1740 | * the data manual delay time/skew specs. | |
1741 | */ | |
1742 | ti,no-idle; | |
1743 | ||
ef9c5b69 M |
1744 | /* |
1745 | * rx_thresh_pend | |
1746 | * rx_pend | |
1747 | * tx_pend | |
1748 | * misc_pend | |
1749 | */ | |
1750 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
1751 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
1752 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
1753 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; | |
1754 | ranges; | |
a084e13e | 1755 | syscon = <&scm_conf>; |
ef9c5b69 M |
1756 | status = "disabled"; |
1757 | ||
1758 | davinci_mdio: mdio@48485000 { | |
1759 | compatible = "ti,davinci_mdio"; | |
1760 | #address-cells = <1>; | |
1761 | #size-cells = <0>; | |
1762 | ti,hwmods = "davinci_mdio"; | |
1763 | bus_freq = <1000000>; | |
1764 | reg = <0x48485000 0x100>; | |
1765 | }; | |
1766 | ||
1767 | cpsw_emac0: slave@48480200 { | |
1768 | /* Filled in by U-Boot */ | |
1769 | mac-address = [ 00 00 00 00 00 00 ]; | |
1770 | }; | |
1771 | ||
1772 | cpsw_emac1: slave@48480300 { | |
1773 | /* Filled in by U-Boot */ | |
1774 | mac-address = [ 00 00 00 00 00 00 ]; | |
1775 | }; | |
1776 | ||
1777 | phy_sel: cpsw-phy-sel@4a002554 { | |
1778 | compatible = "ti,dra7xx-cpsw-phy-sel"; | |
1779 | reg= <0x4a002554 0x4>; | |
1780 | reg-names = "gmii-sel"; | |
1781 | }; | |
1782 | }; | |
1783 | ||
9ec49b9f RQ |
1784 | dcan1: can@481cc000 { |
1785 | compatible = "ti,dra7-d_can"; | |
1786 | ti,hwmods = "dcan1"; | |
1787 | reg = <0x4ae3c000 0x2000>; | |
d919501f | 1788 | syscon-raminit = <&scm_conf 0x558 0>; |
9ec49b9f RQ |
1789 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
1790 | clocks = <&dcan1_sys_clk_mux>; | |
1791 | status = "disabled"; | |
1792 | }; | |
1793 | ||
1794 | dcan2: can@481d0000 { | |
1795 | compatible = "ti,dra7-d_can"; | |
1796 | ti,hwmods = "dcan2"; | |
1797 | reg = <0x48480000 0x2000>; | |
d919501f | 1798 | syscon-raminit = <&scm_conf 0x558 1>; |
9ec49b9f RQ |
1799 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
1800 | clocks = <&sys_clkin1>; | |
1801 | status = "disabled"; | |
1802 | }; | |
95c1cd13 TV |
1803 | |
1804 | dss: dss@58000000 { | |
1805 | compatible = "ti,dra7-dss"; | |
1806 | /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ | |
1807 | /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ | |
1808 | status = "disabled"; | |
1809 | ti,hwmods = "dss_core"; | |
1810 | /* CTRL_CORE_DSS_PLL_CONTROL */ | |
1811 | syscon-pll-ctrl = <&scm_conf 0x538>; | |
1812 | #address-cells = <1>; | |
1813 | #size-cells = <1>; | |
1814 | ranges; | |
1815 | ||
1816 | dispc@58001000 { | |
1817 | compatible = "ti,dra7-dispc"; | |
1818 | reg = <0x58001000 0x1000>; | |
1819 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
1820 | ti,hwmods = "dss_dispc"; | |
1821 | clocks = <&dss_dss_clk>; | |
1822 | clock-names = "fck"; | |
1823 | /* CTRL_CORE_SMA_SW_1 */ | |
1824 | syscon-pol = <&scm_conf 0x534>; | |
1825 | }; | |
1826 | ||
1827 | hdmi: encoder@58060000 { | |
1828 | compatible = "ti,dra7-hdmi"; | |
1829 | reg = <0x58040000 0x200>, | |
1830 | <0x58040200 0x80>, | |
1831 | <0x58040300 0x80>, | |
1832 | <0x58060000 0x19000>; | |
1833 | reg-names = "wp", "pll", "phy", "core"; | |
1834 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
1835 | status = "disabled"; | |
1836 | ti,hwmods = "dss_hdmi"; | |
1837 | clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; | |
1838 | clock-names = "fck", "sys_clk"; | |
1839 | }; | |
1840 | }; | |
34370142 V |
1841 | |
1842 | epwmss0: epwmss@4843e000 { | |
1843 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
1844 | reg = <0x4843e000 0x30>; | |
1845 | ti,hwmods = "epwmss0"; | |
1846 | #address-cells = <1>; | |
1847 | #size-cells = <1>; | |
1848 | status = "disabled"; | |
1849 | ranges; | |
1850 | ||
1851 | ehrpwm0: pwm@4843e200 { | |
1852 | compatible = "ti,dra746-ehrpwm", | |
1853 | "ti,am3352-ehrpwm"; | |
1854 | #pwm-cells = <3>; | |
1855 | reg = <0x4843e200 0x80>; | |
1856 | clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; | |
1857 | clock-names = "tbclk", "fck"; | |
1858 | status = "disabled"; | |
1859 | }; | |
1860 | ||
1861 | ecap0: ecap@4843e100 { | |
1862 | compatible = "ti,dra746-ecap", | |
1863 | "ti,am3352-ecap"; | |
1864 | #pwm-cells = <3>; | |
1865 | reg = <0x4843e100 0x80>; | |
1866 | clocks = <&l4_root_clk_div>; | |
1867 | clock-names = "fck"; | |
1868 | status = "disabled"; | |
1869 | }; | |
1870 | }; | |
1871 | ||
1872 | epwmss1: epwmss@48440000 { | |
1873 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
1874 | reg = <0x48440000 0x30>; | |
1875 | ti,hwmods = "epwmss1"; | |
1876 | #address-cells = <1>; | |
1877 | #size-cells = <1>; | |
1878 | status = "disabled"; | |
1879 | ranges; | |
1880 | ||
1881 | ehrpwm1: pwm@48440200 { | |
1882 | compatible = "ti,dra746-ehrpwm", | |
1883 | "ti,am3352-ehrpwm"; | |
1884 | #pwm-cells = <3>; | |
1885 | reg = <0x48440200 0x80>; | |
1886 | clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; | |
1887 | clock-names = "tbclk", "fck"; | |
1888 | status = "disabled"; | |
1889 | }; | |
1890 | ||
1891 | ecap1: ecap@48440100 { | |
1892 | compatible = "ti,dra746-ecap", | |
1893 | "ti,am3352-ecap"; | |
1894 | #pwm-cells = <3>; | |
1895 | reg = <0x48440100 0x80>; | |
1896 | clocks = <&l4_root_clk_div>; | |
1897 | clock-names = "fck"; | |
1898 | status = "disabled"; | |
1899 | }; | |
1900 | }; | |
1901 | ||
1902 | epwmss2: epwmss@48442000 { | |
1903 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
1904 | reg = <0x48442000 0x30>; | |
1905 | ti,hwmods = "epwmss2"; | |
1906 | #address-cells = <1>; | |
1907 | #size-cells = <1>; | |
1908 | status = "disabled"; | |
1909 | ranges; | |
1910 | ||
1911 | ehrpwm2: pwm@48442200 { | |
1912 | compatible = "ti,dra746-ehrpwm", | |
1913 | "ti,am3352-ehrpwm"; | |
1914 | #pwm-cells = <3>; | |
1915 | reg = <0x48442200 0x80>; | |
1916 | clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; | |
1917 | clock-names = "tbclk", "fck"; | |
1918 | status = "disabled"; | |
1919 | }; | |
1920 | ||
1921 | ecap2: ecap@48442100 { | |
1922 | compatible = "ti,dra746-ecap", | |
1923 | "ti,am3352-ecap"; | |
1924 | #pwm-cells = <3>; | |
1925 | reg = <0x48442100 0x80>; | |
1926 | clocks = <&l4_root_clk_div>; | |
1927 | clock-names = "fck"; | |
1928 | status = "disabled"; | |
1929 | }; | |
1930 | }; | |
6e58b8f1 | 1931 | }; |
f7397edf K |
1932 | |
1933 | thermal_zones: thermal-zones { | |
1934 | #include "omap4-cpu-thermal.dtsi" | |
1935 | #include "omap5-gpu-thermal.dtsi" | |
1936 | #include "omap5-core-thermal.dtsi" | |
667f2599 K |
1937 | #include "dra7-dspeve-thermal.dtsi" |
1938 | #include "dra7-iva-thermal.dtsi" | |
f7397edf K |
1939 | }; |
1940 | ||
1941 | }; | |
1942 | ||
1943 | &cpu_thermal { | |
1944 | polling-delay = <500>; /* milliseconds */ | |
6e58b8f1 | 1945 | }; |
ee6c7507 TK |
1946 | |
1947 | /include/ "dra7xx-clocks.dtsi" |