projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 6e58b8f1 S |
1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | * Based on "omap4.dtsi" | |
| 8 | */ | |
| 9 | ||
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 11 | #include <dt-bindings/pinctrl/dra.h> | |
| 12 | ||
| a46631c4 | 13 | #define MAX_SOURCES 400 |
| a46631c4 | 14 | |
| 6e58b8f1 | 15 | / { |
| dae320ec LV |
16 | #address-cells = <2>; |
| 17 | #size-cells = <2>; | |
| 6e58b8f1 S |
18 | |
| 19 | compatible = "ti,dra7xx"; | |
| 783d3186 | 20 | interrupt-parent = <&crossbar_mpu>; |
| 7f6c857b | 21 | chosen { }; |
| 6e58b8f1 S |
22 | |
| 23 | aliases { | |
| 20b80942 NM |
24 | i2c0 = &i2c1; |
| 25 | i2c1 = &i2c2; | |
| 26 | i2c2 = &i2c3; | |
| 27 | i2c3 = &i2c4; | |
| 28 | i2c4 = &i2c5; | |
| 6e58b8f1 S |
29 | serial0 = &uart1; |
| 30 | serial1 = &uart2; | |
| 31 | serial2 = &uart3; | |
| 32 | serial3 = &uart4; | |
| 33 | serial4 = &uart5; | |
| 34 | serial5 = &uart6; | |
| 065bd7fe NM |
35 | serial6 = &uart7; |
| 36 | serial7 = &uart8; | |
| 37 | serial8 = &uart9; | |
| 38 | serial9 = &uart10; | |
| ef9c5b69 M |
39 | ethernet0 = &cpsw_emac0; |
| 40 | ethernet1 = &cpsw_emac1; | |
| 9ec49b9f RQ |
41 | d_can0 = &dcan1; |
| 42 | d_can1 = &dcan2; | |
| 480b2b32 | 43 | spi0 = &qspi; |
| 6e58b8f1 S |
44 | }; |
| 45 | ||
| 6e58b8f1 S |
46 | timer { |
| 47 | compatible = "arm,armv7-timer"; | |
| 48 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
| 49 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
| 50 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
| 51 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
| 783d3186 | 52 | interrupt-parent = <&gic>; |
| 6e58b8f1 S |
53 | }; |
| 54 | ||
| 55 | gic: interrupt-controller@48211000 { | |
| 56 | compatible = "arm,cortex-a15-gic"; | |
| 57 | interrupt-controller; | |
| 58 | #interrupt-cells = <3>; | |
| dae320ec LV |
59 | reg = <0x0 0x48211000 0x0 0x1000>, |
| 60 | <0x0 0x48212000 0x0 0x1000>, | |
| 61 | <0x0 0x48214000 0x0 0x2000>, | |
| 62 | <0x0 0x48216000 0x0 0x2000>; | |
| 6e58b8f1 | 63 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 783d3186 | 64 | interrupt-parent = <&gic>; |
| 6e58b8f1 S |
65 | }; |
| 66 | ||
| 7136d457 MZ |
67 | wakeupgen: interrupt-controller@48281000 { |
| 68 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; | |
| 69 | interrupt-controller; | |
| 70 | #interrupt-cells = <3>; | |
| dae320ec | 71 | reg = <0x0 0x48281000 0x0 0x1000>; |
| 7136d457 | 72 | interrupt-parent = <&gic>; |
| 6e58b8f1 S |
73 | }; |
| 74 | ||
| b82ffb33 DG |
75 | cpus { |
| 76 | #address-cells = <1>; | |
| 77 | #size-cells = <0>; | |
| 78 | ||
| 79 | cpu0: cpu@0 { | |
| 80 | device_type = "cpu"; | |
| 81 | compatible = "arm,cortex-a15"; | |
| 82 | reg = <0>; | |
| 83 | ||
| a8dc7cb3 DG |
84 | operating-points = < |
| 85 | /* kHz uV */ | |
| 86 | 1000000 1060000 | |
| 87 | 1176000 1160000 | |
| 88 | >; | |
| b82ffb33 DG |
89 | |
| 90 | clocks = <&dpll_mpu_ck>; | |
| 91 | clock-names = "cpu"; | |
| 92 | ||
| 93 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
| 94 | ||
| 95 | /* cooling options */ | |
| 96 | cooling-min-level = <0>; | |
| 97 | cooling-max-level = <2>; | |
| 98 | #cooling-cells = <2>; /* min followed by max */ | |
| 99 | }; | |
| 100 | }; | |
| 101 | ||
| 6e58b8f1 | 102 | /* |
| 5c5be9db | 103 | * The soc node represents the soc top level view. It is used for IPs |
| 6e58b8f1 S |
104 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 105 | */ | |
| 106 | soc { | |
| 107 | compatible = "ti,omap-infra"; | |
| 108 | mpu { | |
| 109 | compatible = "ti,omap5-mpu"; | |
| 110 | ti,hwmods = "mpu"; | |
| 111 | }; | |
| 112 | }; | |
| 113 | ||
| 114 | /* | |
| 115 | * XXX: Use a flat representation of the SOC interconnect. | |
| 116 | * The real OMAP interconnect network is quite complex. | |
| b7ab524b | 117 | * Since it will not bring real advantage to represent that in DT for |
| 6e58b8f1 S |
118 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 119 | * hierarchy. | |
| 120 | */ | |
| 121 | ocp { | |
| fba387a6 | 122 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
| 6e58b8f1 S |
123 | #address-cells = <1>; |
| 124 | #size-cells = <1>; | |
| dae320ec | 125 | ranges = <0x0 0x0 0x0 0xc0000000>; |
| 6e58b8f1 | 126 | ti,hwmods = "l3_main_1", "l3_main_2"; |
| dae320ec LV |
127 | reg = <0x0 0x44000000 0x0 0x1000000>, |
| 128 | <0x0 0x45000000 0x0 0x1000>; | |
| 783d3186 | 129 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 7136d457 | 130 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 131 | |
| d919501f TK |
132 | l4_cfg: l4@4a000000 { |
| 133 | compatible = "ti,dra7-l4-cfg", "simple-bus"; | |
| 134 | #address-cells = <1>; | |
| 135 | #size-cells = <1>; | |
| 136 | ranges = <0 0x4a000000 0x22c000>; | |
| ee6c7507 | 137 | |
| d919501f TK |
138 | scm: scm@2000 { |
| 139 | compatible = "ti,dra7-scm-core", "simple-bus"; | |
| 140 | reg = <0x2000 0x2000>; | |
| ee6c7507 | 141 | #address-cells = <1>; |
| d919501f TK |
142 | #size-cells = <1>; |
| 143 | ranges = <0 0x2000 0x2000>; | |
| 144 | ||
| 145 | scm_conf: scm_conf@0 { | |
| cd455673 | 146 | compatible = "syscon", "simple-bus"; |
| d919501f TK |
147 | reg = <0x0 0x1400>; |
| 148 | #address-cells = <1>; | |
| 149 | #size-cells = <1>; | |
| 9a5e3f27 | 150 | ranges = <0 0x0 0x1400>; |
| d919501f | 151 | |
| 308cfdaf | 152 | pbias_regulator: pbias_regulator@e00 { |
| 737f146f | 153 | compatible = "ti,pbias-dra7", "ti,pbias-omap"; |
| d919501f TK |
154 | reg = <0xe00 0x4>; |
| 155 | syscon = <&scm_conf>; | |
| 156 | pbias_mmc_reg: pbias_mmc_omap5 { | |
| 157 | regulator-name = "pbias_mmc_omap5"; | |
| 158 | regulator-min-microvolt = <1800000>; | |
| 159 | regulator-max-microvolt = <3000000>; | |
| 160 | }; | |
| 161 | }; | |
| 2d5a3c80 TV |
162 | |
| 163 | scm_conf_clocks: clocks { | |
| 164 | #address-cells = <1>; | |
| 165 | #size-cells = <0>; | |
| 166 | }; | |
| d919501f TK |
167 | }; |
| 168 | ||
| 169 | dra7_pmx_core: pinmux@1400 { | |
| 170 | compatible = "ti,dra7-padconf", | |
| 171 | "pinctrl-single"; | |
| 1c5cb6fd | 172 | reg = <0x1400 0x0468>; |
| d919501f TK |
173 | #address-cells = <1>; |
| 174 | #size-cells = <0>; | |
| be76fd31 | 175 | #pinctrl-cells = <1>; |
| d919501f TK |
176 | #interrupt-cells = <1>; |
| 177 | interrupt-controller; | |
| 178 | pinctrl-single,register-width = <32>; | |
| 179 | pinctrl-single,function-mask = <0x3fffffff>; | |
| 180 | }; | |
| 33cb3a13 RQ |
181 | |
| 182 | scm_conf1: scm_conf@1c04 { | |
| 183 | compatible = "syscon"; | |
| 184 | reg = <0x1c04 0x0020>; | |
| 185 | }; | |
| 43acf169 KVA |
186 | |
| 187 | scm_conf_pcie: scm_conf@1c24 { | |
| 188 | compatible = "syscon"; | |
| 189 | reg = <0x1c24 0x0024>; | |
| 190 | }; | |
| 3d2a58bc PU |
191 | |
| 192 | sdma_xbar: dma-router@b78 { | |
| 193 | compatible = "ti,dra7-dma-crossbar"; | |
| 194 | reg = <0xb78 0xfc>; | |
| 195 | #dma-cells = <1>; | |
| 196 | dma-requests = <205>; | |
| 197 | ti,dma-safe-map = <0>; | |
| 198 | dma-masters = <&sdma>; | |
| 199 | }; | |
| 248948fb PU |
200 | |
| 201 | edma_xbar: dma-router@c78 { | |
| 202 | compatible = "ti,dra7-dma-crossbar"; | |
| 203 | reg = <0xc78 0x7c>; | |
| 204 | #dma-cells = <2>; | |
| 205 | dma-requests = <204>; | |
| 206 | ti,dma-safe-map = <0>; | |
| 207 | dma-masters = <&edma>; | |
| 208 | }; | |
| d919501f TK |
209 | }; |
| 210 | ||
| 211 | cm_core_aon: cm_core_aon@5000 { | |
| 212 | compatible = "ti,dra7-cm-core-aon"; | |
| 213 | reg = <0x5000 0x2000>; | |
| 214 | ||
| 215 | cm_core_aon_clocks: clocks { | |
| 216 | #address-cells = <1>; | |
| 217 | #size-cells = <0>; | |
| 218 | }; | |
| 219 | ||
| 220 | cm_core_aon_clockdomains: clockdomains { | |
| 221 | }; | |
| ee6c7507 TK |
222 | }; |
| 223 | ||
| d919501f TK |
224 | cm_core: cm_core@8000 { |
| 225 | compatible = "ti,dra7-cm-core"; | |
| 226 | reg = <0x8000 0x3000>; | |
| 227 | ||
| 228 | cm_core_clocks: clocks { | |
| 229 | #address-cells = <1>; | |
| 230 | #size-cells = <0>; | |
| 231 | }; | |
| 232 | ||
| 233 | cm_core_clockdomains: clockdomains { | |
| 234 | }; | |
| ee6c7507 | 235 | }; |
| d919501f | 236 | }; |
| ee6c7507 | 237 | |
| d919501f TK |
238 | l4_wkup: l4@4ae00000 { |
| 239 | compatible = "ti,dra7-l4-wkup", "simple-bus"; | |
| 240 | #address-cells = <1>; | |
| 241 | #size-cells = <1>; | |
| 242 | ranges = <0 0x4ae00000 0x3f000>; | |
| 243 | ||
| 244 | counter32k: counter@4000 { | |
| 245 | compatible = "ti,omap-counter32k"; | |
| 246 | reg = <0x4000 0x40>; | |
| 247 | ti,hwmods = "counter_32k"; | |
| 248 | }; | |
| 249 | ||
| 250 | prm: prm@6000 { | |
| 251 | compatible = "ti,dra7-prm"; | |
| 252 | reg = <0x6000 0x3000>; | |
| 253 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 254 | ||
| 255 | prm_clocks: clocks { | |
| 256 | #address-cells = <1>; | |
| 257 | #size-cells = <0>; | |
| 258 | }; | |
| 259 | ||
| 260 | prm_clockdomains: clockdomains { | |
| 261 | }; | |
| ee6c7507 | 262 | }; |
| 62e4feed DG |
263 | |
| 264 | scm_wkup: scm_conf@c000 { | |
| 265 | compatible = "syscon"; | |
| 266 | reg = <0xc000 0x1000>; | |
| 267 | }; | |
| ee6c7507 TK |
268 | }; |
| 269 | ||
| 18dcd79d KVA |
270 | axi@0 { |
| 271 | compatible = "simple-bus"; | |
| 272 | #size-cells = <1>; | |
| 273 | #address-cells = <1>; | |
| 274 | ranges = <0x51000000 0x51000000 0x3000 | |
| 275 | 0x0 0x20000000 0x10000000>; | |
| 73c8f0cb | 276 | pcie1: pcie@51000000 { |
| 18dcd79d KVA |
277 | compatible = "ti,dra7-pcie"; |
| 278 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; | |
| 279 | reg-names = "rc_dbics", "ti_conf", "config"; | |
| 280 | interrupts = <0 232 0x4>, <0 233 0x4>; | |
| 281 | #address-cells = <3>; | |
| 282 | #size-cells = <2>; | |
| 283 | device_type = "pci"; | |
| 284 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
| 285 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; | |
| 286 | #interrupt-cells = <1>; | |
| 287 | num-lanes = <1>; | |
| bed596da | 288 | linux,pci-domain = <0>; |
| 18dcd79d KVA |
289 | ti,hwmods = "pcie1"; |
| 290 | phys = <&pcie1_phy>; | |
| 291 | phy-names = "pcie-phy0"; | |
| 292 | interrupt-map-mask = <0 0 0 7>; | |
| 293 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, | |
| 294 | <0 0 0 2 &pcie1_intc 2>, | |
| 295 | <0 0 0 3 &pcie1_intc 3>, | |
| 296 | <0 0 0 4 &pcie1_intc 4>; | |
| 297 | pcie1_intc: interrupt-controller { | |
| 298 | interrupt-controller; | |
| 299 | #address-cells = <0>; | |
| 300 | #interrupt-cells = <1>; | |
| 301 | }; | |
| 302 | }; | |
| 303 | }; | |
| 304 | ||
| 305 | axi@1 { | |
| 306 | compatible = "simple-bus"; | |
| 307 | #size-cells = <1>; | |
| 308 | #address-cells = <1>; | |
| 309 | ranges = <0x51800000 0x51800000 0x3000 | |
| 310 | 0x0 0x30000000 0x10000000>; | |
| 311 | status = "disabled"; | |
| 605b3d30 | 312 | pcie@51800000 { |
| 18dcd79d KVA |
313 | compatible = "ti,dra7-pcie"; |
| 314 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; | |
| 315 | reg-names = "rc_dbics", "ti_conf", "config"; | |
| 316 | interrupts = <0 355 0x4>, <0 356 0x4>; | |
| 317 | #address-cells = <3>; | |
| 318 | #size-cells = <2>; | |
| 319 | device_type = "pci"; | |
| 320 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
| 321 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; | |
| 322 | #interrupt-cells = <1>; | |
| 323 | num-lanes = <1>; | |
| bed596da | 324 | linux,pci-domain = <1>; |
| 18dcd79d KVA |
325 | ti,hwmods = "pcie2"; |
| 326 | phys = <&pcie2_phy>; | |
| 327 | phy-names = "pcie-phy0"; | |
| 328 | interrupt-map-mask = <0 0 0 7>; | |
| 329 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, | |
| 330 | <0 0 0 2 &pcie2_intc 2>, | |
| 331 | <0 0 0 3 &pcie2_intc 3>, | |
| 332 | <0 0 0 4 &pcie2_intc 4>; | |
| 333 | pcie2_intc: interrupt-controller { | |
| 334 | interrupt-controller; | |
| 335 | #address-cells = <0>; | |
| 336 | #interrupt-cells = <1>; | |
| 337 | }; | |
| 338 | }; | |
| 339 | }; | |
| 340 | ||
| a5fa09b6 DG |
341 | ocmcram1: ocmcram@40300000 { |
| 342 | compatible = "mmio-sram"; | |
| 343 | reg = <0x40300000 0x80000>; | |
| 344 | ranges = <0x0 0x40300000 0x80000>; | |
| 345 | #address-cells = <1>; | |
| 346 | #size-cells = <1>; | |
| fae3a9f0 DG |
347 | /* |
| 348 | * This is a placeholder for an optional reserved | |
| 349 | * region for use by secure software. The size | |
| 350 | * of this region is not known until runtime so it | |
| 351 | * is set as zero to either be updated to reserve | |
| 352 | * space or left unchanged to leave all SRAM for use. | |
| 353 | * On HS parts that that require the reserved region | |
| 354 | * either the bootloader can update the size to | |
| 355 | * the required amount or the node can be overridden | |
| 356 | * from the board dts file for the secure platform. | |
| 357 | */ | |
| 358 | sram-hs@0 { | |
| 359 | compatible = "ti,secure-ram"; | |
| 360 | reg = <0x0 0x0>; | |
| 361 | }; | |
| a5fa09b6 DG |
362 | }; |
| 363 | ||
| 364 | /* | |
| 365 | * NOTE: ocmcram2 and ocmcram3 are not available on all | |
| 366 | * DRA7xx and AM57xx variants. Confirm availability in | |
| 367 | * the data manual for the exact part number in use | |
| 368 | * before enabling these nodes in the board dts file. | |
| 369 | */ | |
| 370 | ocmcram2: ocmcram@40400000 { | |
| 371 | status = "disabled"; | |
| 372 | compatible = "mmio-sram"; | |
| 373 | reg = <0x40400000 0x100000>; | |
| 374 | ranges = <0x0 0x40400000 0x100000>; | |
| 375 | #address-cells = <1>; | |
| 376 | #size-cells = <1>; | |
| 377 | }; | |
| 378 | ||
| 379 | ocmcram3: ocmcram@40500000 { | |
| 380 | status = "disabled"; | |
| 381 | compatible = "mmio-sram"; | |
| 382 | reg = <0x40500000 0x100000>; | |
| 383 | ranges = <0x0 0x40500000 0x100000>; | |
| 384 | #address-cells = <1>; | |
| 385 | #size-cells = <1>; | |
| 386 | }; | |
| 387 | ||
| f7397edf K |
388 | bandgap: bandgap@4a0021e0 { |
| 389 | reg = <0x4a0021e0 0xc | |
| 390 | 0x4a00232c 0xc | |
| 391 | 0x4a002380 0x2c | |
| 392 | 0x4a0023C0 0x3c | |
| 393 | 0x4a002564 0x8 | |
| 394 | 0x4a002574 0x50>; | |
| 395 | compatible = "ti,dra752-bandgap"; | |
| 396 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
| 397 | #thermal-sensor-cells = <1>; | |
| 398 | }; | |
| 399 | ||
| 99639ace SA |
400 | dsp1_system: dsp_system@40d00000 { |
| 401 | compatible = "syscon"; | |
| 402 | reg = <0x40d00000 0x100>; | |
| 403 | }; | |
| 404 | ||
| 6e58b8f1 S |
405 | sdma: dma-controller@4a056000 { |
| 406 | compatible = "ti,omap4430-sdma"; | |
| 407 | reg = <0x4a056000 0x1000>; | |
| a46631c4 S |
408 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 409 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
| 410 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
| 411 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 6e58b8f1 | 412 | #dma-cells = <1>; |
| 08d9b327 PU |
413 | dma-channels = <32>; |
| 414 | dma-requests = <127>; | |
| 6e58b8f1 S |
415 | }; |
| 416 | ||
| 248948fb PU |
417 | edma: edma@43300000 { |
| 418 | compatible = "ti,edma3-tpcc"; | |
| 419 | ti,hwmods = "tpcc"; | |
| 420 | reg = <0x43300000 0x100000>; | |
| 421 | reg-names = "edma3_cc"; | |
| 422 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, | |
| 423 | <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, | |
| 424 | <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
| a5206553 | 425 | interrupt-names = "edma3_ccint", "edma3_mperr", |
| 248948fb PU |
426 | "edma3_ccerrint"; |
| 427 | dma-requests = <64>; | |
| 428 | #dma-cells = <2>; | |
| 429 | ||
| 430 | ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; | |
| 431 | ||
| 432 | /* | |
| 433 | * memcpy is disabled, can be enabled with: | |
| 434 | * ti,edma-memcpy-channels = <20 21>; | |
| 435 | * for example. Note that these channels need to be | |
| 436 | * masked in the xbar as well. | |
| 437 | */ | |
| 438 | }; | |
| 439 | ||
| 440 | edma_tptc0: tptc@43400000 { | |
| 441 | compatible = "ti,edma3-tptc"; | |
| 442 | ti,hwmods = "tptc0"; | |
| 443 | reg = <0x43400000 0x100000>; | |
| 444 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; | |
| 445 | interrupt-names = "edma3_tcerrint"; | |
| 446 | }; | |
| 447 | ||
| 448 | edma_tptc1: tptc@43500000 { | |
| 449 | compatible = "ti,edma3-tptc"; | |
| 450 | ti,hwmods = "tptc1"; | |
| 451 | reg = <0x43500000 0x100000>; | |
| 452 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; | |
| 453 | interrupt-names = "edma3_tcerrint"; | |
| 454 | }; | |
| 455 | ||
| 6e58b8f1 S |
456 | gpio1: gpio@4ae10000 { |
| 457 | compatible = "ti,omap4-gpio"; | |
| 458 | reg = <0x4ae10000 0x200>; | |
| a46631c4 | 459 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
460 | ti,hwmods = "gpio1"; |
| 461 | gpio-controller; | |
| 462 | #gpio-cells = <2>; | |
| 463 | interrupt-controller; | |
| e49d519c | 464 | #interrupt-cells = <2>; |
| 6e58b8f1 S |
465 | }; |
| 466 | ||
| 467 | gpio2: gpio@48055000 { | |
| 468 | compatible = "ti,omap4-gpio"; | |
| 469 | reg = <0x48055000 0x200>; | |
| a46631c4 | 470 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
471 | ti,hwmods = "gpio2"; |
| 472 | gpio-controller; | |
| 473 | #gpio-cells = <2>; | |
| 474 | interrupt-controller; | |
| e49d519c | 475 | #interrupt-cells = <2>; |
| 6e58b8f1 S |
476 | }; |
| 477 | ||
| 478 | gpio3: gpio@48057000 { | |
| 479 | compatible = "ti,omap4-gpio"; | |
| 480 | reg = <0x48057000 0x200>; | |
| a46631c4 | 481 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
482 | ti,hwmods = "gpio3"; |
| 483 | gpio-controller; | |
| 484 | #gpio-cells = <2>; | |
| 485 | interrupt-controller; | |
| e49d519c | 486 | #interrupt-cells = <2>; |
| 6e58b8f1 S |
487 | }; |
| 488 | ||
| 489 | gpio4: gpio@48059000 { | |
| 490 | compatible = "ti,omap4-gpio"; | |
| 491 | reg = <0x48059000 0x200>; | |
| a46631c4 | 492 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
493 | ti,hwmods = "gpio4"; |
| 494 | gpio-controller; | |
| 495 | #gpio-cells = <2>; | |
| 496 | interrupt-controller; | |
| e49d519c | 497 | #interrupt-cells = <2>; |
| 6e58b8f1 S |
498 | }; |
| 499 | ||
| 500 | gpio5: gpio@4805b000 { | |
| 501 | compatible = "ti,omap4-gpio"; | |
| 502 | reg = <0x4805b000 0x200>; | |
| a46631c4 | 503 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
504 | ti,hwmods = "gpio5"; |
| 505 | gpio-controller; | |
| 506 | #gpio-cells = <2>; | |
| 507 | interrupt-controller; | |
| e49d519c | 508 | #interrupt-cells = <2>; |
| 6e58b8f1 S |
509 | }; |
| 510 | ||
| 511 | gpio6: gpio@4805d000 { | |
| 512 | compatible = "ti,omap4-gpio"; | |
| 513 | reg = <0x4805d000 0x200>; | |
| a46631c4 | 514 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
515 | ti,hwmods = "gpio6"; |
| 516 | gpio-controller; | |
| 517 | #gpio-cells = <2>; | |
| 518 | interrupt-controller; | |
| e49d519c | 519 | #interrupt-cells = <2>; |
| 6e58b8f1 S |
520 | }; |
| 521 | ||
| 522 | gpio7: gpio@48051000 { | |
| 523 | compatible = "ti,omap4-gpio"; | |
| 524 | reg = <0x48051000 0x200>; | |
| a46631c4 | 525 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
526 | ti,hwmods = "gpio7"; |
| 527 | gpio-controller; | |
| 528 | #gpio-cells = <2>; | |
| 529 | interrupt-controller; | |
| e49d519c | 530 | #interrupt-cells = <2>; |
| 6e58b8f1 S |
531 | }; |
| 532 | ||
| 533 | gpio8: gpio@48053000 { | |
| 534 | compatible = "ti,omap4-gpio"; | |
| 535 | reg = <0x48053000 0x200>; | |
| a46631c4 | 536 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
537 | ti,hwmods = "gpio8"; |
| 538 | gpio-controller; | |
| 539 | #gpio-cells = <2>; | |
| 540 | interrupt-controller; | |
| e49d519c | 541 | #interrupt-cells = <2>; |
| 6e58b8f1 S |
542 | }; |
| 543 | ||
| 544 | uart1: serial@4806a000 { | |
| 2a0e5ef6 | 545 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 546 | reg = <0x4806a000 0x100>; |
| 783d3186 | 547 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
548 | ti,hwmods = "uart1"; |
| 549 | clock-frequency = <48000000>; | |
| 550 | status = "disabled"; | |
| 3a0830de | 551 | dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; |
| f0199a29 | 552 | dma-names = "tx", "rx"; |
| 6e58b8f1 S |
553 | }; |
| 554 | ||
| 555 | uart2: serial@4806c000 { | |
| 2a0e5ef6 | 556 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 557 | reg = <0x4806c000 0x100>; |
| 783d3186 | 558 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
559 | ti,hwmods = "uart2"; |
| 560 | clock-frequency = <48000000>; | |
| 561 | status = "disabled"; | |
| 3a0830de | 562 | dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; |
| f0199a29 | 563 | dma-names = "tx", "rx"; |
| 6e58b8f1 S |
564 | }; |
| 565 | ||
| 566 | uart3: serial@48020000 { | |
| 2a0e5ef6 | 567 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 568 | reg = <0x48020000 0x100>; |
| 783d3186 | 569 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
570 | ti,hwmods = "uart3"; |
| 571 | clock-frequency = <48000000>; | |
| 572 | status = "disabled"; | |
| 3a0830de | 573 | dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; |
| f0199a29 | 574 | dma-names = "tx", "rx"; |
| 6e58b8f1 S |
575 | }; |
| 576 | ||
| 577 | uart4: serial@4806e000 { | |
| 2a0e5ef6 | 578 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 579 | reg = <0x4806e000 0x100>; |
| 783d3186 | 580 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
581 | ti,hwmods = "uart4"; |
| 582 | clock-frequency = <48000000>; | |
| 583 | status = "disabled"; | |
| 3a0830de | 584 | dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; |
| f0199a29 | 585 | dma-names = "tx", "rx"; |
| 6e58b8f1 S |
586 | }; |
| 587 | ||
| 588 | uart5: serial@48066000 { | |
| 2a0e5ef6 | 589 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 590 | reg = <0x48066000 0x100>; |
| 783d3186 | 591 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
592 | ti,hwmods = "uart5"; |
| 593 | clock-frequency = <48000000>; | |
| 594 | status = "disabled"; | |
| 3a0830de | 595 | dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; |
| f0199a29 | 596 | dma-names = "tx", "rx"; |
| 6e58b8f1 S |
597 | }; |
| 598 | ||
| 599 | uart6: serial@48068000 { | |
| 2a0e5ef6 | 600 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 601 | reg = <0x48068000 0x100>; |
| 783d3186 | 602 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
603 | ti,hwmods = "uart6"; |
| 604 | clock-frequency = <48000000>; | |
| 605 | status = "disabled"; | |
| 3a0830de | 606 | dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; |
| f0199a29 | 607 | dma-names = "tx", "rx"; |
| 6e58b8f1 S |
608 | }; |
| 609 | ||
| 610 | uart7: serial@48420000 { | |
| 2a0e5ef6 | 611 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 612 | reg = <0x48420000 0x100>; |
| 783d3186 | 613 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
614 | ti,hwmods = "uart7"; |
| 615 | clock-frequency = <48000000>; | |
| 616 | status = "disabled"; | |
| 617 | }; | |
| 618 | ||
| 619 | uart8: serial@48422000 { | |
| 2a0e5ef6 | 620 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 621 | reg = <0x48422000 0x100>; |
| 783d3186 | 622 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
623 | ti,hwmods = "uart8"; |
| 624 | clock-frequency = <48000000>; | |
| 625 | status = "disabled"; | |
| 626 | }; | |
| 627 | ||
| 628 | uart9: serial@48424000 { | |
| 2a0e5ef6 | 629 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 630 | reg = <0x48424000 0x100>; |
| 783d3186 | 631 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
632 | ti,hwmods = "uart9"; |
| 633 | clock-frequency = <48000000>; | |
| 634 | status = "disabled"; | |
| 635 | }; | |
| 636 | ||
| 637 | uart10: serial@4ae2b000 { | |
| 2a0e5ef6 | 638 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
| 6e58b8f1 | 639 | reg = <0x4ae2b000 0x100>; |
| 783d3186 | 640 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
641 | ti,hwmods = "uart10"; |
| 642 | clock-frequency = <48000000>; | |
| 643 | status = "disabled"; | |
| 644 | }; | |
| 645 | ||
| 38baefb3 SA |
646 | mailbox1: mailbox@4a0f4000 { |
| 647 | compatible = "ti,omap4-mailbox"; | |
| 648 | reg = <0x4a0f4000 0x200>; | |
| b46a6ae6 SA |
649 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 650 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 651 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 652 | ti,hwmods = "mailbox1"; |
| 24df0453 | 653 | #mbox-cells = <1>; |
| 38baefb3 SA |
654 | ti,mbox-num-users = <3>; |
| 655 | ti,mbox-num-fifos = <8>; | |
| 656 | status = "disabled"; | |
| 657 | }; | |
| 658 | ||
| 659 | mailbox2: mailbox@4883a000 { | |
| 660 | compatible = "ti,omap4-mailbox"; | |
| 661 | reg = <0x4883a000 0x200>; | |
| b46a6ae6 SA |
662 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| 663 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, | |
| 664 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
| 665 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 666 | ti,hwmods = "mailbox2"; |
| 24df0453 | 667 | #mbox-cells = <1>; |
| 38baefb3 SA |
668 | ti,mbox-num-users = <4>; |
| 669 | ti,mbox-num-fifos = <12>; | |
| 670 | status = "disabled"; | |
| 671 | }; | |
| 672 | ||
| 673 | mailbox3: mailbox@4883c000 { | |
| 674 | compatible = "ti,omap4-mailbox"; | |
| 675 | reg = <0x4883c000 0x200>; | |
| b46a6ae6 SA |
676 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| 677 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
| 678 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, | |
| 679 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 680 | ti,hwmods = "mailbox3"; |
| 24df0453 | 681 | #mbox-cells = <1>; |
| 38baefb3 SA |
682 | ti,mbox-num-users = <4>; |
| 683 | ti,mbox-num-fifos = <12>; | |
| 684 | status = "disabled"; | |
| 685 | }; | |
| 686 | ||
| 687 | mailbox4: mailbox@4883e000 { | |
| 688 | compatible = "ti,omap4-mailbox"; | |
| 689 | reg = <0x4883e000 0x200>; | |
| b46a6ae6 SA |
690 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 691 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
| 692 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
| 693 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 694 | ti,hwmods = "mailbox4"; |
| 24df0453 | 695 | #mbox-cells = <1>; |
| 38baefb3 SA |
696 | ti,mbox-num-users = <4>; |
| 697 | ti,mbox-num-fifos = <12>; | |
| 698 | status = "disabled"; | |
| 699 | }; | |
| 700 | ||
| 701 | mailbox5: mailbox@48840000 { | |
| 702 | compatible = "ti,omap4-mailbox"; | |
| 703 | reg = <0x48840000 0x200>; | |
| b46a6ae6 SA |
704 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 705 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
| 706 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
| 707 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 708 | ti,hwmods = "mailbox5"; |
| 24df0453 | 709 | #mbox-cells = <1>; |
| 38baefb3 SA |
710 | ti,mbox-num-users = <4>; |
| 711 | ti,mbox-num-fifos = <12>; | |
| 712 | status = "disabled"; | |
| 713 | }; | |
| 714 | ||
| 715 | mailbox6: mailbox@48842000 { | |
| 716 | compatible = "ti,omap4-mailbox"; | |
| 717 | reg = <0x48842000 0x200>; | |
| b46a6ae6 SA |
718 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 719 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
| 720 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
| 721 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 722 | ti,hwmods = "mailbox6"; |
| 24df0453 | 723 | #mbox-cells = <1>; |
| 38baefb3 SA |
724 | ti,mbox-num-users = <4>; |
| 725 | ti,mbox-num-fifos = <12>; | |
| 726 | status = "disabled"; | |
| 727 | }; | |
| 728 | ||
| 729 | mailbox7: mailbox@48844000 { | |
| 730 | compatible = "ti,omap4-mailbox"; | |
| 731 | reg = <0x48844000 0x200>; | |
| b46a6ae6 SA |
732 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| 733 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
| 734 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
| 735 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 736 | ti,hwmods = "mailbox7"; |
| 24df0453 | 737 | #mbox-cells = <1>; |
| 38baefb3 SA |
738 | ti,mbox-num-users = <4>; |
| 739 | ti,mbox-num-fifos = <12>; | |
| 740 | status = "disabled"; | |
| 741 | }; | |
| 742 | ||
| 743 | mailbox8: mailbox@48846000 { | |
| 744 | compatible = "ti,omap4-mailbox"; | |
| 745 | reg = <0x48846000 0x200>; | |
| b46a6ae6 SA |
746 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| 747 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, | |
| 748 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, | |
| 749 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 750 | ti,hwmods = "mailbox8"; |
| 24df0453 | 751 | #mbox-cells = <1>; |
| 38baefb3 SA |
752 | ti,mbox-num-users = <4>; |
| 753 | ti,mbox-num-fifos = <12>; | |
| 754 | status = "disabled"; | |
| 755 | }; | |
| 756 | ||
| 757 | mailbox9: mailbox@4885e000 { | |
| 758 | compatible = "ti,omap4-mailbox"; | |
| 759 | reg = <0x4885e000 0x200>; | |
| b46a6ae6 SA |
760 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| 761 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, | |
| 762 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, | |
| 763 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 764 | ti,hwmods = "mailbox9"; |
| 24df0453 | 765 | #mbox-cells = <1>; |
| 38baefb3 SA |
766 | ti,mbox-num-users = <4>; |
| 767 | ti,mbox-num-fifos = <12>; | |
| 768 | status = "disabled"; | |
| 769 | }; | |
| 770 | ||
| 771 | mailbox10: mailbox@48860000 { | |
| 772 | compatible = "ti,omap4-mailbox"; | |
| 773 | reg = <0x48860000 0x200>; | |
| b46a6ae6 SA |
774 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| 775 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, | |
| 776 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, | |
| 777 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 778 | ti,hwmods = "mailbox10"; |
| 24df0453 | 779 | #mbox-cells = <1>; |
| 38baefb3 SA |
780 | ti,mbox-num-users = <4>; |
| 781 | ti,mbox-num-fifos = <12>; | |
| 782 | status = "disabled"; | |
| 783 | }; | |
| 784 | ||
| 785 | mailbox11: mailbox@48862000 { | |
| 786 | compatible = "ti,omap4-mailbox"; | |
| 787 | reg = <0x48862000 0x200>; | |
| b46a6ae6 SA |
788 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| 789 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, | |
| 790 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, | |
| 791 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 792 | ti,hwmods = "mailbox11"; |
| 24df0453 | 793 | #mbox-cells = <1>; |
| 38baefb3 SA |
794 | ti,mbox-num-users = <4>; |
| 795 | ti,mbox-num-fifos = <12>; | |
| 796 | status = "disabled"; | |
| 797 | }; | |
| 798 | ||
| 799 | mailbox12: mailbox@48864000 { | |
| 800 | compatible = "ti,omap4-mailbox"; | |
| 801 | reg = <0x48864000 0x200>; | |
| b46a6ae6 SA |
802 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
| 803 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, | |
| 804 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
| 805 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 806 | ti,hwmods = "mailbox12"; |
| 24df0453 | 807 | #mbox-cells = <1>; |
| 38baefb3 SA |
808 | ti,mbox-num-users = <4>; |
| 809 | ti,mbox-num-fifos = <12>; | |
| 810 | status = "disabled"; | |
| 811 | }; | |
| 812 | ||
| 813 | mailbox13: mailbox@48802000 { | |
| 814 | compatible = "ti,omap4-mailbox"; | |
| 815 | reg = <0x48802000 0x200>; | |
| b46a6ae6 SA |
816 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| 817 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, | |
| 818 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, | |
| 819 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; | |
| 38baefb3 | 820 | ti,hwmods = "mailbox13"; |
| 24df0453 | 821 | #mbox-cells = <1>; |
| 38baefb3 SA |
822 | ti,mbox-num-users = <4>; |
| 823 | ti,mbox-num-fifos = <12>; | |
| 824 | status = "disabled"; | |
| 825 | }; | |
| 826 | ||
| 6e58b8f1 S |
827 | timer1: timer@4ae18000 { |
| 828 | compatible = "ti,omap5430-timer"; | |
| 829 | reg = <0x4ae18000 0x80>; | |
| a46631c4 | 830 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
831 | ti,hwmods = "timer1"; |
| 832 | ti,timer-alwon; | |
| 833 | }; | |
| 834 | ||
| 835 | timer2: timer@48032000 { | |
| 836 | compatible = "ti,omap5430-timer"; | |
| 837 | reg = <0x48032000 0x80>; | |
| a46631c4 | 838 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
839 | ti,hwmods = "timer2"; |
| 840 | }; | |
| 841 | ||
| 842 | timer3: timer@48034000 { | |
| 843 | compatible = "ti,omap5430-timer"; | |
| 844 | reg = <0x48034000 0x80>; | |
| a46631c4 | 845 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
846 | ti,hwmods = "timer3"; |
| 847 | }; | |
| 848 | ||
| 849 | timer4: timer@48036000 { | |
| 850 | compatible = "ti,omap5430-timer"; | |
| 851 | reg = <0x48036000 0x80>; | |
| a46631c4 | 852 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
853 | ti,hwmods = "timer4"; |
| 854 | }; | |
| 855 | ||
| 856 | timer5: timer@48820000 { | |
| 857 | compatible = "ti,omap5430-timer"; | |
| 858 | reg = <0x48820000 0x80>; | |
| a46631c4 | 859 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 860 | ti,hwmods = "timer5"; |
| 6e58b8f1 S |
861 | }; |
| 862 | ||
| 863 | timer6: timer@48822000 { | |
| 864 | compatible = "ti,omap5430-timer"; | |
| 865 | reg = <0x48822000 0x80>; | |
| a46631c4 | 866 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 867 | ti,hwmods = "timer6"; |
| 6e58b8f1 S |
868 | }; |
| 869 | ||
| 870 | timer7: timer@48824000 { | |
| 871 | compatible = "ti,omap5430-timer"; | |
| 872 | reg = <0x48824000 0x80>; | |
| a46631c4 | 873 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 874 | ti,hwmods = "timer7"; |
| 6e58b8f1 S |
875 | }; |
| 876 | ||
| 877 | timer8: timer@48826000 { | |
| 878 | compatible = "ti,omap5430-timer"; | |
| 879 | reg = <0x48826000 0x80>; | |
| a46631c4 | 880 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 881 | ti,hwmods = "timer8"; |
| 6e58b8f1 S |
882 | }; |
| 883 | ||
| 884 | timer9: timer@4803e000 { | |
| 885 | compatible = "ti,omap5430-timer"; | |
| 886 | reg = <0x4803e000 0x80>; | |
| a46631c4 | 887 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
888 | ti,hwmods = "timer9"; |
| 889 | }; | |
| 890 | ||
| 891 | timer10: timer@48086000 { | |
| 892 | compatible = "ti,omap5430-timer"; | |
| 893 | reg = <0x48086000 0x80>; | |
| a46631c4 | 894 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
895 | ti,hwmods = "timer10"; |
| 896 | }; | |
| 897 | ||
| 898 | timer11: timer@48088000 { | |
| 899 | compatible = "ti,omap5430-timer"; | |
| 900 | reg = <0x48088000 0x80>; | |
| a46631c4 | 901 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 902 | ti,hwmods = "timer11"; |
| 6e58b8f1 S |
903 | }; |
| 904 | ||
| d79852a7 SA |
905 | timer12: timer@4ae20000 { |
| 906 | compatible = "ti,omap5430-timer"; | |
| 907 | reg = <0x4ae20000 0x80>; | |
| 908 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 909 | ti,hwmods = "timer12"; | |
| 910 | ti,timer-alwon; | |
| 911 | ti,timer-secure; | |
| 912 | }; | |
| 913 | ||
| 6e58b8f1 S |
914 | timer13: timer@48828000 { |
| 915 | compatible = "ti,omap5430-timer"; | |
| 916 | reg = <0x48828000 0x80>; | |
| a46631c4 | 917 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 918 | ti,hwmods = "timer13"; |
| 6e58b8f1 S |
919 | }; |
| 920 | ||
| 921 | timer14: timer@4882a000 { | |
| 922 | compatible = "ti,omap5430-timer"; | |
| 923 | reg = <0x4882a000 0x80>; | |
| a46631c4 | 924 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 925 | ti,hwmods = "timer14"; |
| 6e58b8f1 S |
926 | }; |
| 927 | ||
| 928 | timer15: timer@4882c000 { | |
| 929 | compatible = "ti,omap5430-timer"; | |
| 930 | reg = <0x4882c000 0x80>; | |
| a46631c4 | 931 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 932 | ti,hwmods = "timer15"; |
| 6e58b8f1 S |
933 | }; |
| 934 | ||
| 935 | timer16: timer@4882e000 { | |
| 936 | compatible = "ti,omap5430-timer"; | |
| 937 | reg = <0x4882e000 0x80>; | |
| a46631c4 | 938 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 | 939 | ti,hwmods = "timer16"; |
| 6e58b8f1 S |
940 | }; |
| 941 | ||
| 942 | wdt2: wdt@4ae14000 { | |
| be668835 | 943 | compatible = "ti,omap3-wdt"; |
| 6e58b8f1 | 944 | reg = <0x4ae14000 0x80>; |
| a46631c4 | 945 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
946 | ti,hwmods = "wd_timer2"; |
| 947 | }; | |
| 948 | ||
| dbd7c191 SA |
949 | hwspinlock: spinlock@4a0f6000 { |
| 950 | compatible = "ti,omap4-hwspinlock"; | |
| 951 | reg = <0x4a0f6000 0x1000>; | |
| 952 | ti,hwmods = "spinlock"; | |
| 953 | #hwlock-cells = <1>; | |
| 954 | }; | |
| 955 | ||
| 1a5fe3ca AT |
956 | dmm@4e000000 { |
| 957 | compatible = "ti,omap5-dmm"; | |
| 958 | reg = <0x4e000000 0x800>; | |
| a46631c4 | 959 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 1a5fe3ca AT |
960 | ti,hwmods = "dmm"; |
| 961 | }; | |
| 962 | ||
| 6e58b8f1 S |
963 | i2c1: i2c@48070000 { |
| 964 | compatible = "ti,omap4-i2c"; | |
| 965 | reg = <0x48070000 0x100>; | |
| a46631c4 | 966 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
967 | #address-cells = <1>; |
| 968 | #size-cells = <0>; | |
| 969 | ti,hwmods = "i2c1"; | |
| 970 | status = "disabled"; | |
| 971 | }; | |
| 972 | ||
| 973 | i2c2: i2c@48072000 { | |
| 974 | compatible = "ti,omap4-i2c"; | |
| 975 | reg = <0x48072000 0x100>; | |
| a46631c4 | 976 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
977 | #address-cells = <1>; |
| 978 | #size-cells = <0>; | |
| 979 | ti,hwmods = "i2c2"; | |
| 980 | status = "disabled"; | |
| 981 | }; | |
| 982 | ||
| 983 | i2c3: i2c@48060000 { | |
| 984 | compatible = "ti,omap4-i2c"; | |
| 985 | reg = <0x48060000 0x100>; | |
| a46631c4 | 986 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
987 | #address-cells = <1>; |
| 988 | #size-cells = <0>; | |
| 989 | ti,hwmods = "i2c3"; | |
| 990 | status = "disabled"; | |
| 991 | }; | |
| 992 | ||
| 993 | i2c4: i2c@4807a000 { | |
| 994 | compatible = "ti,omap4-i2c"; | |
| 995 | reg = <0x4807a000 0x100>; | |
| a46631c4 | 996 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
997 | #address-cells = <1>; |
| 998 | #size-cells = <0>; | |
| 999 | ti,hwmods = "i2c4"; | |
| 1000 | status = "disabled"; | |
| 1001 | }; | |
| 1002 | ||
| 1003 | i2c5: i2c@4807c000 { | |
| 1004 | compatible = "ti,omap4-i2c"; | |
| 1005 | reg = <0x4807c000 0x100>; | |
| a46631c4 | 1006 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1007 | #address-cells = <1>; |
| 1008 | #size-cells = <0>; | |
| 1009 | ti,hwmods = "i2c5"; | |
| 1010 | status = "disabled"; | |
| 1011 | }; | |
| 1012 | ||
| 1013 | mmc1: mmc@4809c000 { | |
| 1014 | compatible = "ti,omap4-hsmmc"; | |
| 1015 | reg = <0x4809c000 0x400>; | |
| a46631c4 | 1016 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1017 | ti,hwmods = "mmc1"; |
| 1018 | ti,dual-volt; | |
| 1019 | ti,needs-special-reset; | |
| 3a0830de | 1020 | dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; |
| 6e58b8f1 S |
1021 | dma-names = "tx", "rx"; |
| 1022 | status = "disabled"; | |
| cd042fe5 | 1023 | pbias-supply = <&pbias_mmc_reg>; |
| 6e58b8f1 S |
1024 | }; |
| 1025 | ||
| 1026 | mmc2: mmc@480b4000 { | |
| 1027 | compatible = "ti,omap4-hsmmc"; | |
| 1028 | reg = <0x480b4000 0x400>; | |
| a46631c4 | 1029 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1030 | ti,hwmods = "mmc2"; |
| 1031 | ti,needs-special-reset; | |
| 3a0830de | 1032 | dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; |
| 6e58b8f1 S |
1033 | dma-names = "tx", "rx"; |
| 1034 | status = "disabled"; | |
| 1035 | }; | |
| 1036 | ||
| 1037 | mmc3: mmc@480ad000 { | |
| 1038 | compatible = "ti,omap4-hsmmc"; | |
| 1039 | reg = <0x480ad000 0x400>; | |
| a46631c4 | 1040 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1041 | ti,hwmods = "mmc3"; |
| 1042 | ti,needs-special-reset; | |
| 3a0830de | 1043 | dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; |
| 6e58b8f1 S |
1044 | dma-names = "tx", "rx"; |
| 1045 | status = "disabled"; | |
| 1046 | }; | |
| 1047 | ||
| 1048 | mmc4: mmc@480d1000 { | |
| 1049 | compatible = "ti,omap4-hsmmc"; | |
| 1050 | reg = <0x480d1000 0x400>; | |
| a46631c4 | 1051 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1052 | ti,hwmods = "mmc4"; |
| 1053 | ti,needs-special-reset; | |
| 3a0830de | 1054 | dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; |
| 6e58b8f1 S |
1055 | dma-names = "tx", "rx"; |
| 1056 | status = "disabled"; | |
| 1057 | }; | |
| 1058 | ||
| 2c7e07c5 SA |
1059 | mmu0_dsp1: mmu@40d01000 { |
| 1060 | compatible = "ti,dra7-dsp-iommu"; | |
| 1061 | reg = <0x40d01000 0x100>; | |
| 1062 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 1063 | ti,hwmods = "mmu0_dsp1"; | |
| 1064 | #iommu-cells = <0>; | |
| 1065 | ti,syscon-mmuconfig = <&dsp1_system 0x0>; | |
| 1066 | status = "disabled"; | |
| 1067 | }; | |
| 1068 | ||
| 1069 | mmu1_dsp1: mmu@40d02000 { | |
| 1070 | compatible = "ti,dra7-dsp-iommu"; | |
| 1071 | reg = <0x40d02000 0x100>; | |
| 1072 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
| 1073 | ti,hwmods = "mmu1_dsp1"; | |
| 1074 | #iommu-cells = <0>; | |
| 1075 | ti,syscon-mmuconfig = <&dsp1_system 0x1>; | |
| 1076 | status = "disabled"; | |
| 1077 | }; | |
| 1078 | ||
| 1079 | mmu_ipu1: mmu@58882000 { | |
| 1080 | compatible = "ti,dra7-iommu"; | |
| 1081 | reg = <0x58882000 0x100>; | |
| 1082 | interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; | |
| 1083 | ti,hwmods = "mmu_ipu1"; | |
| 1084 | #iommu-cells = <0>; | |
| 1085 | ti,iommu-bus-err-back; | |
| 1086 | status = "disabled"; | |
| 1087 | }; | |
| 1088 | ||
| 1089 | mmu_ipu2: mmu@55082000 { | |
| 1090 | compatible = "ti,dra7-iommu"; | |
| 1091 | reg = <0x55082000 0x100>; | |
| 1092 | interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; | |
| 1093 | ti,hwmods = "mmu_ipu2"; | |
| 1094 | #iommu-cells = <0>; | |
| 1095 | ti,iommu-bus-err-back; | |
| 1096 | status = "disabled"; | |
| 1097 | }; | |
| 1098 | ||
| a1b8ee10 NM |
1099 | abb_mpu: regulator-abb-mpu { |
| 1100 | compatible = "ti,abb-v3"; | |
| 1101 | regulator-name = "abb_mpu"; | |
| 1102 | #address-cells = <0>; | |
| 1103 | #size-cells = <0>; | |
| 1104 | clocks = <&sys_clkin1>; | |
| 1105 | ti,settling-time = <50>; | |
| 1106 | ti,clock-cycles = <16>; | |
| 1107 | ||
| 1108 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, | |
| 18227346 | 1109 | <0x4ae06014 0x4>, <0x4a003b20 0xc>, |
| a1b8ee10 NM |
1110 | <0x4ae0c158 0x4>; |
| 1111 | reg-names = "setup-address", "control-address", | |
| 1112 | "int-address", "efuse-address", | |
| 1113 | "ldo-address"; | |
| 1114 | ti,tranxdone-status-mask = <0x80>; | |
| 1115 | /* LDOVBBMPU_FBB_MUX_CTRL */ | |
| 1116 | ti,ldovbb-override-mask = <0x400>; | |
| 1117 | /* LDOVBBMPU_FBB_VSET_OUT */ | |
| 1118 | ti,ldovbb-vset-mask = <0x1F>; | |
| 1119 | ||
| 1120 | /* | |
| 1121 | * NOTE: only FBB mode used but actual vset will | |
| 1122 | * determine final biasing | |
| 1123 | */ | |
| 1124 | ti,abb_info = < | |
| 1125 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
| 1126 | 1060000 0 0x0 0 0x02000000 0x01F00000 | |
| 1127 | 1160000 0 0x4 0 0x02000000 0x01F00000 | |
| 1128 | 1210000 0 0x8 0 0x02000000 0x01F00000 | |
| 1129 | >; | |
| 1130 | }; | |
| 1131 | ||
| 1132 | abb_ivahd: regulator-abb-ivahd { | |
| 1133 | compatible = "ti,abb-v3"; | |
| 1134 | regulator-name = "abb_ivahd"; | |
| 1135 | #address-cells = <0>; | |
| 1136 | #size-cells = <0>; | |
| 1137 | clocks = <&sys_clkin1>; | |
| 1138 | ti,settling-time = <50>; | |
| 1139 | ti,clock-cycles = <16>; | |
| 1140 | ||
| 1141 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, | |
| 18227346 | 1142 | <0x4ae06010 0x4>, <0x4a0025cc 0xc>, |
| a1b8ee10 NM |
1143 | <0x4a002470 0x4>; |
| 1144 | reg-names = "setup-address", "control-address", | |
| 1145 | "int-address", "efuse-address", | |
| 1146 | "ldo-address"; | |
| 1147 | ti,tranxdone-status-mask = <0x40000000>; | |
| 1148 | /* LDOVBBIVA_FBB_MUX_CTRL */ | |
| 1149 | ti,ldovbb-override-mask = <0x400>; | |
| 1150 | /* LDOVBBIVA_FBB_VSET_OUT */ | |
| 1151 | ti,ldovbb-vset-mask = <0x1F>; | |
| 1152 | ||
| 1153 | /* | |
| 1154 | * NOTE: only FBB mode used but actual vset will | |
| 1155 | * determine final biasing | |
| 1156 | */ | |
| 1157 | ti,abb_info = < | |
| 1158 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
| 1159 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
| 1160 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
| 1161 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
| 1162 | >; | |
| 1163 | }; | |
| 1164 | ||
| 1165 | abb_dspeve: regulator-abb-dspeve { | |
| 1166 | compatible = "ti,abb-v3"; | |
| 1167 | regulator-name = "abb_dspeve"; | |
| 1168 | #address-cells = <0>; | |
| 1169 | #size-cells = <0>; | |
| 1170 | clocks = <&sys_clkin1>; | |
| 1171 | ti,settling-time = <50>; | |
| 1172 | ti,clock-cycles = <16>; | |
| 1173 | ||
| 1174 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, | |
| 18227346 | 1175 | <0x4ae06010 0x4>, <0x4a0025e0 0xc>, |
| a1b8ee10 NM |
1176 | <0x4a00246c 0x4>; |
| 1177 | reg-names = "setup-address", "control-address", | |
| 1178 | "int-address", "efuse-address", | |
| 1179 | "ldo-address"; | |
| 1180 | ti,tranxdone-status-mask = <0x20000000>; | |
| 1181 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ | |
| 1182 | ti,ldovbb-override-mask = <0x400>; | |
| 1183 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ | |
| 1184 | ti,ldovbb-vset-mask = <0x1F>; | |
| 1185 | ||
| 1186 | /* | |
| 1187 | * NOTE: only FBB mode used but actual vset will | |
| 1188 | * determine final biasing | |
| 1189 | */ | |
| 1190 | ti,abb_info = < | |
| 1191 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
| 1192 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
| 1193 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
| 1194 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
| 1195 | >; | |
| 1196 | }; | |
| 1197 | ||
| 1198 | abb_gpu: regulator-abb-gpu { | |
| 1199 | compatible = "ti,abb-v3"; | |
| 1200 | regulator-name = "abb_gpu"; | |
| 1201 | #address-cells = <0>; | |
| 1202 | #size-cells = <0>; | |
| 1203 | clocks = <&sys_clkin1>; | |
| 1204 | ti,settling-time = <50>; | |
| 1205 | ti,clock-cycles = <16>; | |
| 1206 | ||
| 1207 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, | |
| 18227346 | 1208 | <0x4ae06010 0x4>, <0x4a003b08 0xc>, |
| a1b8ee10 NM |
1209 | <0x4ae0c154 0x4>; |
| 1210 | reg-names = "setup-address", "control-address", | |
| 1211 | "int-address", "efuse-address", | |
| 1212 | "ldo-address"; | |
| 1213 | ti,tranxdone-status-mask = <0x10000000>; | |
| 1214 | /* LDOVBBGPU_FBB_MUX_CTRL */ | |
| 1215 | ti,ldovbb-override-mask = <0x400>; | |
| 1216 | /* LDOVBBGPU_FBB_VSET_OUT */ | |
| 1217 | ti,ldovbb-vset-mask = <0x1F>; | |
| 1218 | ||
| 1219 | /* | |
| 1220 | * NOTE: only FBB mode used but actual vset will | |
| 1221 | * determine final biasing | |
| 1222 | */ | |
| 1223 | ti,abb_info = < | |
| 1224 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
| 1225 | 1090000 0 0x0 0 0x02000000 0x01F00000 | |
| 1226 | 1210000 0 0x4 0 0x02000000 0x01F00000 | |
| 1227 | 1280000 0 0x8 0 0x02000000 0x01F00000 | |
| 1228 | >; | |
| 1229 | }; | |
| 1230 | ||
| 6e58b8f1 S |
1231 | mcspi1: spi@48098000 { |
| 1232 | compatible = "ti,omap4-mcspi"; | |
| 1233 | reg = <0x48098000 0x200>; | |
| a46631c4 | 1234 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1235 | #address-cells = <1>; |
| 1236 | #size-cells = <0>; | |
| 1237 | ti,hwmods = "mcspi1"; | |
| 1238 | ti,spi-num-cs = <4>; | |
| 3a0830de PU |
1239 | dmas = <&sdma_xbar 35>, |
| 1240 | <&sdma_xbar 36>, | |
| 1241 | <&sdma_xbar 37>, | |
| 1242 | <&sdma_xbar 38>, | |
| 1243 | <&sdma_xbar 39>, | |
| 1244 | <&sdma_xbar 40>, | |
| 1245 | <&sdma_xbar 41>, | |
| 1246 | <&sdma_xbar 42>; | |
| 6e58b8f1 S |
1247 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 1248 | "tx2", "rx2", "tx3", "rx3"; | |
| 1249 | status = "disabled"; | |
| 1250 | }; | |
| 1251 | ||
| 1252 | mcspi2: spi@4809a000 { | |
| 1253 | compatible = "ti,omap4-mcspi"; | |
| 1254 | reg = <0x4809a000 0x200>; | |
| a46631c4 | 1255 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1256 | #address-cells = <1>; |
| 1257 | #size-cells = <0>; | |
| 1258 | ti,hwmods = "mcspi2"; | |
| 1259 | ti,spi-num-cs = <2>; | |
| 3a0830de PU |
1260 | dmas = <&sdma_xbar 43>, |
| 1261 | <&sdma_xbar 44>, | |
| 1262 | <&sdma_xbar 45>, | |
| 1263 | <&sdma_xbar 46>; | |
| 6e58b8f1 S |
1264 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 1265 | status = "disabled"; | |
| 1266 | }; | |
| 1267 | ||
| 1268 | mcspi3: spi@480b8000 { | |
| 1269 | compatible = "ti,omap4-mcspi"; | |
| 1270 | reg = <0x480b8000 0x200>; | |
| a46631c4 | 1271 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1272 | #address-cells = <1>; |
| 1273 | #size-cells = <0>; | |
| 1274 | ti,hwmods = "mcspi3"; | |
| 1275 | ti,spi-num-cs = <2>; | |
| 3a0830de | 1276 | dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; |
| 6e58b8f1 S |
1277 | dma-names = "tx0", "rx0"; |
| 1278 | status = "disabled"; | |
| 1279 | }; | |
| 1280 | ||
| 1281 | mcspi4: spi@480ba000 { | |
| 1282 | compatible = "ti,omap4-mcspi"; | |
| 1283 | reg = <0x480ba000 0x200>; | |
| a46631c4 | 1284 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| 6e58b8f1 S |
1285 | #address-cells = <1>; |
| 1286 | #size-cells = <0>; | |
| 1287 | ti,hwmods = "mcspi4"; | |
| 1288 | ti,spi-num-cs = <1>; | |
| 3a0830de | 1289 | dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; |
| 6e58b8f1 S |
1290 | dma-names = "tx0", "rx0"; |
| 1291 | status = "disabled"; | |
| 1292 | }; | |
| dc2dd5b8 SP |
1293 | |
| 1294 | qspi: qspi@4b300000 { | |
| 1295 | compatible = "ti,dra7xxx-qspi"; | |
| 1929d0b5 V |
1296 | reg = <0x4b300000 0x100>, |
| 1297 | <0x5c000000 0x4000000>; | |
| 1298 | reg-names = "qspi_base", "qspi_mmap"; | |
| 1299 | syscon-chipselects = <&scm_conf 0x558>; | |
| dc2dd5b8 SP |
1300 | #address-cells = <1>; |
| 1301 | #size-cells = <0>; | |
| 1302 | ti,hwmods = "qspi"; | |
| 1303 | clocks = <&qspi_gfclk_div>; | |
| 1304 | clock-names = "fck"; | |
| 1305 | num-cs = <4>; | |
| a46631c4 | 1306 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
| dc2dd5b8 SP |
1307 | status = "disabled"; |
| 1308 | }; | |
| 7be80569 | 1309 | |
| 7be80569 B |
1310 | /* OCP2SCP3 */ |
| 1311 | ocp2scp@4a090000 { | |
| 1312 | compatible = "ti,omap-ocp2scp"; | |
| 1313 | #address-cells = <1>; | |
| 1314 | #size-cells = <1>; | |
| 1315 | ranges; | |
| 1316 | reg = <0x4a090000 0x20>; | |
| 1317 | ti,hwmods = "ocp2scp3"; | |
| 1318 | sata_phy: phy@4A096000 { | |
| 1319 | compatible = "ti,phy-pipe3-sata"; | |
| 1320 | reg = <0x4A096000 0x80>, /* phy_rx */ | |
| 1321 | <0x4A096400 0x64>, /* phy_tx */ | |
| 1322 | <0x4A096800 0x40>; /* pll_ctrl */ | |
| 1323 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
| 2338c76a | 1324 | syscon-phy-power = <&scm_conf 0x374>; |
| 773c5a0f RQ |
1325 | clocks = <&sys_clkin1>, <&sata_ref_clk>; |
| 1326 | clock-names = "sysclk", "refclk"; | |
| 257d5d9a | 1327 | syscon-pllreset = <&scm_conf 0x3fc>; |
| 7be80569 B |
1328 | #phy-cells = <0>; |
| 1329 | }; | |
| 692df0ef KVA |
1330 | |
| 1331 | pcie1_phy: pciephy@4a094000 { | |
| 1332 | compatible = "ti,phy-pipe3-pcie"; | |
| 1333 | reg = <0x4a094000 0x80>, /* phy_rx */ | |
| 1334 | <0x4a094400 0x64>; /* phy_tx */ | |
| 1335 | reg-names = "phy_rx", "phy_tx"; | |
| 6921e58b KVA |
1336 | syscon-phy-power = <&scm_conf_pcie 0x1c>; |
| 1337 | syscon-pcs = <&scm_conf_pcie 0x10>; | |
| 692df0ef KVA |
1338 | clocks = <&dpll_pcie_ref_ck>, |
| 1339 | <&dpll_pcie_ref_m2ldo_ck>, | |
| 1340 | <&optfclk_pciephy1_32khz>, | |
| 1341 | <&optfclk_pciephy1_clk>, | |
| 1342 | <&optfclk_pciephy1_div_clk>, | |
| 6921e58b KVA |
1343 | <&optfclk_pciephy_div>, |
| 1344 | <&sys_clkin1>; | |
| 692df0ef KVA |
1345 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1346 | "wkupclk", "refclk", | |
| 6921e58b | 1347 | "div-clk", "phy-div", "sysclk"; |
| 692df0ef | 1348 | #phy-cells = <0>; |
| 692df0ef KVA |
1349 | }; |
| 1350 | ||
| 1351 | pcie2_phy: pciephy@4a095000 { | |
| 1352 | compatible = "ti,phy-pipe3-pcie"; | |
| 1353 | reg = <0x4a095000 0x80>, /* phy_rx */ | |
| 1354 | <0x4a095400 0x64>; /* phy_tx */ | |
| 1355 | reg-names = "phy_rx", "phy_tx"; | |
| 6921e58b KVA |
1356 | syscon-phy-power = <&scm_conf_pcie 0x20>; |
| 1357 | syscon-pcs = <&scm_conf_pcie 0x10>; | |
| 692df0ef KVA |
1358 | clocks = <&dpll_pcie_ref_ck>, |
| 1359 | <&dpll_pcie_ref_m2ldo_ck>, | |
| 1360 | <&optfclk_pciephy2_32khz>, | |
| 1361 | <&optfclk_pciephy2_clk>, | |
| 1362 | <&optfclk_pciephy2_div_clk>, | |
| 6921e58b KVA |
1363 | <&optfclk_pciephy_div>, |
| 1364 | <&sys_clkin1>; | |
| 692df0ef KVA |
1365 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1366 | "wkupclk", "refclk", | |
| 6921e58b | 1367 | "div-clk", "phy-div", "sysclk"; |
| 692df0ef | 1368 | #phy-cells = <0>; |
| 692df0ef KVA |
1369 | status = "disabled"; |
| 1370 | }; | |
| 7be80569 B |
1371 | }; |
| 1372 | ||
| 1373 | sata: sata@4a141100 { | |
| 1374 | compatible = "snps,dwc-ahci"; | |
| 1375 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | |
| a46631c4 | 1376 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| 7be80569 B |
1377 | phys = <&sata_phy>; |
| 1378 | phy-names = "sata-phy"; | |
| 1379 | clocks = <&sata_ref_clk>; | |
| 1380 | ti,hwmods = "sata"; | |
| 1381 | }; | |
| fbf3e552 | 1382 | |
| 00edd317 | 1383 | rtc: rtc@48838000 { |
| bc078316 LV |
1384 | compatible = "ti,am3352-rtc"; |
| 1385 | reg = <0x48838000 0x100>; | |
| 1386 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, | |
| 1387 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; | |
| 1388 | ti,hwmods = "rtcss"; | |
| 1389 | clocks = <&sys_32k_ck>; | |
| 1390 | }; | |
| 1391 | ||
| fbf3e552 RQ |
1392 | /* OCP2SCP1 */ |
| 1393 | ocp2scp@4a080000 { | |
| 1394 | compatible = "ti,omap-ocp2scp"; | |
| 1395 | #address-cells = <1>; | |
| 1396 | #size-cells = <1>; | |
| 1397 | ranges; | |
| 1398 | reg = <0x4a080000 0x20>; | |
| 1399 | ti,hwmods = "ocp2scp1"; | |
| 1400 | ||
| 1401 | usb2_phy1: phy@4a084000 { | |
| 291f1af5 | 1402 | compatible = "ti,dra7x-usb2", "ti,omap-usb2"; |
| fbf3e552 | 1403 | reg = <0x4a084000 0x400>; |
| 2338c76a | 1404 | syscon-phy-power = <&scm_conf 0x300>; |
| fbf3e552 RQ |
1405 | clocks = <&usb_phy1_always_on_clk32k>, |
| 1406 | <&usb_otg_ss1_refclk960m>; | |
| 1407 | clock-names = "wkupclk", | |
| 1408 | "refclk"; | |
| 1409 | #phy-cells = <0>; | |
| 1410 | }; | |
| 1411 | ||
| 1412 | usb2_phy2: phy@4a085000 { | |
| 4b4f52ed KVA |
1413 | compatible = "ti,dra7x-usb2-phy2", |
| 1414 | "ti,omap-usb2"; | |
| fbf3e552 | 1415 | reg = <0x4a085000 0x400>; |
| 2338c76a | 1416 | syscon-phy-power = <&scm_conf 0xe74>; |
| fbf3e552 RQ |
1417 | clocks = <&usb_phy2_always_on_clk32k>, |
| 1418 | <&usb_otg_ss2_refclk960m>; | |
| 1419 | clock-names = "wkupclk", | |
| 1420 | "refclk"; | |
| 1421 | #phy-cells = <0>; | |
| 1422 | }; | |
| 1423 | ||
| 1424 | usb3_phy1: phy@4a084400 { | |
| 1425 | compatible = "ti,omap-usb3"; | |
| 1426 | reg = <0x4a084400 0x80>, | |
| 1427 | <0x4a084800 0x64>, | |
| 1428 | <0x4a084c00 0x40>; | |
| 1429 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
| 2338c76a | 1430 | syscon-phy-power = <&scm_conf 0x370>; |
| fbf3e552 RQ |
1431 | clocks = <&usb_phy3_always_on_clk32k>, |
| 1432 | <&sys_clkin1>, | |
| 1433 | <&usb_otg_ss1_refclk960m>; | |
| 1434 | clock-names = "wkupclk", | |
| 1435 | "sysclk", | |
| 1436 | "refclk"; | |
| 1437 | #phy-cells = <0>; | |
| 1438 | }; | |
| 1439 | }; | |
| 1440 | ||
| 4f6dec70 | 1441 | omap_dwc3_1: omap_dwc3_1@48880000 { |
| fbf3e552 RQ |
1442 | compatible = "ti,dwc3"; |
| 1443 | ti,hwmods = "usb_otg_ss1"; | |
| 1444 | reg = <0x48880000 0x10000>; | |
| a46631c4 | 1445 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| fbf3e552 RQ |
1446 | #address-cells = <1>; |
| 1447 | #size-cells = <1>; | |
| 1448 | utmi-mode = <2>; | |
| 1449 | ranges; | |
| 1450 | usb1: usb@48890000 { | |
| 1451 | compatible = "snps,dwc3"; | |
| 1452 | reg = <0x48890000 0x17000>; | |
| 964927f3 RQ |
1453 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, |
| 1454 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, | |
| 1455 | <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
| 1456 | interrupt-names = "peripheral", | |
| 1457 | "host", | |
| 1458 | "otg"; | |
| fbf3e552 RQ |
1459 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 1460 | phy-names = "usb2-phy", "usb3-phy"; | |
| fbf3e552 RQ |
1461 | maximum-speed = "super-speed"; |
| 1462 | dr_mode = "otg"; | |
| 8c606735 FB |
1463 | snps,dis_u3_susphy_quirk; |
| 1464 | snps,dis_u2_susphy_quirk; | |
| fbf3e552 RQ |
1465 | }; |
| 1466 | }; | |
| 1467 | ||
| 4f6dec70 | 1468 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
| fbf3e552 RQ |
1469 | compatible = "ti,dwc3"; |
| 1470 | ti,hwmods = "usb_otg_ss2"; | |
| 1471 | reg = <0x488c0000 0x10000>; | |
| a46631c4 | 1472 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| fbf3e552 RQ |
1473 | #address-cells = <1>; |
| 1474 | #size-cells = <1>; | |
| 1475 | utmi-mode = <2>; | |
| 1476 | ranges; | |
| 1477 | usb2: usb@488d0000 { | |
| 1478 | compatible = "snps,dwc3"; | |
| 1479 | reg = <0x488d0000 0x17000>; | |
| 964927f3 RQ |
1480 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| 1481 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
| 1482 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 1483 | interrupt-names = "peripheral", | |
| 1484 | "host", | |
| 1485 | "otg"; | |
| fbf3e552 RQ |
1486 | phys = <&usb2_phy2>; |
| 1487 | phy-names = "usb2-phy"; | |
| fbf3e552 RQ |
1488 | maximum-speed = "high-speed"; |
| 1489 | dr_mode = "otg"; | |
| 8c606735 FB |
1490 | snps,dis_u3_susphy_quirk; |
| 1491 | snps,dis_u2_susphy_quirk; | |
| fbf3e552 RQ |
1492 | }; |
| 1493 | }; | |
| 1494 | ||
| 1495 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ | |
| 4f6dec70 | 1496 | omap_dwc3_3: omap_dwc3_3@48900000 { |
| fbf3e552 RQ |
1497 | compatible = "ti,dwc3"; |
| 1498 | ti,hwmods = "usb_otg_ss3"; | |
| 1499 | reg = <0x48900000 0x10000>; | |
| a46631c4 | 1500 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
| fbf3e552 RQ |
1501 | #address-cells = <1>; |
| 1502 | #size-cells = <1>; | |
| 1503 | utmi-mode = <2>; | |
| 1504 | ranges; | |
| 1505 | status = "disabled"; | |
| 1506 | usb3: usb@48910000 { | |
| 1507 | compatible = "snps,dwc3"; | |
| 1508 | reg = <0x48910000 0x17000>; | |
| 964927f3 RQ |
1509 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| 1510 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, | |
| 1511 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; | |
| 1512 | interrupt-names = "peripheral", | |
| 1513 | "host", | |
| 1514 | "otg"; | |
| fbf3e552 RQ |
1515 | maximum-speed = "high-speed"; |
| 1516 | dr_mode = "otg"; | |
| 8c606735 FB |
1517 | snps,dis_u3_susphy_quirk; |
| 1518 | snps,dis_u2_susphy_quirk; | |
| fbf3e552 RQ |
1519 | }; |
| 1520 | }; | |
| 1521 | ||
| ff66a3c8 MS |
1522 | elm: elm@48078000 { |
| 1523 | compatible = "ti,am3352-elm"; | |
| 1524 | reg = <0x48078000 0xfc0>; /* device IO registers */ | |
| a46631c4 | 1525 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| ff66a3c8 MS |
1526 | ti,hwmods = "elm"; |
| 1527 | status = "disabled"; | |
| 1528 | }; | |
| 1529 | ||
| 1530 | gpmc: gpmc@50000000 { | |
| 1531 | compatible = "ti,am3352-gpmc"; | |
| 1532 | ti,hwmods = "gpmc"; | |
| 1533 | reg = <0x50000000 0x37c>; /* device IO registers */ | |
| a46631c4 | 1534 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 10ce2404 FCJ |
1535 | dmas = <&edma_xbar 4 0>; |
| 1536 | dma-names = "rxtx"; | |
| ff66a3c8 MS |
1537 | gpmc,num-cs = <8>; |
| 1538 | gpmc,num-waitpins = <2>; | |
| 1539 | #address-cells = <2>; | |
| 1540 | #size-cells = <1>; | |
| 488f270d RQ |
1541 | interrupt-controller; |
| 1542 | #interrupt-cells = <2>; | |
| 845b1a26 RQ |
1543 | gpio-controller; |
| 1544 | #gpio-cells = <2>; | |
| ff66a3c8 MS |
1545 | status = "disabled"; |
| 1546 | }; | |
| 2ca0945f PU |
1547 | |
| 1548 | atl: atl@4843c000 { | |
| 1549 | compatible = "ti,dra7-atl"; | |
| 1550 | reg = <0x4843c000 0x3ff>; | |
| 1551 | ti,hwmods = "atl"; | |
| 1552 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, | |
| 1553 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; | |
| 1554 | clocks = <&atl_gfclk_mux>; | |
| 1555 | clock-names = "fck"; | |
| 1556 | status = "disabled"; | |
| 1557 | }; | |
| 412a9bbd | 1558 | |
| 296ea972 PU |
1559 | mcasp1: mcasp@48460000 { |
| 1560 | compatible = "ti,dra7-mcasp-audio"; | |
| 1561 | ti,hwmods = "mcasp1"; | |
| 1562 | reg = <0x48460000 0x2000>, | |
| 1563 | <0x45800000 0x1000>; | |
| 1564 | reg-names = "mpu","dat"; | |
| 1565 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
| 1566 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
| 1567 | interrupt-names = "tx", "rx"; | |
| 1568 | dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; | |
| 1569 | dma-names = "tx", "rx"; | |
| 1570 | clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, | |
| 1571 | <&mcasp1_ahclkr_mux>; | |
| 1572 | clock-names = "fck", "ahclkx", "ahclkr"; | |
| 1573 | status = "disabled"; | |
| 1574 | }; | |
| 1575 | ||
| 1576 | mcasp2: mcasp@48464000 { | |
| 1577 | compatible = "ti,dra7-mcasp-audio"; | |
| 1578 | ti,hwmods = "mcasp2"; | |
| 1579 | reg = <0x48464000 0x2000>, | |
| 1580 | <0x45c00000 0x1000>; | |
| 1581 | reg-names = "mpu","dat"; | |
| 1582 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
| 1583 | <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
| 1584 | interrupt-names = "tx", "rx"; | |
| 1585 | dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; | |
| 1586 | dma-names = "tx", "rx"; | |
| 1587 | clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, | |
| 1588 | <&mcasp2_ahclkr_mux>; | |
| 1589 | clock-names = "fck", "ahclkx", "ahclkr"; | |
| 1590 | status = "disabled"; | |
| 1591 | }; | |
| 1592 | ||
| 026d4d6d PU |
1593 | mcasp3: mcasp@48468000 { |
| 1594 | compatible = "ti,dra7-mcasp-audio"; | |
| 1595 | ti,hwmods = "mcasp3"; | |
| 0c92de2c MLC |
1596 | reg = <0x48468000 0x2000>, |
| 1597 | <0x46000000 0x1000>; | |
| 1598 | reg-names = "mpu","dat"; | |
| 026d4d6d PU |
1599 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
| 1600 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
| 1601 | interrupt-names = "tx", "rx"; | |
| 0c92de2c | 1602 | dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; |
| 026d4d6d | 1603 | dma-names = "tx", "rx"; |
| bf05c2c2 | 1604 | clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; |
| 296ea972 PU |
1605 | clock-names = "fck", "ahclkx"; |
| 1606 | status = "disabled"; | |
| 1607 | }; | |
| 1608 | ||
| 1609 | mcasp4: mcasp@4846c000 { | |
| 1610 | compatible = "ti,dra7-mcasp-audio"; | |
| 1611 | ti,hwmods = "mcasp4"; | |
| 1612 | reg = <0x4846c000 0x2000>, | |
| 1613 | <0x48436000 0x1000>; | |
| 1614 | reg-names = "mpu","dat"; | |
| 1615 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
| 1616 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
| 1617 | interrupt-names = "tx", "rx"; | |
| 1618 | dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; | |
| 1619 | dma-names = "tx", "rx"; | |
| 1620 | clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; | |
| 1621 | clock-names = "fck", "ahclkx"; | |
| 1622 | status = "disabled"; | |
| 1623 | }; | |
| 1624 | ||
| 1625 | mcasp5: mcasp@48470000 { | |
| 1626 | compatible = "ti,dra7-mcasp-audio"; | |
| 1627 | ti,hwmods = "mcasp5"; | |
| 1628 | reg = <0x48470000 0x2000>, | |
| 1629 | <0x4843a000 0x1000>; | |
| 1630 | reg-names = "mpu","dat"; | |
| 1631 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, | |
| 1632 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
| 1633 | interrupt-names = "tx", "rx"; | |
| 1634 | dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; | |
| 1635 | dma-names = "tx", "rx"; | |
| 1636 | clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; | |
| 1637 | clock-names = "fck", "ahclkx"; | |
| 1638 | status = "disabled"; | |
| 1639 | }; | |
| 1640 | ||
| 1641 | mcasp6: mcasp@48474000 { | |
| 1642 | compatible = "ti,dra7-mcasp-audio"; | |
| 1643 | ti,hwmods = "mcasp6"; | |
| 1644 | reg = <0x48474000 0x2000>, | |
| 1645 | <0x4844c000 0x1000>; | |
| 1646 | reg-names = "mpu","dat"; | |
| 1647 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
| 1648 | <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
| 1649 | interrupt-names = "tx", "rx"; | |
| 1650 | dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; | |
| 1651 | dma-names = "tx", "rx"; | |
| 1652 | clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; | |
| 1653 | clock-names = "fck", "ahclkx"; | |
| 1654 | status = "disabled"; | |
| 1655 | }; | |
| 1656 | ||
| 1657 | mcasp7: mcasp@48478000 { | |
| 1658 | compatible = "ti,dra7-mcasp-audio"; | |
| 1659 | ti,hwmods = "mcasp7"; | |
| 1660 | reg = <0x48478000 0x2000>, | |
| 1661 | <0x48450000 0x1000>; | |
| 1662 | reg-names = "mpu","dat"; | |
| 1663 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, | |
| 1664 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 1665 | interrupt-names = "tx", "rx"; | |
| 1666 | dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; | |
| 1667 | dma-names = "tx", "rx"; | |
| 1668 | clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; | |
| 1669 | clock-names = "fck", "ahclkx"; | |
| 1670 | status = "disabled"; | |
| 1671 | }; | |
| 1672 | ||
| 1673 | mcasp8: mcasp@4847c000 { | |
| 1674 | compatible = "ti,dra7-mcasp-audio"; | |
| 1675 | ti,hwmods = "mcasp8"; | |
| 1676 | reg = <0x4847c000 0x2000>, | |
| 1677 | <0x48454000 0x1000>; | |
| 1678 | reg-names = "mpu","dat"; | |
| 1679 | interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, | |
| 1680 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; | |
| 1681 | interrupt-names = "tx", "rx"; | |
| 1682 | dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; | |
| 1683 | dma-names = "tx", "rx"; | |
| 1684 | clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; | |
| bf05c2c2 | 1685 | clock-names = "fck", "ahclkx"; |
| 026d4d6d PU |
1686 | status = "disabled"; |
| 1687 | }; | |
| 1688 | ||
| 783d3186 | 1689 | crossbar_mpu: crossbar@4a002a48 { |
| a46631c4 S |
1690 | compatible = "ti,irq-crossbar"; |
| 1691 | reg = <0x4a002a48 0x130>; | |
| 783d3186 | 1692 | interrupt-controller; |
| 7136d457 | 1693 | interrupt-parent = <&wakeupgen>; |
| 783d3186 | 1694 | #interrupt-cells = <3>; |
| a46631c4 S |
1695 | ti,max-irqs = <160>; |
| 1696 | ti,max-crossbar-sources = <MAX_SOURCES>; | |
| 1697 | ti,reg-size = <2>; | |
| 1698 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; | |
| 1699 | ti,irqs-skip = <10 133 139 140>; | |
| 1700 | ti,irqs-safe-map = <0>; | |
| 1701 | }; | |
| ef9c5b69 | 1702 | |
| c263a5b8 | 1703 | mac: ethernet@48484000 { |
| e2095318 | 1704 | compatible = "ti,dra7-cpsw","ti,cpsw"; |
| ef9c5b69 | 1705 | ti,hwmods = "gmac"; |
| c097338e | 1706 | clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; |
| ef9c5b69 M |
1707 | clock-names = "fck", "cpts"; |
| 1708 | cpdma_channels = <8>; | |
| 1709 | ale_entries = <1024>; | |
| 1710 | bd_ram_size = <0x2000>; | |
| 1711 | no_bd_ram = <0>; | |
| ef9c5b69 M |
1712 | mac_control = <0x20>; |
| 1713 | slaves = <2>; | |
| 1714 | active_slave = <0>; | |
| c097338e | 1715 | cpts_clock_mult = <0x784CFE14>; |
| ef9c5b69 M |
1716 | cpts_clock_shift = <29>; |
| 1717 | reg = <0x48484000 0x1000 | |
| 1718 | 0x48485200 0x2E00>; | |
| 1719 | #address-cells = <1>; | |
| 1720 | #size-cells = <1>; | |
| 0f514e69 M |
1721 | |
| 1722 | /* | |
| 1723 | * Do not allow gating of cpsw clock as workaround | |
| 1724 | * for errata i877. Keeping internal clock disabled | |
| 1725 | * causes the device switching characteristics | |
| 1726 | * to degrade over time and eventually fail to meet | |
| 1727 | * the data manual delay time/skew specs. | |
| 1728 | */ | |
| 1729 | ti,no-idle; | |
| 1730 | ||
| ef9c5b69 M |
1731 | /* |
| 1732 | * rx_thresh_pend | |
| 1733 | * rx_pend | |
| 1734 | * tx_pend | |
| 1735 | * misc_pend | |
| 1736 | */ | |
| 1737 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
| 1738 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
| 1739 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
| 1740 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; | |
| 1741 | ranges; | |
| a084e13e | 1742 | syscon = <&scm_conf>; |
| ef9c5b69 M |
1743 | status = "disabled"; |
| 1744 | ||
| 1745 | davinci_mdio: mdio@48485000 { | |
| 9efd1a6f | 1746 | compatible = "ti,cpsw-mdio","ti,davinci_mdio"; |
| ef9c5b69 M |
1747 | #address-cells = <1>; |
| 1748 | #size-cells = <0>; | |
| 1749 | ti,hwmods = "davinci_mdio"; | |
| 1750 | bus_freq = <1000000>; | |
| 1751 | reg = <0x48485000 0x100>; | |
| 1752 | }; | |
| 1753 | ||
| 1754 | cpsw_emac0: slave@48480200 { | |
| 1755 | /* Filled in by U-Boot */ | |
| 1756 | mac-address = [ 00 00 00 00 00 00 ]; | |
| 1757 | }; | |
| 1758 | ||
| 1759 | cpsw_emac1: slave@48480300 { | |
| 1760 | /* Filled in by U-Boot */ | |
| 1761 | mac-address = [ 00 00 00 00 00 00 ]; | |
| 1762 | }; | |
| 1763 | ||
| 1764 | phy_sel: cpsw-phy-sel@4a002554 { | |
| 1765 | compatible = "ti,dra7xx-cpsw-phy-sel"; | |
| 1766 | reg= <0x4a002554 0x4>; | |
| 1767 | reg-names = "gmii-sel"; | |
| 1768 | }; | |
| 1769 | }; | |
| 1770 | ||
| 9ec49b9f RQ |
1771 | dcan1: can@481cc000 { |
| 1772 | compatible = "ti,dra7-d_can"; | |
| 1773 | ti,hwmods = "dcan1"; | |
| 1774 | reg = <0x4ae3c000 0x2000>; | |
| d919501f | 1775 | syscon-raminit = <&scm_conf 0x558 0>; |
| 9ec49b9f RQ |
1776 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| 1777 | clocks = <&dcan1_sys_clk_mux>; | |
| 1778 | status = "disabled"; | |
| 1779 | }; | |
| 1780 | ||
| 1781 | dcan2: can@481d0000 { | |
| 1782 | compatible = "ti,dra7-d_can"; | |
| 1783 | ti,hwmods = "dcan2"; | |
| 1784 | reg = <0x48480000 0x2000>; | |
| d919501f | 1785 | syscon-raminit = <&scm_conf 0x558 1>; |
| 9ec49b9f RQ |
1786 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| 1787 | clocks = <&sys_clkin1>; | |
| 1788 | status = "disabled"; | |
| 1789 | }; | |
| 95c1cd13 TV |
1790 | |
| 1791 | dss: dss@58000000 { | |
| 1792 | compatible = "ti,dra7-dss"; | |
| 1793 | /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ | |
| 1794 | /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ | |
| 1795 | status = "disabled"; | |
| 1796 | ti,hwmods = "dss_core"; | |
| 1797 | /* CTRL_CORE_DSS_PLL_CONTROL */ | |
| 1798 | syscon-pll-ctrl = <&scm_conf 0x538>; | |
| 1799 | #address-cells = <1>; | |
| 1800 | #size-cells = <1>; | |
| 1801 | ranges; | |
| 1802 | ||
| 1803 | dispc@58001000 { | |
| 1804 | compatible = "ti,dra7-dispc"; | |
| 1805 | reg = <0x58001000 0x1000>; | |
| 1806 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 1807 | ti,hwmods = "dss_dispc"; | |
| 1808 | clocks = <&dss_dss_clk>; | |
| 1809 | clock-names = "fck"; | |
| 1810 | /* CTRL_CORE_SMA_SW_1 */ | |
| 1811 | syscon-pol = <&scm_conf 0x534>; | |
| 1812 | }; | |
| 1813 | ||
| 1814 | hdmi: encoder@58060000 { | |
| 1815 | compatible = "ti,dra7-hdmi"; | |
| 1816 | reg = <0x58040000 0x200>, | |
| 1817 | <0x58040200 0x80>, | |
| 1818 | <0x58040300 0x80>, | |
| 1819 | <0x58060000 0x19000>; | |
| 1820 | reg-names = "wp", "pll", "phy", "core"; | |
| 1821 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 1822 | status = "disabled"; | |
| 1823 | ti,hwmods = "dss_hdmi"; | |
| 1824 | clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; | |
| 1825 | clock-names = "fck", "sys_clk"; | |
| 1826 | }; | |
| 1827 | }; | |
| 34370142 V |
1828 | |
| 1829 | epwmss0: epwmss@4843e000 { | |
| 1830 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
| 1831 | reg = <0x4843e000 0x30>; | |
| 1832 | ti,hwmods = "epwmss0"; | |
| 1833 | #address-cells = <1>; | |
| 1834 | #size-cells = <1>; | |
| 1835 | status = "disabled"; | |
| 1836 | ranges; | |
| 1837 | ||
| 1838 | ehrpwm0: pwm@4843e200 { | |
| 1839 | compatible = "ti,dra746-ehrpwm", | |
| 1840 | "ti,am3352-ehrpwm"; | |
| 1841 | #pwm-cells = <3>; | |
| 1842 | reg = <0x4843e200 0x80>; | |
| 1843 | clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; | |
| 1844 | clock-names = "tbclk", "fck"; | |
| 1845 | status = "disabled"; | |
| 1846 | }; | |
| 1847 | ||
| 1848 | ecap0: ecap@4843e100 { | |
| 1849 | compatible = "ti,dra746-ecap", | |
| 1850 | "ti,am3352-ecap"; | |
| 1851 | #pwm-cells = <3>; | |
| 1852 | reg = <0x4843e100 0x80>; | |
| 1853 | clocks = <&l4_root_clk_div>; | |
| 1854 | clock-names = "fck"; | |
| 1855 | status = "disabled"; | |
| 1856 | }; | |
| 1857 | }; | |
| 1858 | ||
| 1859 | epwmss1: epwmss@48440000 { | |
| 1860 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
| 1861 | reg = <0x48440000 0x30>; | |
| 1862 | ti,hwmods = "epwmss1"; | |
| 1863 | #address-cells = <1>; | |
| 1864 | #size-cells = <1>; | |
| 1865 | status = "disabled"; | |
| 1866 | ranges; | |
| 1867 | ||
| 1868 | ehrpwm1: pwm@48440200 { | |
| 1869 | compatible = "ti,dra746-ehrpwm", | |
| 1870 | "ti,am3352-ehrpwm"; | |
| 1871 | #pwm-cells = <3>; | |
| 1872 | reg = <0x48440200 0x80>; | |
| 1873 | clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; | |
| 1874 | clock-names = "tbclk", "fck"; | |
| 1875 | status = "disabled"; | |
| 1876 | }; | |
| 1877 | ||
| 1878 | ecap1: ecap@48440100 { | |
| 1879 | compatible = "ti,dra746-ecap", | |
| 1880 | "ti,am3352-ecap"; | |
| 1881 | #pwm-cells = <3>; | |
| 1882 | reg = <0x48440100 0x80>; | |
| 1883 | clocks = <&l4_root_clk_div>; | |
| 1884 | clock-names = "fck"; | |
| 1885 | status = "disabled"; | |
| 1886 | }; | |
| 1887 | }; | |
| 1888 | ||
| 1889 | epwmss2: epwmss@48442000 { | |
| 1890 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
| 1891 | reg = <0x48442000 0x30>; | |
| 1892 | ti,hwmods = "epwmss2"; | |
| 1893 | #address-cells = <1>; | |
| 1894 | #size-cells = <1>; | |
| 1895 | status = "disabled"; | |
| 1896 | ranges; | |
| 1897 | ||
| 1898 | ehrpwm2: pwm@48442200 { | |
| 1899 | compatible = "ti,dra746-ehrpwm", | |
| 1900 | "ti,am3352-ehrpwm"; | |
| 1901 | #pwm-cells = <3>; | |
| 1902 | reg = <0x48442200 0x80>; | |
| 1903 | clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; | |
| 1904 | clock-names = "tbclk", "fck"; | |
| 1905 | status = "disabled"; | |
| 1906 | }; | |
| 1907 | ||
| 1908 | ecap2: ecap@48442100 { | |
| 1909 | compatible = "ti,dra746-ecap", | |
| 1910 | "ti,am3352-ecap"; | |
| 1911 | #pwm-cells = <3>; | |
| 1912 | reg = <0x48442100 0x80>; | |
| 1913 | clocks = <&l4_root_clk_div>; | |
| 1914 | clock-names = "fck"; | |
| 1915 | status = "disabled"; | |
| 1916 | }; | |
| 1917 | }; | |
| bac9d0b8 | 1918 | |
| e7fd15c1 JF |
1919 | aes1: aes@4b500000 { |
| 1920 | compatible = "ti,omap4-aes"; | |
| 1921 | ti,hwmods = "aes1"; | |
| 1922 | reg = <0x4b500000 0xa0>; | |
| 1923 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
| 1924 | dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; | |
| 1925 | dma-names = "tx", "rx"; | |
| 1926 | clocks = <&l3_iclk_div>; | |
| 1927 | clock-names = "fck"; | |
| 1928 | }; | |
| 1929 | ||
| 1930 | aes2: aes@4b700000 { | |
| 1931 | compatible = "ti,omap4-aes"; | |
| 1932 | ti,hwmods = "aes2"; | |
| 1933 | reg = <0x4b700000 0xa0>; | |
| 1934 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
| 1935 | dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; | |
| 1936 | dma-names = "tx", "rx"; | |
| 1937 | clocks = <&l3_iclk_div>; | |
| 1938 | clock-names = "fck"; | |
| 1939 | }; | |
| 1940 | ||
| bac9d0b8 JF |
1941 | des: des@480a5000 { |
| 1942 | compatible = "ti,omap4-des"; | |
| 1943 | ti,hwmods = "des"; | |
| 1944 | reg = <0x480a5000 0xa0>; | |
| 1945 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 1946 | dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; | |
| 1947 | dma-names = "tx", "rx"; | |
| 1948 | clocks = <&l3_iclk_div>; | |
| 1949 | clock-names = "fck"; | |
| 1950 | }; | |
| da34609d LV |
1951 | |
| 1952 | sham: sham@53100000 { | |
| 1953 | compatible = "ti,omap5-sham"; | |
| 1954 | ti,hwmods = "sham"; | |
| 1955 | reg = <0x4b101000 0x300>; | |
| 1956 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| 1957 | dmas = <&edma_xbar 119 0>; | |
| 1958 | dma-names = "rx"; | |
| 1959 | clocks = <&l3_iclk_div>; | |
| 1960 | clock-names = "fck"; | |
| 1961 | }; | |
| 610e9c4a LV |
1962 | |
| 1963 | rng: rng@48090000 { | |
| 1964 | compatible = "ti,omap4-rng"; | |
| 1965 | ti,hwmods = "rng"; | |
| 1966 | reg = <0x48090000 0x2000>; | |
| 1967 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
| 1968 | clocks = <&l3_iclk_div>; | |
| 1969 | clock-names = "fck"; | |
| 1970 | }; | |
| 6e58b8f1 | 1971 | }; |
| f7397edf K |
1972 | |
| 1973 | thermal_zones: thermal-zones { | |
| 1974 | #include "omap4-cpu-thermal.dtsi" | |
| 1975 | #include "omap5-gpu-thermal.dtsi" | |
| 1976 | #include "omap5-core-thermal.dtsi" | |
| 667f2599 K |
1977 | #include "dra7-dspeve-thermal.dtsi" |
| 1978 | #include "dra7-iva-thermal.dtsi" | |
| f7397edf K |
1979 | }; |
| 1980 | ||
| 1981 | }; | |
| 1982 | ||
| 1983 | &cpu_thermal { | |
| 1984 | polling-delay = <500>; /* milliseconds */ | |
| 6e58b8f1 | 1985 | }; |
| ee6c7507 TK |
1986 | |
| 1987 | /include/ "dra7xx-clocks.dtsi" |