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ARM: dts: dra72-evm-common: Add wilink8 wlan support
[linux-2.6-block.git] / arch / arm / boot / dts / dra7-evm.dts
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
38b248db 10#include "dra74x.dtsi"
895bd4b3 11#include "dra7-evm-common.dtsi"
8d55881c 12#include "dra74x-mmc-iodelay.dtsi"
6e58b8f1
S		 13
14/ {
38b248db
RN		 15 model = "TI DRA742";
16 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
6e58b8f1 17
5c4d9f0d 18 memory@0 {
6e58b8f1 19 device_type = "memory";
dae320ec 20 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
6e58b8f1 21 };
6cf02dbb 22
b5ca62a5
RK		 23 evm_1v8_sw: fixedregulator-evm_1v8 {
24 compatible = "regulator-fixed";
25 regulator-name = "evm_1v8";
26 vin-supply = <&smps9_reg>;
27 regulator-min-microvolt = <1800000>;
28 regulator-max-microvolt = <1800000>;
29 };
30
4b935215
B		 31 evm_3v3_sd: fixedregulator-sd {
32 compatible = "regulator-fixed";
33 regulator-name = "evm_3v3_sd";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 enable-active-high;
37 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
38 };
39
27f39e5f 40 evm_3v3_sw: fixedregulator-evm_3v3_sw {
6cf02dbb 41 compatible = "regulator-fixed";
27f39e5f 42 regulator-name = "evm_3v3_sw";
8695add6 43 vin-supply = <&sysen1>;
6cf02dbb
B		 44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
c7cc9ba1 47
d6818223
PU		 48 aic_dvdd: fixedregulator-aic_dvdd {
49 /* TPS77018DBVT */
50 compatible = "regulator-fixed";
51 regulator-name = "aic_dvdd";
52 vin-supply = <&evm_3v3_sw>;
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <1800000>;
55 };
56
87517d26
RQ		 57 extcon_usb2: extcon_usb2 {
58 compatible = "linux,extcon-usb-gpio";
59 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
60 };
61
c7cc9ba1
LV		 62 vtt_fixed: fixedregulator-vtt {
63 compatible = "regulator-fixed";
64 regulator-name = "vtt_fixed";
65 regulator-min-microvolt = <1350000>;
66 regulator-max-microvolt = <1350000>;
67 regulator-always-on;
68 regulator-boot-on;
69 enable-active-high;
8695add6 70 vin-supply = <&sysen2>;
c7cc9ba1
LV		 71 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
72 };
a9347bfa 73
6e58b8f1
S		 74};
75
76&dra7_pmx_core {
b41502e0
RQ		 77 dcan1_pins_default: dcan1_pins_default {
78 pinctrl-single,pins = <
c78be3d8
JMC		 79 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
80 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
b41502e0
RQ		 81 >;
82 };
83
84 dcan1_pins_sleep: dcan1_pins_sleep {
85 pinctrl-single,pins = <
c78be3d8
JMC		 86 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
87 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
b41502e0
RQ		 88 >;
89 };
6e58b8f1
S		 90};
91
92&i2c1 {
93 status = "okay";
6e58b8f1 94 clock-frequency = <400000>;
c56a831c
K		 95
96 tps659038: tps659038@58 {
97 compatible = "ti,tps659038";
98 reg = <0x58>;
7c62de5f
K		 99 ti,palmas-override-powerhold;
100 ti,system-power-controller;
c56a831c
K		 101
102 tps659038_pmic {
103 compatible = "ti,tps659038-pmic";
104
105 regulators {
106 smps123_reg: smps123 {
107 /* VDD_MPU */
108 regulator-name = "smps123";
109 regulator-min-microvolt = < 850000>;
110 regulator-max-microvolt = <1250000>;
111 regulator-always-on;
112 regulator-boot-on;
113 };
114
115 smps45_reg: smps45 {
116 /* VDD_DSPEVE */
117 regulator-name = "smps45";
118 regulator-min-microvolt = < 850000>;
54d03c5d 119 regulator-max-microvolt = <1250000>;
395b23ca 120 regulator-always-on;
c56a831c
K		 121 regulator-boot-on;
122 };
123
124 smps6_reg: smps6 {
125 /* VDD_GPU - over VDD_SMPS6 */
126 regulator-name = "smps6";
127 regulator-min-microvolt = <850000>;
d114e854 128 regulator-max-microvolt = <1250000>;
395b23ca 129 regulator-always-on;
c56a831c
K		 130 regulator-boot-on;
131 };
132
133 smps7_reg: smps7 {
134 /* CORE_VDD */
135 regulator-name = "smps7";
136 regulator-min-microvolt = <850000>;
54d03c5d 137 regulator-max-microvolt = <1150000>;
c56a831c
K		 138 regulator-always-on;
139 regulator-boot-on;
140 };
141
142 smps8_reg: smps8 {
143 /* VDD_IVAHD */
144 regulator-name = "smps8";
145 regulator-min-microvolt = < 850000>;
146 regulator-max-microvolt = <1250000>;
395b23ca 147 regulator-always-on;
c56a831c
K		 148 regulator-boot-on;
149 };
150
151 smps9_reg: smps9 {
152 /* VDDS1V8 */
153 regulator-name = "smps9";
154 regulator-min-microvolt = <1800000>;
155 regulator-max-microvolt = <1800000>;
156 regulator-always-on;
157 regulator-boot-on;
158 };
159
160 ldo1_reg: ldo1 {
161 /* LDO1_OUT --> SDIO */
162 regulator-name = "ldo1";
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <3300000>;
9f04ceeb 165 regulator-always-on;
c56a831c
K		 166 regulator-boot-on;
167 };
168
169 ldo2_reg: ldo2 {
170 /* VDD_RTCIO */
171 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
172 regulator-name = "ldo2";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
395b23ca 175 regulator-always-on;
c56a831c
K		 176 regulator-boot-on;
177 };
178
179 ldo3_reg: ldo3 {
180 /* VDDA_1V8_PHY */
181 regulator-name = "ldo3";
182 regulator-min-microvolt = <1800000>;
183 regulator-max-microvolt = <1800000>;
e120fb45 184 regulator-always-on;
c56a831c
K		 185 regulator-boot-on;
186 };
187
188 ldo9_reg: ldo9 {
189 /* VDD_RTC */
190 regulator-name = "ldo9";
191 regulator-min-microvolt = <1050000>;
192 regulator-max-microvolt = <1050000>;
395b23ca 193 regulator-always-on;
c56a831c 194 regulator-boot-on;
fcf58958 195 regulator-allow-bypass;
c56a831c
K		 196 };
197
198 ldoln_reg: ldoln {
199 /* VDDA_1V8_PLL */
200 regulator-name = "ldoln";
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <1800000>;
203 regulator-always-on;
204 regulator-boot-on;
205 };
206
207 ldousb_reg: ldousb {
208 /* VDDA_3V_USB: VDDA_USBHS33 */
209 regulator-name = "ldousb";
210 regulator-min-microvolt = <3300000>;
211 regulator-max-microvolt = <3300000>;
212 regulator-boot-on;
213 };
8695add6
NM		 214
215 /* REGEN1 is unused */
216
217 regen2: regen2 {
218 /* Needed for PMIC internal resources */
219 regulator-name = "regen2";
220 regulator-boot-on;
221 regulator-always-on;
222 };
223
224 /* REGEN3 is unused */
225
226 sysen1: sysen1 {
227 /* PMIC_REGEN_3V3 */
228 regulator-name = "sysen1";
229 regulator-boot-on;
230 regulator-always-on;
231 };
232
233 sysen2: sysen2 {
234 /* PMIC_REGEN_DDR */
235 regulator-name = "sysen2";
236 regulator-boot-on;
237 regulator-always-on;
238 };
c56a831c
K		 239 };
240 };
241 };
87517d26 242
4fbdc6ab 243 pcf_lcd: gpio@20 {
86f196f8 244 compatible = "ti,pcf8575", "nxp,pcf8575";
4fbdc6ab
GS		 245 reg = <0x20>;
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-parent = <&gpio6>;
249 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 };
253
87517d26 254 pcf_gpio_21: gpio@21 {
86f196f8 255 compatible = "ti,pcf8575", "nxp,pcf8575";
87517d26
RQ		 256 reg = <0x21>;
257 lines-initial-states = <0x1408>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-parent = <&gpio6>;
261 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 };
265
a9347bfa
PU		 266 tlv320aic3106: tlv320aic3106@19 {
267 #sound-dai-cells = <0>;
268 compatible = "ti,tlv320aic3106";
269 reg = <0x19>;
270 adc-settle-ms = <40>;
271 ai3x-micbias-vg = <1>; /* 2.0V */
272 status = "okay";
273
274 /* Regulators */
275 AVDD-supply = <&evm_3v3_sw>;
276 IOVDD-supply = <&evm_3v3_sw>;
277 DRVDD-supply = <&evm_3v3_sw>;
278 DVDD-supply = <&aic_dvdd>;
279 };
6e58b8f1
S		 280};
281
282&i2c2 {
283 status = "okay";
6e58b8f1 284 clock-frequency = <400000>;
c5d294db
PU		 285
286 pcf_hdmi: gpio@26 {
86f196f8 287 compatible = "ti,pcf8575", "nxp,pcf8575";
c5d294db
PU		 288 reg = <0x26>;
289 gpio-controller;
290 #gpio-cells = <2>;
291 p1 {
292 /* vin6_sel_s0: high: VIN6, low: audio */
293 gpio-hog;
294 gpios = <1 GPIO_ACTIVE_HIGH>;
295 output-low;
296 line-name = "vin6_sel_s0";
297 };
298 };
6e58b8f1
S		 299};
300
bf1788df
B		 301&mmc1 {
302 status = "okay";
4b935215 303 vmmc-supply = <&evm_3v3_sd>;
45ea75eb 304 vqmmc-supply = <&ldo1_reg>;
bf1788df 305 bus-width = <4>;
f4eaf9e0
NM		 306 /*
307 * SDCD signal is not being used here - using the fact that GPIO mode
308 * is always hardwired.
309 */
267068d8 310 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
8d55881c
KVA		 311 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
312 pinctrl-0 = <&mmc1_pins_default>;
313 pinctrl-1 = <&mmc1_pins_hs>;
314 pinctrl-2 = <&mmc1_pins_sdr12>;
315 pinctrl-3 = <&mmc1_pins_sdr25>;
316 pinctrl-4 = <&mmc1_pins_sdr50>;
317 pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
318 pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
319 pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
320 pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
bf1788df 321};
6cf02dbb
B		 322
323&mmc2 {
324 status = "okay";
b5ca62a5 325 vmmc-supply = <&evm_1v8_sw>;
a9aa4e6e 326 vqmmc-supply = <&evm_1v8_sw>;
6cf02dbb 327 bus-width = <8>;
8d55881c
KVA		 328 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
329 pinctrl-0 = <&mmc2_pins_default>;
330 pinctrl-1 = <&mmc2_pins_hs>;
331 pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
332 pinctrl-3 = <&mmc2_pins_ddr_rev20>;
333 pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
334 pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
6cf02dbb 335};
22f1e7ef
K		 336
337&cpu0 {
fea79e0b 338 vdd-supply = <&smps123_reg>;
22f1e7ef 339};
dc2dd5b8 340
a7b0aa19
RQ		 341&omap_dwc3_2 {
342 extcon = <&extcon_usb2>;
343};
344
ff66a3c8
MS		 345&elm {
346 status = "okay";
347};
348
349&gpmc {
d888e9d7
SN		 350 /*
351 * For the existing IOdelay configuration via U-Boot we don't
352 * support NAND on dra7-evm. Keep it disabled. Enabling it
353 * requires a different configuration by U-Boot.
354 */
355 status = "disabled";
488f270d 356 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
ff66a3c8 357 nand@0,0 {
488f270d 358 compatible = "ti,omap2-nand";
ff66a3c8 359 reg = <0 0 4>; /* device IO registers */
488f270d
RQ		 360 interrupt-parent = <&gpmc>;
361 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
362 <1 IRQ_TYPE_NONE>; /* termcount */
a23fc155 363 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
a46394be 364 ti,nand-xfer-type = "prefetch-dma";
ff66a3c8
MS		 365 ti,nand-ecc-opt = "bch8";
366 ti,elm-id = <&elm>;
367 nand-bus-width = <16>;
368 gpmc,device-width = <2>;
369 gpmc,sync-clk-ps = <0>;
370 gpmc,cs-on-ns = <0>;
5990047c
RQ		 371 gpmc,cs-rd-off-ns = <80>;
372 gpmc,cs-wr-off-ns = <80>;
ff66a3c8 373 gpmc,adv-on-ns = <0>;
5990047c
RQ		 374 gpmc,adv-rd-off-ns = <60>;
375 gpmc,adv-wr-off-ns = <60>;
376 gpmc,we-on-ns = <10>;
377 gpmc,we-off-ns = <50>;
378 gpmc,oe-on-ns = <4>;
379 gpmc,oe-off-ns = <40>;
380 gpmc,access-ns = <40>;
381 gpmc,wr-access-ns = <80>;
382 gpmc,rd-cycle-ns = <80>;
383 gpmc,wr-cycle-ns = <80>;
ff66a3c8
MS		 384 gpmc,bus-turnaround-ns = <0>;
385 gpmc,cycle2cycle-delay-ns = <0>;
386 gpmc,clk-activation-ns = <0>;
ff66a3c8
MS		 387 gpmc,wr-data-mux-bus-ns = <0>;
388 /* MTD partition table */
389 /* All SPL-* partitions are sized to minimal length
390 * which can be independently programmable. For
391 * NAND flash this is equal to size of erase-block */
392 #address-cells = <1>;
393 #size-cells = <1>;
394 partition@0 {
395 label = "NAND.SPL";
396 reg = <0x00000000 0x000020000>;
397 };
398 partition@1 {
399 label = "NAND.SPL.backup1";
400 reg = <0x00020000 0x00020000>;
401 };
402 partition@2 {
403 label = "NAND.SPL.backup2";
404 reg = <0x00040000 0x00020000>;
405 };
406 partition@3 {
407 label = "NAND.SPL.backup3";
408 reg = <0x00060000 0x00020000>;
409 };
410 partition@4 {
411 label = "NAND.u-boot-spl-os";
412 reg = <0x00080000 0x00040000>;
413 };
414 partition@5 {
415 label = "NAND.u-boot";
416 reg = <0x000c0000 0x00100000>;
417 };
418 partition@6 {
419 label = "NAND.u-boot-env";
420 reg = <0x001c0000 0x00020000>;
421 };
422 partition@7 {
f0e9fab3 423 label = "NAND.u-boot-env.backup1";
ff66a3c8
MS		 424 reg = <0x001e0000 0x00020000>;
425 };
426 partition@8 {
427 label = "NAND.kernel";
428 reg = <0x00200000 0x00800000>;
429 };
430 partition@9 {
431 label = "NAND.file-system";
432 reg = <0x00a00000 0x0f600000>;
433 };
434 };
435};
ae28ea88
RQ		 436
437&usb2_phy1 {
438 phy-supply = <&ldousb_reg>;
439};
440
441&usb2_phy2 {
442 phy-supply = <&ldousb_reg>;
443};
c7cc9ba1
LV		 444
445&gpio7 {
446 ti,no-reset-on-init;
447 ti,no-idle-on-init;
448};
8d039290
M		 449
450&mac {
451 status = "okay";
8d039290
M		 452 dual_emac;
453};
454
455&cpsw_emac0 {
456 phy_id = <&davinci_mdio>, <2>;
457 phy-mode = "rgmii";
458 dual_emac_res_vlan = <1>;
459};
460
461&cpsw_emac1 {
462 phy_id = <&davinci_mdio>, <3>;
463 phy-mode = "rgmii";
464 dual_emac_res_vlan = <2>;
465};
466
b41502e0
RQ		 467&dcan1 {
468 status = "ok";
2acb5c30
RQ		 469 pinctrl-names = "default", "sleep", "active";
470 pinctrl-0 = <&dcan1_pins_sleep>;
b41502e0 471 pinctrl-1 = <&dcan1_pins_sleep>;
2acb5c30 472 pinctrl-2 = <&dcan1_pins_default>;
b41502e0 473};
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