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ARM: dts: am57xx-beagle-x15: mmc1: remove redundant pbias-supply property
[linux-2.6-block.git] / arch / arm / boot / dts / dra7-evm.dts
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
38b248db 10#include "dra74x.dtsi"
c7cc9ba1 11#include <dt-bindings/gpio/gpio.h>
6e58b8f1
S		 12
13/ {
38b248db
RN		 14 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
6e58b8f1
S		 16
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x60000000>; /* 1536 MB */
20 };
6cf02dbb 21
4b935215
B		 22 evm_3v3_sd: fixedregulator-sd {
23 compatible = "regulator-fixed";
24 regulator-name = "evm_3v3_sd";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 enable-active-high;
28 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
29 };
30
6cf02dbb
B		 31 mmc2_3v3: fixedregulator-mmc2 {
32 compatible = "regulator-fixed";
33 regulator-name = "mmc2_3v3";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 };
c7cc9ba1 37
87517d26
RQ		 38 extcon_usb1: extcon_usb1 {
39 compatible = "linux,extcon-usb-gpio";
40 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
41 };
42
43 extcon_usb2: extcon_usb2 {
44 compatible = "linux,extcon-usb-gpio";
45 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
46 };
47
c7cc9ba1
LV		 48 vtt_fixed: fixedregulator-vtt {
49 compatible = "regulator-fixed";
50 regulator-name = "vtt_fixed";
51 regulator-min-microvolt = <1350000>;
52 regulator-max-microvolt = <1350000>;
53 regulator-always-on;
54 regulator-boot-on;
55 enable-active-high;
56 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
57 };
6e58b8f1
S		 58};
59
60&dra7_pmx_core {
c7cc9ba1
LV		 61 pinctrl-names = "default";
62 pinctrl-0 = <&vtt_pin>;
63
64 vtt_pin: pinmux_vtt_pin {
65 pinctrl-single,pins = <
66 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
67 >;
68 };
69
6e58b8f1
S		 70 i2c1_pins: pinmux_i2c1_pins {
71 pinctrl-single,pins = <
72 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
73 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
74 >;
75 };
76
77 i2c2_pins: pinmux_i2c2_pins {
78 pinctrl-single,pins = <
79 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
80 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
81 >;
82 };
83
84 i2c3_pins: pinmux_i2c3_pins {
85 pinctrl-single,pins = <
544d63d0
RQ		 86 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
87 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
6e58b8f1
S		 88 >;
89 };
90
91 mcspi1_pins: pinmux_mcspi1_pins {
92 pinctrl-single,pins = <
68e4d9e5
NM		 93 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
94 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
95 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
96 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
68e4d9e5
NM		 97 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
98 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
6e58b8f1
S		 99 >;
100 };
101
102 mcspi2_pins: pinmux_mcspi2_pins {
103 pinctrl-single,pins = <
104 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
105 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
106 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
107 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
108 >;
109 };
110
111 uart1_pins: pinmux_uart1_pins {
112 pinctrl-single,pins = <
113 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
114 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
115 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
116 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
117 >;
118 };
119
120 uart2_pins: pinmux_uart2_pins {
121 pinctrl-single,pins = <
122 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
123 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
124 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
125 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
126 >;
127 };
128
129 uart3_pins: pinmux_uart3_pins {
130 pinctrl-single,pins = <
131 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
132 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
133 >;
134 };
dc2dd5b8
SP		 135
136 qspi1_pins: pinmux_qspi1_pins {
137 pinctrl-single,pins = <
138 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
139 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
140 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
141 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
142 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
143 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
144 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
145 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
146 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
147 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
148 >;
149 };
4b4437cb
RQ		 150
151 usb1_pins: pinmux_usb1_pins {
152 pinctrl-single,pins = <
153 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
154 >;
155 };
156
157 usb2_pins: pinmux_usb2_pins {
158 pinctrl-single,pins = <
159 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
160 >;
161 };
ff66a3c8
MS		 162
163 nand_flash_x16: nand_flash_x16 {
164 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
165 * So NAND flash requires following switch settings:
166 * SW5.9 (GPMC_WPN) = LOW
167 * SW5.1 (NAND_BOOTn) = HIGH */
168 pinctrl-single,pins = <
169 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
170 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
171 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
172 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
173 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
174 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
175 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
176 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
177 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
178 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
179 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
180 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
181 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
182 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
183 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
184 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
185 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
186 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
187 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
188 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
189 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
190 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
191 >;
192 };
8d039290
M		 193
194 cpsw_default: cpsw_default {
195 pinctrl-single,pins = <
196 /* Slave 1 */
197 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
198 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
199 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
200 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
201 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
202 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
203 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
204 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
205 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
206 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
207 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
208 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
209
210 /* Slave 2 */
211 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
212 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
213 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
214 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
215 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
216 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
217 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
218 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
219 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
220 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
221 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
222 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
223 >;
224
225 };
226
227 cpsw_sleep: cpsw_sleep {
228 pinctrl-single,pins = <
229 /* Slave 1 */
230 0x250 (MUX_MODE15)
231 0x254 (MUX_MODE15)
232 0x258 (MUX_MODE15)
233 0x25c (MUX_MODE15)
234 0x260 (MUX_MODE15)
235 0x264 (MUX_MODE15)
236 0x268 (MUX_MODE15)
237 0x26c (MUX_MODE15)
238 0x270 (MUX_MODE15)
239 0x274 (MUX_MODE15)
240 0x278 (MUX_MODE15)
241 0x27c (MUX_MODE15)
242
243 /* Slave 2 */
244 0x198 (MUX_MODE15)
245 0x19c (MUX_MODE15)
246 0x1a0 (MUX_MODE15)
247 0x1a4 (MUX_MODE15)
248 0x1a8 (MUX_MODE15)
249 0x1ac (MUX_MODE15)
250 0x1b0 (MUX_MODE15)
251 0x1b4 (MUX_MODE15)
252 0x1b8 (MUX_MODE15)
253 0x1bc (MUX_MODE15)
254 0x1c0 (MUX_MODE15)
255 0x1c4 (MUX_MODE15)
256 >;
257 };
258
259 davinci_mdio_default: davinci_mdio_default {
260 pinctrl-single,pins = <
261 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
262 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
263 >;
264 };
265
266 davinci_mdio_sleep: davinci_mdio_sleep {
267 pinctrl-single,pins = <
268 0x23c (MUX_MODE15)
269 0x240 (MUX_MODE15)
270 >;
271 };
272
b41502e0
RQ		 273 dcan1_pins_default: dcan1_pins_default {
274 pinctrl-single,pins = <
d80d581b
RQ		 275 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
276 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
b41502e0
RQ		 277 >;
278 };
279
280 dcan1_pins_sleep: dcan1_pins_sleep {
281 pinctrl-single,pins = <
d80d581b
RQ		 282 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
283 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
b41502e0
RQ		 284 >;
285 };
6e58b8f1
S		 286};
287
288&i2c1 {
289 status = "okay";
290 pinctrl-names = "default";
291 pinctrl-0 = <&i2c1_pins>;
292 clock-frequency = <400000>;
c56a831c
K		 293
294 tps659038: tps659038@58 {
295 compatible = "ti,tps659038";
296 reg = <0x58>;
297
298 tps659038_pmic {
299 compatible = "ti,tps659038-pmic";
300
301 regulators {
302 smps123_reg: smps123 {
303 /* VDD_MPU */
304 regulator-name = "smps123";
305 regulator-min-microvolt = < 850000>;
306 regulator-max-microvolt = <1250000>;
307 regulator-always-on;
308 regulator-boot-on;
309 };
310
311 smps45_reg: smps45 {
312 /* VDD_DSPEVE */
313 regulator-name = "smps45";
314 regulator-min-microvolt = < 850000>;
315 regulator-max-microvolt = <1150000>;
395b23ca 316 regulator-always-on;
c56a831c
K		 317 regulator-boot-on;
318 };
319
320 smps6_reg: smps6 {
321 /* VDD_GPU - over VDD_SMPS6 */
322 regulator-name = "smps6";
323 regulator-min-microvolt = <850000>;
d114e854 324 regulator-max-microvolt = <1250000>;
395b23ca 325 regulator-always-on;
c56a831c
K		 326 regulator-boot-on;
327 };
328
329 smps7_reg: smps7 {
330 /* CORE_VDD */
331 regulator-name = "smps7";
332 regulator-min-microvolt = <850000>;
70fcaf92 333 regulator-max-microvolt = <1060000>;
c56a831c
K		 334 regulator-always-on;
335 regulator-boot-on;
336 };
337
338 smps8_reg: smps8 {
339 /* VDD_IVAHD */
340 regulator-name = "smps8";
341 regulator-min-microvolt = < 850000>;
342 regulator-max-microvolt = <1250000>;
395b23ca 343 regulator-always-on;
c56a831c
K		 344 regulator-boot-on;
345 };
346
347 smps9_reg: smps9 {
348 /* VDDS1V8 */
349 regulator-name = "smps9";
350 regulator-min-microvolt = <1800000>;
351 regulator-max-microvolt = <1800000>;
352 regulator-always-on;
353 regulator-boot-on;
354 };
355
356 ldo1_reg: ldo1 {
357 /* LDO1_OUT --> SDIO */
358 regulator-name = "ldo1";
359 regulator-min-microvolt = <1800000>;
360 regulator-max-microvolt = <3300000>;
361 regulator-boot-on;
362 };
363
364 ldo2_reg: ldo2 {
365 /* VDD_RTCIO */
366 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
367 regulator-name = "ldo2";
368 regulator-min-microvolt = <3300000>;
369 regulator-max-microvolt = <3300000>;
395b23ca 370 regulator-always-on;
c56a831c
K		 371 regulator-boot-on;
372 };
373
374 ldo3_reg: ldo3 {
375 /* VDDA_1V8_PHY */
376 regulator-name = "ldo3";
377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <1800000>;
e120fb45 379 regulator-always-on;
c56a831c
K		 380 regulator-boot-on;
381 };
382
383 ldo9_reg: ldo9 {
384 /* VDD_RTC */
385 regulator-name = "ldo9";
386 regulator-min-microvolt = <1050000>;
387 regulator-max-microvolt = <1050000>;
395b23ca 388 regulator-always-on;
c56a831c
K		 389 regulator-boot-on;
390 };
391
392 ldoln_reg: ldoln {
393 /* VDDA_1V8_PLL */
394 regulator-name = "ldoln";
395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <1800000>;
397 regulator-always-on;
398 regulator-boot-on;
399 };
400
401 ldousb_reg: ldousb {
402 /* VDDA_3V_USB: VDDA_USBHS33 */
403 regulator-name = "ldousb";
404 regulator-min-microvolt = <3300000>;
405 regulator-max-microvolt = <3300000>;
406 regulator-boot-on;
407 };
408 };
409 };
410 };
87517d26
RQ		 411
412 pcf_gpio_21: gpio@21 {
413 compatible = "ti,pcf8575";
414 reg = <0x21>;
415 lines-initial-states = <0x1408>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-parent = <&gpio6>;
419 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
423
6e58b8f1
S		 424};
425
426&i2c2 {
427 status = "okay";
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c2_pins>;
430 clock-frequency = <400000>;
431};
432
433&i2c3 {
434 status = "okay";
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c3_pins>;
544d63d0 437 clock-frequency = <400000>;
6e58b8f1
S		 438};
439
440&mcspi1 {
441 status = "okay";
442 pinctrl-names = "default";
443 pinctrl-0 = <&mcspi1_pins>;
444};
445
446&mcspi2 {
447 status = "okay";
448 pinctrl-names = "default";
449 pinctrl-0 = <&mcspi2_pins>;
450};
451
452&uart1 {
453 status = "okay";
454 pinctrl-names = "default";
455 pinctrl-0 = <&uart1_pins>;
783d3186 456 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
66b04369 457 <&dra7_pmx_core 0x3e0>;
6e58b8f1
S		 458};
459
460&uart2 {
461 status = "okay";
462 pinctrl-names = "default";
463 pinctrl-0 = <&uart2_pins>;
464};
465
466&uart3 {
467 status = "okay";
468 pinctrl-names = "default";
469 pinctrl-0 = <&uart3_pins>;
470};
bf1788df
B		 471
472&mmc1 {
473 status = "okay";
4b935215
B		 474 vmmc-supply = <&evm_3v3_sd>;
475 vmmc_aux-supply = <&ldo1_reg>;
bf1788df 476 bus-width = <4>;
f4eaf9e0
NM		 477 /*
478 * SDCD signal is not being used here - using the fact that GPIO mode
479 * is always hardwired.
480 */
481 cd-gpios = <&gpio6 27 0>;
bf1788df 482};
6cf02dbb
B		 483
484&mmc2 {
485 status = "okay";
486 vmmc-supply = <&mmc2_3v3>;
487 bus-width = <8>;
488};
22f1e7ef
K		 489
490&cpu0 {
491 cpu0-supply = <&smps123_reg>;
492};
dc2dd5b8
SP		 493
494&qspi {
495 status = "okay";
496 pinctrl-names = "default";
497 pinctrl-0 = <&qspi1_pins>;
498
499 spi-max-frequency = <48000000>;
500 m25p80@0 {
501 compatible = "s25fl256s1";
502 spi-max-frequency = <48000000>;
503 reg = <0>;
504 spi-tx-bus-width = <1>;
505 spi-rx-bus-width = <4>;
506 spi-cpol;
507 spi-cpha;
508 #address-cells = <1>;
509 #size-cells = <1>;
510
511 /* MTD partition table.
512 * The ROM checks the first four physical blocks
513 * for a valid file to boot and the flash here is
514 * 64KiB block size.
515 */
516 partition@0 {
517 label = "QSPI.SPL";
518 reg = <0x00000000 0x000010000>;
519 };
520 partition@1 {
521 label = "QSPI.SPL.backup1";
522 reg = <0x00010000 0x00010000>;
523 };
524 partition@2 {
525 label = "QSPI.SPL.backup2";
526 reg = <0x00020000 0x00010000>;
527 };
528 partition@3 {
529 label = "QSPI.SPL.backup3";
530 reg = <0x00030000 0x00010000>;
531 };
532 partition@4 {
533 label = "QSPI.u-boot";
534 reg = <0x00040000 0x00100000>;
535 };
536 partition@5 {
537 label = "QSPI.u-boot-spl-os";
69d2626f 538 reg = <0x00140000 0x00080000>;
dc2dd5b8
SP		 539 };
540 partition@6 {
541 label = "QSPI.u-boot-env";
69d2626f 542 reg = <0x001c0000 0x00010000>;
dc2dd5b8
SP		 543 };
544 partition@7 {
545 label = "QSPI.u-boot-env.backup1";
69d2626f 546 reg = <0x001d0000 0x0010000>;
dc2dd5b8
SP		 547 };
548 partition@8 {
549 label = "QSPI.kernel";
69d2626f 550 reg = <0x001e0000 0x0800000>;
dc2dd5b8
SP		 551 };
552 partition@9 {
553 label = "QSPI.file-system";
69d2626f 554 reg = <0x009e0000 0x01620000>;
dc2dd5b8
SP		 555 };
556 };
557};
4b4437cb 558
a7b0aa19
RQ		 559&omap_dwc3_1 {
560 extcon = <&extcon_usb1>;
561};
562
563&omap_dwc3_2 {
564 extcon = <&extcon_usb2>;
565};
566
4b4437cb
RQ		 567&usb1 {
568 dr_mode = "peripheral";
569 pinctrl-names = "default";
570 pinctrl-0 = <&usb1_pins>;
571};
572
573&usb2 {
574 dr_mode = "host";
575 pinctrl-names = "default";
576 pinctrl-0 = <&usb2_pins>;
577};
ff66a3c8
MS		 578
579&elm {
580 status = "okay";
581};
582
583&gpmc {
584 status = "okay";
585 pinctrl-names = "default";
586 pinctrl-0 = <&nand_flash_x16>;
587 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
588 nand@0,0 {
589 reg = <0 0 4>; /* device IO registers */
590 ti,nand-ecc-opt = "bch8";
591 ti,elm-id = <&elm>;
592 nand-bus-width = <16>;
593 gpmc,device-width = <2>;
594 gpmc,sync-clk-ps = <0>;
595 gpmc,cs-on-ns = <0>;
5990047c
RQ		 596 gpmc,cs-rd-off-ns = <80>;
597 gpmc,cs-wr-off-ns = <80>;
ff66a3c8 598 gpmc,adv-on-ns = <0>;
5990047c
RQ		 599 gpmc,adv-rd-off-ns = <60>;
600 gpmc,adv-wr-off-ns = <60>;
601 gpmc,we-on-ns = <10>;
602 gpmc,we-off-ns = <50>;
603 gpmc,oe-on-ns = <4>;
604 gpmc,oe-off-ns = <40>;
605 gpmc,access-ns = <40>;
606 gpmc,wr-access-ns = <80>;
607 gpmc,rd-cycle-ns = <80>;
608 gpmc,wr-cycle-ns = <80>;
ff66a3c8
MS		 609 gpmc,bus-turnaround-ns = <0>;
610 gpmc,cycle2cycle-delay-ns = <0>;
611 gpmc,clk-activation-ns = <0>;
612 gpmc,wait-monitoring-ns = <0>;
613 gpmc,wr-data-mux-bus-ns = <0>;
614 /* MTD partition table */
615 /* All SPL-* partitions are sized to minimal length
616 * which can be independently programmable. For
617 * NAND flash this is equal to size of erase-block */
618 #address-cells = <1>;
619 #size-cells = <1>;
620 partition@0 {
621 label = "NAND.SPL";
622 reg = <0x00000000 0x000020000>;
623 };
624 partition@1 {
625 label = "NAND.SPL.backup1";
626 reg = <0x00020000 0x00020000>;
627 };
628 partition@2 {
629 label = "NAND.SPL.backup2";
630 reg = <0x00040000 0x00020000>;
631 };
632 partition@3 {
633 label = "NAND.SPL.backup3";
634 reg = <0x00060000 0x00020000>;
635 };
636 partition@4 {
637 label = "NAND.u-boot-spl-os";
638 reg = <0x00080000 0x00040000>;
639 };
640 partition@5 {
641 label = "NAND.u-boot";
642 reg = <0x000c0000 0x00100000>;
643 };
644 partition@6 {
645 label = "NAND.u-boot-env";
646 reg = <0x001c0000 0x00020000>;
647 };
648 partition@7 {
f0e9fab3 649 label = "NAND.u-boot-env.backup1";
ff66a3c8
MS		 650 reg = <0x001e0000 0x00020000>;
651 };
652 partition@8 {
653 label = "NAND.kernel";
654 reg = <0x00200000 0x00800000>;
655 };
656 partition@9 {
657 label = "NAND.file-system";
658 reg = <0x00a00000 0x0f600000>;
659 };
660 };
661};
ae28ea88
RQ		 662
663&usb2_phy1 {
664 phy-supply = <&ldousb_reg>;
665};
666
667&usb2_phy2 {
668 phy-supply = <&ldousb_reg>;
669};
c7cc9ba1
LV		 670
671&gpio7 {
672 ti,no-reset-on-init;
673 ti,no-idle-on-init;
674};
8d039290
M		 675
676&mac {
677 status = "okay";
678 pinctrl-names = "default", "sleep";
679 pinctrl-0 = <&cpsw_default>;
680 pinctrl-1 = <&cpsw_sleep>;
681 dual_emac;
682};
683
684&cpsw_emac0 {
685 phy_id = <&davinci_mdio>, <2>;
686 phy-mode = "rgmii";
687 dual_emac_res_vlan = <1>;
688};
689
690&cpsw_emac1 {
691 phy_id = <&davinci_mdio>, <3>;
692 phy-mode = "rgmii";
693 dual_emac_res_vlan = <2>;
694};
695
696&davinci_mdio {
697 pinctrl-names = "default", "sleep";
698 pinctrl-0 = <&davinci_mdio_default>;
699 pinctrl-1 = <&davinci_mdio_sleep>;
700};
b41502e0
RQ		 701
702&dcan1 {
703 status = "ok";
704 pinctrl-names = "default", "sleep";
705 pinctrl-0 = <&dcan1_pins_default>;
706 pinctrl-1 = <&dcan1_pins_sleep>;
707};
Linux 6.x block layer and io_uring tree(s)