[linux-2.6-block.git] / arch / arm / boot / dts / da850.dtsi

/*
 * Copyright 2012 DENX Software Engineering GmbH
 * Heiko Schocher <hs@denx.de>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	arm {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		intc: interrupt-controller {
			compatible = "ti,cp-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <100>;
			reg = <0xfffee000 0x2000>;
		};
	};
	soc {
		compatible = "simple-bus";
		model = "da850";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x01c00000 0x400000>;
		interrupt-parent = <&intc>;

		pmx_core: pinmux@1c14120 {
			compatible = "pinctrl-single";
			reg = <0x14120 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,bit-per-mux;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0xf>;
			status = "disabled";

			nand_cs3_pins: pinmux_nand_pins {
				pinctrl-single,bits = <
					/* EMA_OE, EMA_WE */
					0x1c 0x00110000  0x00ff0000
					/* EMA_CS[4],EMA_CS[3]*/
					0x1c 0x00000110  0x00000ff0
					/*
					 * EMA_D[0], EMA_D[1], EMA_D[2],
					 * EMA_D[3], EMA_D[4], EMA_D[5],
					 * EMA_D[6], EMA_D[7]
					 */
					0x24 0x11111111  0xffffffff
					/* EMA_A[1], EMA_A[2] */
					0x30 0x01100000  0x0ff00000
				>;
			};
			i2c0_pins: pinmux_i2c0_pins {
				pinctrl-single,bits = <
					/* I2C0_SDA,I2C0_SCL */
					0x10 0x00002200 0x0000ff00
				>;
			};
			mmc0_pins: pinmux_mmc_pins {
				pinctrl-single,bits = <
					/* MMCSD0_DAT[3] MMCSD0_DAT[2]
					 * MMCSD0_DAT[1] MMCSD0_DAT[0]
					 * MMCSD0_CMD    MMCSD0_CLK
					 */
					0x28 0x00222222  0x00ffffff
				>;
			};
			ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
				pinctrl-single,bits = <
					/* EPWM0A */
					0xc 0x00000002 0x0000000f
				>;
			};
			ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
				pinctrl-single,bits = <
					/* EPWM0B */
					0xc 0x00000020 0x000000f0
				>;
			};
			ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
				pinctrl-single,bits = <
					/* EPWM1A */
					0x14 0x00000002 0x0000000f
				>;
			};
			ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
				pinctrl-single,bits = <
					/* EPWM1B */
					0x14 0x00000020 0x000000f0
				>;
			};
			ecap0_pins: pinmux_ecap0_pins {
				pinctrl-single,bits = <
					/* ECAP0_APWM0 */
					0x8 0x20000000 0xf0000000
				>;
			};
			ecap1_pins: pinmux_ecap1_pins {
				pinctrl-single,bits = <
					/* ECAP1_APWM1 */
					0x4 0x40000000 0xf0000000
				>;
			};
			ecap2_pins: pinmux_ecap2_pins {
				pinctrl-single,bits = <
					/* ECAP2_APWM2 */
					0x4 0x00000004 0x0000000f
				>;
			};
			spi1_pins: pinmux_spi_pins {
				pinctrl-single,bits = <
					/* SIMO, SOMI, CLK */
					0x14 0x00110100 0x00ff0f00
				>;
			};
			spi1_cs0_pin: pinmux_spi1_cs0 {
				pinctrl-single,bits = <
					/* CS0 */
					0x14 0x00000010 0x000000f0
				>;
			};
			mdio_pins: pinmux_mdio_pins {
				pinctrl-single,bits = <
					/* MDIO_CLK, MDIO_D */
					0x10 0x00000088 0x000000ff
				>;
			};
			mii_pins: pinmux_mii_pins {
				pinctrl-single,bits = <
					/*
					 * MII_TXEN, MII_TXCLK, MII_COL
					 * MII_TXD_3, MII_TXD_2, MII_TXD_1
					 * MII_TXD_0
					 */
					0x8 0x88888880 0xfffffff0
					/*
					 * MII_RXER, MII_CRS, MII_RXCLK
					 * MII_RXDV, MII_RXD_3, MII_RXD_2
					 * MII_RXD_1, MII_RXD_0
					 */
					0xc 0x88888888 0xffffffff
				>;
			};

		};
		serial0: serial@1c42000 {
			compatible = "ns16550a";
			reg = <0x42000 0x100>;
			reg-shift = <2>;
			interrupts = <25>;
			status = "disabled";
		};
		serial1: serial@1d0c000 {
			compatible = "ns16550a";
			reg = <0x10c000 0x100>;
			reg-shift = <2>;
			interrupts = <53>;
			status = "disabled";
		};
		serial2: serial@1d0d000 {
			compatible = "ns16550a";
			reg = <0x10d000 0x100>;
			reg-shift = <2>;
			interrupts = <61>;
			status = "disabled";
		};
		rtc0: rtc@1c23000 {
			compatible = "ti,da830-rtc";
			reg = <0x23000 0x1000>;
			interrupts = <19
				      19>;
			status = "disabled";
		};
		i2c0: i2c@1c22000 {
			compatible = "ti,davinci-i2c";
			reg = <0x22000 0x1000>;
			interrupts = <15>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		wdt: wdt@1c21000 {
			compatible = "ti,davinci-wdt";
			reg = <0x21000 0x1000>;
			status = "disabled";
		};
		mmc0: mmc@1c40000 {
			compatible = "ti,da830-mmc";
			reg = <0x40000 0x1000>;
			interrupts = <16>;
			status = "disabled";
		};
		ehrpwm0: ehrpwm@01f00000 {
			compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x300000 0x2000>;
			status = "disabled";
		};
		ehrpwm1: ehrpwm@01f02000 {
			compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x302000 0x2000>;
			status = "disabled";
		};
		ecap0: ecap@01f06000 {
			compatible = "ti,da850-ecap", "ti,am33xx-ecap";
			#pwm-cells = <3>;
			reg = <0x306000 0x80>;
			status = "disabled";
		};
		ecap1: ecap@01f07000 {
			compatible = "ti,da850-ecap", "ti,am33xx-ecap";
			#pwm-cells = <3>;
			reg = <0x307000 0x80>;
			status = "disabled";
		};
		ecap2: ecap@01f08000 {
			compatible = "ti,da850-ecap", "ti,am33xx-ecap";
			#pwm-cells = <3>;
			reg = <0x308000 0x80>;
			status = "disabled";
		};
		spi1: spi@1f0e000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "ti,da830-spi";
			reg = <0x30e000 0x1000>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <1>;
			interrupts = <56>;
			status = "disabled";
		};
		mdio: mdio@1e24000 {
			compatible = "ti,davinci_mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x224000 0x1000>;
		};
		eth0: ethernet@1e20000 {
			compatible = "ti,davinci-dm6467-emac";
			reg = <0x220000 0x4000>;
			ti,davinci-ctrl-reg-offset = <0x3000>;
			ti,davinci-ctrl-mod-reg-offset = <0x2000>;
			ti,davinci-ctrl-ram-offset = <0>;
			ti,davinci-ctrl-ram-size = <0x2000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <33
					34
					35
					36
					>;
		};
		gpio: gpio@1e26000 {
			compatible = "ti,dm6441-gpio";
			gpio-controller;
			reg = <0x226000 0x1000>;
			interrupts = <42 IRQ_TYPE_EDGE_BOTH
				43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
				45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
				47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
				49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
			ti,ngpio = <144>;
			ti,davinci-gpio-unbanked = <0>;
			status = "disabled";
		};
	};
	nand_cs3@62000000 {
		compatible = "ti,davinci-nand";
		reg = <0x62000000 0x807ff
		       0x68000000 0x8000>;
		ti,davinci-chipselect = <1>;
		ti,davinci-mask-ale = <0>;
		ti,davinci-mask-cle = <0>;
		ti,davinci-mask-chipsel = <0>;
		ti,davinci-ecc-mode = "hw";
		ti,davinci-ecc-bits = <4>;
		ti,davinci-nand-use-bbt;
		status = "disabled";
	};
};
Commit	Line	Data
33085b3e HS	1	/*
	2	* Copyright 2012 DENX Software Engineering GmbH
	3	* Heiko Schocher <hs@denx.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
a2bcd776	10	#include "skeleton.dtsi"
2e38b946	11	#include <dt-bindings/interrupt-controller/irq.h>
33085b3e HS	12
	13	/ {
	14	arm {
	15	#address-cells = <1>;
	16	#size-cells = <1>;
	17	ranges;
	18	intc: interrupt-controller {
	19	compatible = "ti,cp-intc";
	20	interrupt-controller;
	21	#interrupt-cells = <1>;
	22	ti,intc-size = <100>;
	23	reg = <0xfffee000 0x2000>;
	24	};
	25	};
	26	soc {
	27	compatible = "simple-bus";
	28	model = "da850";
	29	#address-cells = <1>;
	30	#size-cells = <1>;
	31	ranges = <0x0 0x01c00000 0x400000>;
c57ff58d	32	interrupt-parent = <&intc>;
33085b3e	33
1faaba3d KA	34	pmx_core: pinmux@1c14120 {
	35	compatible = "pinctrl-single";
	36	reg = <0x14120 0x50>;
	37	#address-cells = <1>;
	38	#size-cells = <0>;
	39	pinctrl-single,bit-per-mux;
	40	pinctrl-single,register-width = <32>;
055cb2a9	41	pinctrl-single,function-mask = <0xf>;
1faaba3d	42	status = "disabled";
99b8800c KA	43
	44	nand_cs3_pins: pinmux_nand_pins {
	45	pinctrl-single,bits = <
	46	/* EMA_OE, EMA_WE */
	47	0x1c 0x00110000 0x00ff0000
	48	/* EMA_CS[4],EMA_CS[3]*/
	49	0x1c 0x00000110 0x00000ff0
	50	/*
	51	* EMA_D[0], EMA_D[1], EMA_D[2],
	52	* EMA_D[3], EMA_D[4], EMA_D[5],
	53	* EMA_D[6], EMA_D[7]
	54	*/
	55	0x24 0x11111111 0xffffffff
	56	/* EMA_A[1], EMA_A[2] */
	57	0x30 0x01100000 0x0ff00000
	58	>;
	59	};
01729ccf VBM	60	i2c0_pins: pinmux_i2c0_pins {
	61	pinctrl-single,bits = <
	62	/* I2C0_SDA,I2C0_SCL */
	63	0x10 0x00002200 0x0000ff00
	64	>;
	65	};
88df4122 MP	66	mmc0_pins: pinmux_mmc_pins {
	67	pinctrl-single,bits = <
	68	/* MMCSD0_DAT[3] MMCSD0_DAT[2]
	69	* MMCSD0_DAT[1] MMCSD0_DAT[0]
	70	* MMCSD0_CMD MMCSD0_CLK
	71	*/
	72	0x28 0x00222222 0x00ffffff
	73	>;
	74	};
64fa59c4 PA	75	ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
	76	pinctrl-single,bits = <
	77	/* EPWM0A */
	78	0xc 0x00000002 0x0000000f
	79	>;
	80	};
	81	ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
	82	pinctrl-single,bits = <
	83	/* EPWM0B */
	84	0xc 0x00000020 0x000000f0
	85	>;
	86	};
	87	ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
	88	pinctrl-single,bits = <
	89	/* EPWM1A */
	90	0x14 0x00000002 0x0000000f
	91	>;
	92	};
	93	ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
	94	pinctrl-single,bits = <
	95	/* EPWM1B */
	96	0x14 0x00000020 0x000000f0
	97	>;
	98	};
	99	ecap0_pins: pinmux_ecap0_pins {
	100	pinctrl-single,bits = <
	101	/* ECAP0_APWM0 */
	102	0x8 0x20000000 0xf0000000
	103	>;
	104	};
	105	ecap1_pins: pinmux_ecap1_pins {
	106	pinctrl-single,bits = <
	107	/* ECAP1_APWM1 */
	108	0x4 0x40000000 0xf0000000
	109	>;
	110	};
	111	ecap2_pins: pinmux_ecap2_pins {
	112	pinctrl-single,bits = <
	113	/* ECAP2_APWM2 */
	114	0x4 0x00000004 0x0000000f
	115	>;
	116	};
c6347e48 MP	117	spi1_pins: pinmux_spi_pins {
	118	pinctrl-single,bits = <
	119	/* SIMO, SOMI, CLK */
	120	0x14 0x00110100 0x00ff0f00
	121	>;
	122	};
	123	spi1_cs0_pin: pinmux_spi1_cs0 {
	124	pinctrl-single,bits = <
	125	/* CS0 */
	126	0x14 0x00000010 0x000000f0
	127	>;
	128	};
609f4bcf LP	129	mdio_pins: pinmux_mdio_pins {
	130	pinctrl-single,bits = <
	131	/* MDIO_CLK, MDIO_D */
	132	0x10 0x00000088 0x000000ff
	133	>;
	134	};
dd7deaf2 LP	135	mii_pins: pinmux_mii_pins {
	136	pinctrl-single,bits = <
	137	/*
	138	* MII_TXEN, MII_TXCLK, MII_COL
	139	* MII_TXD_3, MII_TXD_2, MII_TXD_1
	140	* MII_TXD_0
	141	*/
	142	0x8 0x88888880 0xfffffff0
	143	/*
	144	* MII_RXER, MII_CRS, MII_RXCLK
	145	* MII_RXDV, MII_RXD_3, MII_RXD_2
	146	* MII_RXD_1, MII_RXD_0
	147	*/
	148	0xc 0x88888888 0xffffffff
	149	>;
	150	};
609f4bcf	151
1faaba3d	152	};
33085b3e HS	153	serial0: serial@1c42000 {
	154	compatible = "ns16550a";
	155	reg = <0x42000 0x100>;
33085b3e HS	156	reg-shift = <2>;
33085b3e HS	157	interrupts = <25>;
33085b3e HS	158	status = "disabled";
	159	};
	160	serial1: serial@1d0c000 {
	161	compatible = "ns16550a";
	162	reg = <0x10c000 0x100>;
33085b3e HS	163	reg-shift = <2>;
33085b3e HS	164	interrupts = <53>;
33085b3e HS	165	status = "disabled";
	166	};
	167	serial2: serial@1d0d000 {
	168	compatible = "ns16550a";
	169	reg = <0x10d000 0x100>;
33085b3e HS	170	reg-shift = <2>;
33085b3e HS	171	interrupts = <61>;
33085b3e HS	172	status = "disabled";
33085b3e HS	173	};
1661636d MK	174	rtc0: rtc@1c23000 {
	175	compatible = "ti,da830-rtc";
	176	reg = <0x23000 0x1000>;
	177	interrupts = <19
	178	19>;
	179	status = "disabled";
	180	};
01729ccf VBM	181	i2c0: i2c@1c22000 {
	182	compatible = "ti,davinci-i2c";
	183	reg = <0x22000 0x1000>;
	184	interrupts = <15>;
	185	#address-cells = <1>;
	186	#size-cells = <0>;
	187	status = "disabled";
	188	};
518f97db KA	189	wdt: wdt@1c21000 {
	190	compatible = "ti,davinci-wdt";
	191	reg = <0x21000 0x1000>;
	192	status = "disabled";
	193	};
88df4122 MP	194	mmc0: mmc@1c40000 {
	195	compatible = "ti,da830-mmc";
	196	reg = <0x40000 0x1000>;
	197	interrupts = <16>;
	198	status = "disabled";
	199	};
64fa59c4 PA	200	ehrpwm0: ehrpwm@01f00000 {
	201	compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
	202	#pwm-cells = <3>;
	203	reg = <0x300000 0x2000>;
	204	status = "disabled";
	205	};
	206	ehrpwm1: ehrpwm@01f02000 {
	207	compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
	208	#pwm-cells = <3>;
	209	reg = <0x302000 0x2000>;
	210	status = "disabled";
	211	};
	212	ecap0: ecap@01f06000 {
	213	compatible = "ti,da850-ecap", "ti,am33xx-ecap";
	214	#pwm-cells = <3>;
	215	reg = <0x306000 0x80>;
	216	status = "disabled";
	217	};
	218	ecap1: ecap@01f07000 {
	219	compatible = "ti,da850-ecap", "ti,am33xx-ecap";
	220	#pwm-cells = <3>;
	221	reg = <0x307000 0x80>;
	222	status = "disabled";
	223	};
	224	ecap2: ecap@01f08000 {
	225	compatible = "ti,da850-ecap", "ti,am33xx-ecap";
	226	#pwm-cells = <3>;
	227	reg = <0x308000 0x80>;
	228	status = "disabled";
	229	};
c6347e48 MP	230	spi1: spi@1f0e000 {
	231	#address-cells = <1>;
	232	#size-cells = <0>;
	233	compatible = "ti,da830-spi";
	234	reg = <0x30e000 0x1000>;
	235	num-cs = <4>;
	236	ti,davinci-spi-intr-line = <1>;
	237	interrupts = <56>;
	238	status = "disabled";
	239	};
609f4bcf LP	240	mdio: mdio@1e24000 {
	241	compatible = "ti,davinci_mdio";
	242	#address-cells = <1>;
	243	#size-cells = <0>;
	244	reg = <0x224000 0x1000>;
	245	};
dd7deaf2 LP	246	eth0: ethernet@1e20000 {
	247	compatible = "ti,davinci-dm6467-emac";
	248	reg = <0x220000 0x4000>;
	249	ti,davinci-ctrl-reg-offset = <0x3000>;
	250	ti,davinci-ctrl-mod-reg-offset = <0x2000>;
	251	ti,davinci-ctrl-ram-offset = <0>;
	252	ti,davinci-ctrl-ram-size = <0x2000>;
	253	local-mac-address = [ 00 00 00 00 00 00 ];
	254	interrupts = <33
	255	34
	256	35
	257	36
	258	>;
	259	};
2e38b946 KS	260	gpio: gpio@1e26000 {
	261	compatible = "ti,dm6441-gpio";
	262	gpio-controller;
	263	reg = <0x226000 0x1000>;
	264	interrupts = <42 IRQ_TYPE_EDGE_BOTH
	265	43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
	266	45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
	267	47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
	268	49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
	269	ti,ngpio = <144>;
	270	ti,davinci-gpio-unbanked = <0>;
	271	status = "disabled";
	272	};
33085b3e	273	};
99b8800c KA	274	nand_cs3@62000000 {
	275	compatible = "ti,davinci-nand";
	276	reg = <0x62000000 0x807ff
	277	0x68000000 0x8000>;
	278	ti,davinci-chipselect = <1>;
	279	ti,davinci-mask-ale = <0>;
	280	ti,davinci-mask-cle = <0>;
	281	ti,davinci-mask-chipsel = <0>;
	282	ti,davinci-ecc-mode = "hw";
	283	ti,davinci-ecc-bits = <4>;
	284	ti,davinci-nand-use-bbt;
	285	status = "disabled";
	286	};
33085b3e	287	};