[linux-2.6-block.git] / arch / arm / boot / dts / berlin2cd.dtsi

/*
 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500-mini (BG2CD) SoC";
	compatible = "marvell,berlin2cd", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		l2: l2-cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_TWD>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "marvell,berlin2cd-chip-ctrl";
			#clock-cells = <1>;
			#reset-cells = <2>;
			reg = <0xea0000 0x400>;
			clocks = <&refclk>;
			clock-names = "refclk";

			uart0_pmux: uart0-pmux {
				groups = "G6";
				function = "uart0";
			};
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
				};
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
				};
			};

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&refclk>;
				status = "disabled";
			};

			sysctrl: system-controller@d000 {
				compatible = "marvell,berlin2cd-system-ctrl";
				reg = <0xd000 0x100>;
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
a9092118 SH	1	/*
	2	* Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
	3	*
	4	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	5	*
	6	* based on GPL'ed 2.6 kernel sources
	7	* (c) Marvell International Ltd.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include "skeleton.dtsi"
556f4a33	15	#include <dt-bindings/clock/berlin2.h>
a9092118 SH	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
	17
	18	/ {
	19	model = "Marvell Armada 1500-mini (BG2CD) SoC";
	20	compatible = "marvell,berlin2cd", "marvell,berlin";
	21
	22	cpus {
	23	#address-cells = <1>;
	24	#size-cells = <0>;
	25
	26	cpu@0 {
	27	compatible = "arm,cortex-a9";
	28	device_type = "cpu";
	29	next-level-cache = <&l2>;
	30	reg = <0>;
	31	};
	32	};
	33
556f4a33 SH	34	refclk: oscillator {
	35	compatible = "fixed-clock";
	36	#clock-cells = <0>;
	37	clock-frequency = <25000000>;
a9092118 SH	38	};
	39
	40	soc {
	41	compatible = "simple-bus";
	42	#address-cells = <1>;
	43	#size-cells = <1>;
	44	interrupt-parent = <&gic>;
	45
	46	ranges = <0 0xf7000000 0x1000000>;
	47
	48	l2: l2-cache-controller@ac0000 {
	49	compatible = "arm,pl310-cache";
	50	reg = <0xac0000 0x1000>;
	51	cache-unified;
	52	cache-level = <2>;
	53	};
	54
	55	gic: interrupt-controller@ad1000 {
	56	compatible = "arm,cortex-a9-gic";
	57	reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
	58	interrupt-controller;
	59	#interrupt-cells = <3>;
	60	};
	61
	62	local-timer@ad0600 {
	63	compatible = "arm,cortex-a9-twd-timer";
	64	reg = <0xad0600 0x20>;
	65	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
556f4a33	66	clocks = <&chip CLKID_TWD>;
a9092118 SH	67	};
	68
	69	apb@e80000 {
	70	compatible = "simple-bus";
	71	#address-cells = <1>;
	72	#size-cells = <1>;
	73
	74	ranges = <0 0xe80000 0x10000>;
	75	interrupt-parent = <&aic>;
	76
c920a669 AT	77	gpio0: gpio@0400 {
	78	compatible = "snps,dw-apb-gpio";
	79	reg = <0x0400 0x400>;
	80	#address-cells = <1>;
	81	#size-cells = <0>;
	82
	83	porta: gpio-port@0 {
	84	compatible = "snps,dw-apb-gpio-port";
	85	gpio-controller;
	86	#gpio-cells = <2>;
	87	snps,nr-gpios = <8>;
	88	reg = <0>;
	89	interrupt-controller;
	90	#interrupt-cells = <2>;
	91	interrupts = <0>;
	92	};
	93	};
	94
	95	gpio1: gpio@0800 {
	96	compatible = "snps,dw-apb-gpio";
	97	reg = <0x0800 0x400>;
	98	#address-cells = <1>;
	99	#size-cells = <0>;
	100
	101	portb: gpio-port@1 {
	102	compatible = "snps,dw-apb-gpio-port";
	103	gpio-controller;
	104	#gpio-cells = <2>;
	105	snps,nr-gpios = <8>;
	106	reg = <0>;
	107	interrupt-controller;
	108	#interrupt-cells = <2>;
	109	interrupts = <1>;
	110	};
	111	};
	112
	113	gpio2: gpio@0c00 {
	114	compatible = "snps,dw-apb-gpio";
	115	reg = <0x0c00 0x400>;
	116	#address-cells = <1>;
	117	#size-cells = <0>;
	118
	119	portc: gpio-port@2 {
	120	compatible = "snps,dw-apb-gpio-port";
	121	gpio-controller;
	122	#gpio-cells = <2>;
	123	snps,nr-gpios = <8>;
	124	reg = <0>;
	125	interrupt-controller;
	126	#interrupt-cells = <2>;
	127	interrupts = <2>;
	128	};
	129	};
	130
	131	gpio3: gpio@1000 {
	132	compatible = "snps,dw-apb-gpio";
	133	reg = <0x1000 0x400>;
	134	#address-cells = <1>;
	135	#size-cells = <0>;
	136
	137	portd: gpio-port@3 {
	138	compatible = "snps,dw-apb-gpio-port";
	139	gpio-controller;
	140	#gpio-cells = <2>;
141	snps,nr-gpios = <8>;
142	reg = <0>;
143	interrupt-controller;
144	#interrupt-cells = <2>;
145	interrupts = <3>;
146	};
147	};
148
a9092118 SH	149	timer0: timer@2c00 {
	150	compatible = "snps,dw-apb-timer";
	151	reg = <0x2c00 0x14>;
	152	interrupts = <8>;
556f4a33	153	clocks = <&chip CLKID_CFG>;
a9092118 SH	154	clock-names = "timer";
	155	status = "okay";
	156	};
	157
	158	timer1: timer@2c14 {
	159	compatible = "snps,dw-apb-timer";
	160	reg = <0x2c14 0x14>;
	161	interrupts = <9>;
556f4a33	162	clocks = <&chip CLKID_CFG>;
a9092118 SH	163	clock-names = "timer";
	164	status = "okay";
	165	};
	166
	167	timer2: timer@2c28 {
	168	compatible = "snps,dw-apb-timer";
	169	reg = <0x2c28 0x14>;
	170	interrupts = <10>;
556f4a33	171	clocks = <&chip CLKID_CFG>;
a9092118 SH	172	clock-names = "timer";
	173	status = "disabled";
	174	};
	175
	176	timer3: timer@2c3c {
	177	compatible = "snps,dw-apb-timer";
	178	reg = <0x2c3c 0x14>;
	179	interrupts = <11>;
556f4a33	180	clocks = <&chip CLKID_CFG>;
a9092118 SH	181	clock-names = "timer";
	182	status = "disabled";
	183	};
	184
	185	timer4: timer@2c50 {
	186	compatible = "snps,dw-apb-timer";
	187	reg = <0x2c50 0x14>;
	188	interrupts = <12>;
556f4a33	189	clocks = <&chip CLKID_CFG>;
a9092118 SH	190	clock-names = "timer";
	191	status = "disabled";
	192	};
	193
	194	timer5: timer@2c64 {
	195	compatible = "snps,dw-apb-timer";
	196	reg = <0x2c64 0x14>;
	197	interrupts = <13>;
556f4a33	198	clocks = <&chip CLKID_CFG>;
a9092118 SH	199	clock-names = "timer";
	200	status = "disabled";
	201	};
	202
	203	timer6: timer@2c78 {
	204	compatible = "snps,dw-apb-timer";
	205	reg = <0x2c78 0x14>;
	206	interrupts = <14>;
556f4a33	207	clocks = <&chip CLKID_CFG>;
a9092118 SH	208	clock-names = "timer";
	209	status = "disabled";
	210	};
	211
	212	timer7: timer@2c8c {
	213	compatible = "snps,dw-apb-timer";
	214	reg = <0x2c8c 0x14>;
	215	interrupts = <15>;
556f4a33	216	clocks = <&chip CLKID_CFG>;
a9092118 SH	217	clock-names = "timer";
	218	status = "disabled";
	219	};
	220
	221	aic: interrupt-controller@3000 {
	222	compatible = "snps,dw-apb-ictl";
	223	reg = <0x3000 0xc00>;
	224	interrupt-controller;
	225	#interrupt-cells = <1>;
	226	interrupt-parent = <&gic>;
	227	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	228	};
	229	};
	230
556f4a33 SH	231	chip: chip-control@ea0000 {
	232	compatible = "marvell,berlin2cd-chip-ctrl";
	233	#clock-cells = <1>;
1e27a261	234	#reset-cells = <2>;
556f4a33 SH	235	reg = <0xea0000 0x400>;
	236	clocks = <&refclk>;
	237	clock-names = "refclk";
50cc24ff AT	238
	239	uart0_pmux: uart0-pmux {
	240	groups = "G6";
	241	function = "uart0";
	242	};
556f4a33 SH	243	};
556f4a33 SH	244
a9092118 SH	245	apb@fc0000 {
	246	compatible = "simple-bus";
	247	#address-cells = <1>;
	248	#size-cells = <1>;
	249
	250	ranges = <0 0xfc0000 0x10000>;
	251	interrupt-parent = <&sic>;
	252
c920a669 AT	253	sm_gpio1: gpio@5000 {
	254	compatible = "snps,dw-apb-gpio";
	255	reg = <0x5000 0x400>;
	256	#address-cells = <1>;
	257	#size-cells = <0>;
	258
	259	portf: gpio-port@5 {
	260	compatible = "snps,dw-apb-gpio-port";
	261	gpio-controller;
	262	#gpio-cells = <2>;
	263	snps,nr-gpios = <8>;
	264	reg = <0>;
	265	};
	266	};
	267
	268	sm_gpio0: gpio@c000 {
	269	compatible = "snps,dw-apb-gpio";
	270	reg = <0xc000 0x400>;
	271	#address-cells = <1>;
	272	#size-cells = <0>;
	273
	274	porte: gpio-port@4 {
	275	compatible = "snps,dw-apb-gpio-port";
	276	gpio-controller;
	277	#gpio-cells = <2>;
	278	snps,nr-gpios = <8>;
	279	reg = <0>;
	280	};
	281	};
	282
a9092118 SH	283	uart0: serial@9000 {
	284	compatible = "snps,dw-apb-uart";
	285	reg = <0x9000 0x100>;
	286	reg-shift = <2>;
	287	reg-io-width = <1>;
	288	interrupts = <8>;
556f4a33	289	clocks = <&refclk>;
50cc24ff AT	290	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	291	pinctrl-names = "default";
a9092118 SH	292	status = "disabled";
	293	};
	294
	295	uart1: serial@a000 {
	296	compatible = "snps,dw-apb-uart";
	297	reg = <0xa000 0x100>;
	298	reg-shift = <2>;
	299	reg-io-width = <1>;
	300	interrupts = <9>;
556f4a33	301	clocks = <&refclk>;
a9092118 SH	302	status = "disabled";
	303	};
	304
50cc24ff AT	305	sysctrl: system-controller@d000 {
	306	compatible = "marvell,berlin2cd-system-ctrl";
	307	reg = <0xd000 0x100>;
	308	};
	309
a9092118 SH	310	sic: interrupt-controller@e000 {
	311	compatible = "snps,dw-apb-ictl";
	312	reg = <0xe000 0x400>;
	313	interrupt-controller;
	314	#interrupt-cells = <1>;
	315	interrupt-parent = <&gic>;
	316	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	317	};
	318	};
	319	};
	320	};