[linux-2.6-block.git] / arch / arm / boot / dts / berlin2.dtsi

/*
 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is licensed under the terms of the GNU General Public
 *     License version 2. This program is licensed "as is" without any
 *     warranty of any kind, whether express or implied.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500 (BG2) SoC";
	compatible = "marvell,berlin2", "marvell,berlin";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu@0 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			operating-points = <
				/* kHz    uV */
				1200000 1200000
				1000000 1200000
				800000  1200000
				600000  1200000
			>;
		};

		cpu@1 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc@f7000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		sdhci0: sdhci@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: sdhci@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: sdhci@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
			clock-names = "io", "core";
			pinctrl-0 = <&emmc_pmux>;
			pinctrl-names = "default";
			status = "disabled";
		};

		l2: l2-cache-controller@ac0000 {
			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&chip_clk CLKID_TWD>;
		};

		eth1: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip_clk CLKID_GETH1>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy1>;
			status = "disabled";

			ethphy1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		cpu-ctrl@dd0000 {
			compatible = "marvell,berlin-cpu-ctrl";
			reg = <0xdd0000 0x10000>;
		};

		eth0: ethernet@e50000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xe50000 0x10000>;
			clocks = <&chip_clk CLKID_GETH0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		ahci: sata@e90000 {
			compatible = "marvell,berlin2-ahci", "generic-ahci";
			reg = <0xe90000 0x1000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy 0>;
				status = "disabled";
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy 1>;
				status = "disabled";
			};
		};

		sata_phy: phy@e900a0 {
			compatible = "marvell,berlin2-sata-phy";
			reg = <0xe900a0 0x200>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;
			#phy-cells = <1>;
			status = "disabled";

			sata-phy@0 {
				reg = <0>;
			};

			sata-phy@1 {
				reg = <1>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "simple-mfd", "syscon";
			reg = <0xea0000 0x400>;

			chip_clk: clock {
				compatible = "marvell,berlin2-clk";
				#clock-cells = <1>;
				clocks = <&refclk>;
				clock-names = "refclk";
			};

			soc_pinctrl: pin-controller {
				compatible = "marvell,berlin2-soc-pinctrl";

				emmc_pmux: emmc-pmux {
					groups = "G26";
					function = "emmc";
				};
			};

			chip_rst: reset {
				compatible = "marvell,berlin2-reset";
				#reset-cells = <2>;
			};
		};

		pwm: pwm@f20000 {
			compatible = "marvell,berlin-pwm";
			reg = <0xf20000 0x40>;
			clocks = <&chip_clk CLKID_CFG>;
			#pwm-cells = <3>;
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			wdt0: watchdog@1000 {
				compatible = "snps,dw-wdt";
				reg = <0x1000 0x100>;
				clocks = <&refclk>;
				interrupts = <0>;
			};

			wdt1: watchdog@2000 {
				compatible = "snps,dw-wdt";
				reg = <0x2000 0x100>;
				clocks = <&refclk>;
				interrupts = <1>;
			};

			wdt2: watchdog@3000 {
				compatible = "snps,dw-wdt";
				reg = <0x3000 0x100>;
				clocks = <&refclk>;
				interrupts = <2>;
			};

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
				};
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <11>;
				};
			};

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart2: serial@b000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xb000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <10>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart2_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sysctrl: system-controller@d000 {
				compatible = "simple-mfd", "syscon";
				reg = <0xd000 0x100>;

				sys_pinctrl: pin-controller {
					compatible = "marvell,berlin2-system-pinctrl";
					uart0_pmux: uart0-pmux {
						groups = "GSM4";
						function = "uart0";
					};

					uart1_pmux: uart1-pmux {
						groups = "GSM5";
						function = "uart1";
					};
					uart2_pmux: uart2-pmux {
						groups = "GSM3";
						function = "uart2";
					};
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
2440946c SH	1	/*
	2	* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
	3	*
	4	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	5	*
	6	* based on GPL'ed 2.6 kernel sources
	7	* (c) Marvell International Ltd.
	8	*
267f9107 AT	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPL or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This file is licensed under the terms of the GNU General Public
	15	* License version 2. This program is licensed "as is" without any
	16	* warranty of any kind, whether express or implied.
	17	*
	18	* Or, alternatively,
	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
	23	* restriction, including without limitation the rights to use,
	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
	32	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
2440946c SH	40	*/
2440946c SH	41
36601dbf	42	#include <dt-bindings/clock/berlin2.h>
2440946c SH	43	#include <dt-bindings/interrupt-controller/arm-gic.h>
	44
	45	/ {
	46	model = "Marvell Armada 1500 (BG2) SoC";
	47	compatible = "marvell,berlin2", "marvell,berlin";
2653c8cb JZ	48	#address-cells = <1>;
2653c8cb JZ	49	#size-cells = <1>;
2440946c	50
487eacb9 JZ	51	aliases {
	52	serial0 = &uart0;
	53	serial1 = &uart1;
	54	serial2 = &uart2;
	55	};
	56
2440946c SH	57	cpus {
	58	#address-cells = <1>;
	59	#size-cells = <0>;
460d02ac	60	enable-method = "marvell,berlin-smp";
2440946c SH	61
	62	cpu@0 {
	63	compatible = "marvell,pj4b";
	64	device_type = "cpu";
	65	next-level-cache = <&l2>;
	66	reg = <0>;
2e1782ad AT	67
	68	clocks = <&chip_clk CLKID_CPU>;
	69	clock-latency = <100000>;
	70	operating-points = <
	71	/* kHz uV */
	72	1200000 1200000
	73	1000000 1200000
	74	800000 1200000
	75	600000 1200000
	76	>;
2440946c SH	77	};
	78
	79	cpu@1 {
	80	compatible = "marvell,pj4b";
	81	device_type = "cpu";
	82	next-level-cache = <&l2>;
	83	reg = <1>;
	84	};
	85	};
	86
36601dbf SH	87	refclk: oscillator {
	88	compatible = "fixed-clock";
	89	#clock-cells = <0>;
	90	clock-frequency = <25000000>;
2440946c SH	91	};
2440946c SH	92
a6942e9f	93	soc@f7000000 {
2440946c SH	94	compatible = "simple-bus";
	95	#address-cells = <1>;
	96	#size-cells = <1>;
	97	interrupt-parent = <&gic>;
	98
	99	ranges = <0 0xf7000000 0x1000000>;
	100
652538c4 SH	101	sdhci0: sdhci@ab0000 {
	102	compatible = "mrvl,pxav3-mmc";
	103	reg = <0xab0000 0x200>;
18df8165	104	clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
652538c4 SH	105	clock-names = "io", "core";
	106	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	107	status = "disabled";
	108	};
	109
	110	sdhci1: sdhci@ab0800 {
	111	compatible = "mrvl,pxav3-mmc";
	112	reg = <0xab0800 0x200>;
18df8165	113	clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
652538c4 SH	114	clock-names = "io", "core";
	115	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	116	status = "disabled";
	117	};
	118
	119	sdhci2: sdhci@ab1000 {
	120	compatible = "mrvl,pxav3-mmc";
	121	reg = <0xab1000 0x200>;
	122	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
18df8165	123	clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
652538c4 SH	124	clock-names = "io", "core";
	125	pinctrl-0 = <&emmc_pmux>;
	126	pinctrl-names = "default";
	127	status = "disabled";
	128	};
	129
2440946c SH	130	l2: l2-cache-controller@ac0000 {
	131	compatible = "marvell,tauros3-cache", "arm,pl310-cache";
	132	reg = <0xac0000 0x1000>;
	133	cache-unified;
	134	cache-level = <2>;
	135	};
	136
0bd4b346 SH	137	scu: snoop-control-unit@ad0000 {
	138	compatible = "arm,cortex-a9-scu";
	139	reg = <0xad0000 0x58>;
	140	};
	141
2440946c SH	142	gic: interrupt-controller@ad1000 {
	143	compatible = "arm,cortex-a9-gic";
	144	reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
	145	interrupt-controller;
	146	#interrupt-cells = <3>;
	147	};
	148
	149	local-timer@ad0600 {
	150	compatible = "arm,cortex-a9-twd-timer";
	151	reg = <0xad0600 0x20>;
2356d2f3	152	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
18df8165	153	clocks = <&chip_clk CLKID_TWD>;
2440946c SH	154	};
2440946c SH	155
ae01f64b SH	156	eth1: ethernet@b90000 {
	157	compatible = "marvell,pxa168-eth";
	158	reg = <0xb90000 0x10000>;
18df8165	159	clocks = <&chip_clk CLKID_GETH1>;
ae01f64b SH	160	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	161	/* set by bootloader */
	162	local-mac-address = [00 00 00 00 00 00];
	163	#address-cells = <1>;
	164	#size-cells = <0>;
	165	phy-connection-type = "mii";
	166	phy-handle = <&ethphy1>;
	167	status = "disabled";
	168
	169	ethphy1: ethernet-phy@0 {
	170	reg = <0>;
	171	};
	172	};
	173
460d02ac AT	174	cpu-ctrl@dd0000 {
	175	compatible = "marvell,berlin-cpu-ctrl";
	176	reg = <0xdd0000 0x10000>;
	177	};
	178
ae01f64b SH	179	eth0: ethernet@e50000 {
	180	compatible = "marvell,pxa168-eth";
	181	reg = <0xe50000 0x10000>;
18df8165	182	clocks = <&chip_clk CLKID_GETH0>;
ae01f64b SH	183	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	184	/* set by bootloader */
	185	local-mac-address = [00 00 00 00 00 00];
	186	#address-cells = <1>;
	187	#size-cells = <0>;
	188	phy-connection-type = "mii";
	189	phy-handle = <&ethphy0>;
	190	status = "disabled";
	191
	192	ethphy0: ethernet-phy@0 {
	193	reg = <0>;
	194	};
	195	};
	196
2440946c SH	197	apb@e80000 {
	198	compatible = "simple-bus";
	199	#address-cells = <1>;
	200	#size-cells = <1>;
	201
	202	ranges = <0 0xe80000 0x10000>;
	203	interrupt-parent = <&aic>;
	204
6d3da018 AT	205	gpio0: gpio@0400 {
	206	compatible = "snps,dw-apb-gpio";
	207	reg = <0x0400 0x400>;
	208	#address-cells = <1>;
	209	#size-cells = <0>;
	210
	211	porta: gpio-port@0 {
	212	compatible = "snps,dw-apb-gpio-port";
	213	gpio-controller;
	214	#gpio-cells = <2>;
	215	snps,nr-gpios = <8>;
	216	reg = <0>;
	217	interrupt-controller;
	218	#interrupt-cells = <2>;
	219	interrupts = <0>;
	220	};
	221	};
	222
	223	gpio1: gpio@0800 {
	224	compatible = "snps,dw-apb-gpio";
	225	reg = <0x0800 0x400>;
	226	#address-cells = <1>;
	227	#size-cells = <0>;
	228
	229	portb: gpio-port@1 {
	230	compatible = "snps,dw-apb-gpio-port";
	231	gpio-controller;
	232	#gpio-cells = <2>;
	233	snps,nr-gpios = <8>;
	234	reg = <0>;
	235	interrupt-controller;
	236	#interrupt-cells = <2>;
	237	interrupts = <1>;
	238	};
	239	};
	240
	241	gpio2: gpio@0c00 {
	242	compatible = "snps,dw-apb-gpio";
	243	reg = <0x0c00 0x400>;
	244	#address-cells = <1>;
	245	#size-cells = <0>;
	246
	247	portc: gpio-port@2 {
	248	compatible = "snps,dw-apb-gpio-port";
	249	gpio-controller;
	250	#gpio-cells = <2>;
	251	snps,nr-gpios = <8>;
	252	reg = <0>;
	253	interrupt-controller;
	254	#interrupt-cells = <2>;
	255	interrupts = <2>;
	256	};
	257	};
	258
	259	gpio3: gpio@1000 {
	260	compatible = "snps,dw-apb-gpio";
	261	reg = <0x1000 0x400>;
	262	#address-cells = <1>;
	263	#size-cells = <0>;
	264
	265	portd: gpio-port@3 {
	266	compatible = "snps,dw-apb-gpio-port";
	267	gpio-controller;
	268	#gpio-cells = <2>;
269	snps,nr-gpios = <8>;
270	reg = <0>;
271	interrupt-controller;
272	#interrupt-cells = <2>;
273	interrupts = <3>;
274	};
275	};
276
2440946c SH	277	timer0: timer@2c00 {
	278	compatible = "snps,dw-apb-timer";
	279	reg = <0x2c00 0x14>;
	280	interrupts = <8>;
18df8165	281	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	282	clock-names = "timer";
	283	status = "okay";
	284	};
	285
	286	timer1: timer@2c14 {
	287	compatible = "snps,dw-apb-timer";
	288	reg = <0x2c14 0x14>;
	289	interrupts = <9>;
18df8165	290	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	291	clock-names = "timer";
	292	status = "okay";
	293	};
	294
	295	timer2: timer@2c28 {
	296	compatible = "snps,dw-apb-timer";
	297	reg = <0x2c28 0x14>;
	298	interrupts = <10>;
18df8165	299	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	300	clock-names = "timer";
	301	status = "disabled";
	302	};
	303
	304	timer3: timer@2c3c {
	305	compatible = "snps,dw-apb-timer";
	306	reg = <0x2c3c 0x14>;
	307	interrupts = <11>;
18df8165	308	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	309	clock-names = "timer";
	310	status = "disabled";
	311	};
	312
	313	timer4: timer@2c50 {
	314	compatible = "snps,dw-apb-timer";
	315	reg = <0x2c50 0x14>;
	316	interrupts = <12>;
18df8165	317	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	318	clock-names = "timer";
	319	status = "disabled";
	320	};
	321
	322	timer5: timer@2c64 {
	323	compatible = "snps,dw-apb-timer";
	324	reg = <0x2c64 0x14>;
	325	interrupts = <13>;
18df8165	326	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	327	clock-names = "timer";
	328	status = "disabled";
	329	};
	330
	331	timer6: timer@2c78 {
	332	compatible = "snps,dw-apb-timer";
	333	reg = <0x2c78 0x14>;
	334	interrupts = <14>;
18df8165	335	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	336	clock-names = "timer";
	337	status = "disabled";
	338	};
	339
	340	timer7: timer@2c8c {
	341	compatible = "snps,dw-apb-timer";
	342	reg = <0x2c8c 0x14>;
	343	interrupts = <15>;
18df8165	344	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	345	clock-names = "timer";
	346	status = "disabled";
	347	};
	348
	349	aic: interrupt-controller@3000 {
	350	compatible = "snps,dw-apb-ictl";
	351	reg = <0x3000 0xc00>;
	352	interrupt-controller;
	353	#interrupt-cells = <1>;
	354	interrupt-parent = <&gic>;
	355	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	356	};
	357	};
	358
878a3ee3 SH	359	ahci: sata@e90000 {
	360	compatible = "marvell,berlin2-ahci", "generic-ahci";
	361	reg = <0xe90000 0x1000>;
	362	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
18df8165	363	clocks = <&chip_clk CLKID_SATA>;
878a3ee3 SH	364	#address-cells = <1>;
	365	#size-cells = <0>;
	366
	367	sata0: sata-port@0 {
	368	reg = <0>;
	369	phys = <&sata_phy 0>;
	370	status = "disabled";
	371	};
	372
	373	sata1: sata-port@1 {
	374	reg = <1>;
	375	phys = <&sata_phy 1>;
	376	status = "disabled";
	377	};
	378	};
	379
	380	sata_phy: phy@e900a0 {
	381	compatible = "marvell,berlin2-sata-phy";
	382	reg = <0xe900a0 0x200>;
18df8165	383	clocks = <&chip_clk CLKID_SATA>;
878a3ee3 SH	384	#address-cells = <1>;
	385	#size-cells = <0>;
	386	#phy-cells = <1>;
	387	status = "disabled";
	388
	389	sata-phy@0 {
	390	reg = <0>;
	391	};
	392
	393	sata-phy@1 {
	394	reg = <1>;
	395	};
	396	};
	397
36601dbf	398	chip: chip-control@ea0000 {
f3f94f71	399	compatible = "simple-mfd", "syscon";
36601dbf	400	reg = <0xea0000 0x400>;
652538c4	401
18df8165 AT	402	chip_clk: clock {
	403	compatible = "marvell,berlin2-clk";
	404	#clock-cells = <1>;
	405	clocks = <&refclk>;
	406	clock-names = "refclk";
	407	};
652538c4	408
630c986b AT	409	soc_pinctrl: pin-controller {
	410	compatible = "marvell,berlin2-soc-pinctrl";
	411
	412	emmc_pmux: emmc-pmux {
	413	groups = "G26";
	414	function = "emmc";
	415	};
652538c4	416	};
43225728 AT	417
	418	chip_rst: reset {
	419	compatible = "marvell,berlin2-reset";
	420	#reset-cells = <2>;
652538c4	421	};
0bd4b346 SH	422	};
0bd4b346 SH	423
8eaaaa6f AT	424	pwm: pwm@f20000 {
	425	compatible = "marvell,berlin-pwm";
	426	reg = <0xf20000 0x40>;
	427	clocks = <&chip_clk CLKID_CFG>;
	428	#pwm-cells = <3>;
	429	};
	430
2440946c SH	431	apb@fc0000 {
	432	compatible = "simple-bus";
	433	#address-cells = <1>;
	434	#size-cells = <1>;
	435
	436	ranges = <0 0xfc0000 0x10000>;
	437	interrupt-parent = <&sic>;
	438
4b6c390b JZ	439	wdt0: watchdog@1000 {
	440	compatible = "snps,dw-wdt";
	441	reg = <0x1000 0x100>;
	442	clocks = <&refclk>;
	443	interrupts = <0>;
	444	};
	445
	446	wdt1: watchdog@2000 {
	447	compatible = "snps,dw-wdt";
	448	reg = <0x2000 0x100>;
	449	clocks = <&refclk>;
	450	interrupts = <1>;
4b6c390b JZ	451	};
	452
	453	wdt2: watchdog@3000 {
	454	compatible = "snps,dw-wdt";
	455	reg = <0x3000 0x100>;
	456	clocks = <&refclk>;
	457	interrupts = <2>;
4b6c390b JZ	458	};
4b6c390b JZ	459
6d3da018 AT	460	sm_gpio1: gpio@5000 {
	461	compatible = "snps,dw-apb-gpio";
	462	reg = <0x5000 0x400>;
	463	#address-cells = <1>;
	464	#size-cells = <0>;
	465
	466	portf: gpio-port@5 {
	467	compatible = "snps,dw-apb-gpio-port";
	468	gpio-controller;
	469	#gpio-cells = <2>;
	470	snps,nr-gpios = <8>;
	471	reg = <0>;
	472	};
	473	};
	474
	475	sm_gpio0: gpio@c000 {
	476	compatible = "snps,dw-apb-gpio";
	477	reg = <0xc000 0x400>;
	478	#address-cells = <1>;
	479	#size-cells = <0>;
	480
	481	porte: gpio-port@4 {
	482	compatible = "snps,dw-apb-gpio-port";
	483	gpio-controller;
	484	#gpio-cells = <2>;
	485	snps,nr-gpios = <8>;
	486	reg = <0>;
	487	interrupt-controller;
	488	#interrupt-cells = <2>;
	489	interrupts = <11>;
	490	};
	491	};
	492
2440946c SH	493	uart0: serial@9000 {
	494	compatible = "snps,dw-apb-uart";
	495	reg = <0x9000 0x100>;
	496	reg-shift = <2>;
	497	reg-io-width = <1>;
	498	interrupts = <8>;
36601dbf	499	clocks = <&refclk>;
50cc24ff AT	500	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	501	pinctrl-names = "default";
2440946c SH	502	status = "disabled";
	503	};
	504
	505	uart1: serial@a000 {
	506	compatible = "snps,dw-apb-uart";
	507	reg = <0xa000 0x100>;
	508	reg-shift = <2>;
	509	reg-io-width = <1>;
	510	interrupts = <9>;
36601dbf	511	clocks = <&refclk>;
50cc24ff AT	512	pinctrl-0 = <&uart1_pmux>;
50cc24ff AT	513	pinctrl-names = "default";
2440946c SH	514	status = "disabled";
	515	};
	516
	517	uart2: serial@b000 {
	518	compatible = "snps,dw-apb-uart";
	519	reg = <0xb000 0x100>;
	520	reg-shift = <2>;
	521	reg-io-width = <1>;
	522	interrupts = <10>;
36601dbf	523	clocks = <&refclk>;
50cc24ff AT	524	pinctrl-0 = <&uart2_pmux>;
50cc24ff AT	525	pinctrl-names = "default";
2440946c SH	526	status = "disabled";
	527	};
	528
50cc24ff	529	sysctrl: system-controller@d000 {
f3f94f71	530	compatible = "simple-mfd", "syscon";
50cc24ff AT	531	reg = <0xd000 0x100>;
50cc24ff AT	532
630c986b AT	533	sys_pinctrl: pin-controller {
	534	compatible = "marvell,berlin2-system-pinctrl";
	535	uart0_pmux: uart0-pmux {
	536	groups = "GSM4";
	537	function = "uart0";
	538	};
	539
	540	uart1_pmux: uart1-pmux {
	541	groups = "GSM5";
	542	function = "uart1";
	543	};
	544	uart2_pmux: uart2-pmux {
	545	groups = "GSM3";
	546	function = "uart2";
	547	};
50cc24ff AT	548	};
	549	};
	550
2440946c SH	551	sic: interrupt-controller@e000 {
	552	compatible = "snps,dw-apb-ictl";
	553	reg = <0xe000 0x400>;
	554	interrupt-controller;
	555	#interrupt-cells = <1>;
	556	interrupt-parent = <&gic>;
	557	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	558	};
	559	};
	560	};
	561	};