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46d4bca0 FF |
1 | /* |
2 | * Broadcom BCM63138 DSL SoCs Device Tree | |
3 | */ | |
4 | ||
5 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
6 | #include <dt-bindings/interrupt-controller/irq.h> | |
7 | ||
8 | #include "skeleton.dtsi" | |
9 | ||
10 | / { | |
11 | compatible = "brcm,bcm63138"; | |
12 | model = "Broadcom BCM63138 DSL SoC"; | |
13 | interrupt-parent = <&gic>; | |
14 | ||
15 | aliases { | |
16 | uart0 = &serial0; | |
17 | uart1 = &serial1; | |
18 | }; | |
19 | ||
20 | cpus { | |
21 | #address-cells = <1>; | |
22 | #size-cells = <0>; | |
23 | ||
24 | cpu@0 { | |
25 | device_type = "cpu"; | |
26 | compatible = "arm,cortex-a9"; | |
27 | next-level-cache = <&L2>; | |
28 | reg = <0>; | |
9f988029 | 29 | enable-method = "brcm,bcm63138"; |
46d4bca0 FF |
30 | }; |
31 | ||
32 | cpu@1 { | |
33 | device_type = "cpu"; | |
34 | compatible = "arm,cortex-a9"; | |
35 | next-level-cache = <&L2>; | |
36 | reg = <1>; | |
9f988029 FF |
37 | enable-method = "brcm,bcm63138"; |
38 | resets = <&pmb0 4 1>; | |
46d4bca0 FF |
39 | }; |
40 | }; | |
41 | ||
42 | clocks { | |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
511d3044 | 46 | /* UBUS peripheral clock */ |
46d4bca0 FF |
47 | periph_clk: periph_clk { |
48 | #clock-cells = <0>; | |
49 | compatible = "fixed-clock"; | |
50 | clock-frequency = <50000000>; | |
51 | clock-output-names = "periph"; | |
52 | }; | |
511d3044 FF |
53 | |
54 | /* peripheral clock for system timer */ | |
55 | axi_clk: axi_clk { | |
56 | #clock-cells = <0>; | |
57 | compatible = "fixed-factor-clock"; | |
58 | clocks = <&armpll>; | |
59 | clock-div = <2>; | |
60 | clock-mult = <1>; | |
61 | }; | |
62 | ||
63 | /* APB bus clock */ | |
64 | apb_clk: apb_clk { | |
65 | #clock-cells = <0>; | |
66 | compatible = "fixed-factor-clock"; | |
67 | clocks = <&armpll>; | |
68 | clock-div = <4>; | |
69 | clock-mult = <1>; | |
70 | }; | |
46d4bca0 FF |
71 | }; |
72 | ||
73 | /* ARM bus */ | |
74 | axi@80000000 { | |
75 | compatible = "simple-bus"; | |
76 | ranges = <0 0x80000000 0x784000>; | |
77 | #address-cells = <1>; | |
78 | #size-cells = <1>; | |
79 | ||
80 | L2: cache-controller@1d000 { | |
81 | compatible = "arm,pl310-cache"; | |
82 | reg = <0x1d000 0x1000>; | |
83 | cache-unified; | |
84 | cache-level = <2>; | |
9df11828 FF |
85 | cache-size = <524288>; |
86 | cache-sets = <1024>; | |
87 | cache-line-size = <32>; | |
46d4bca0 FF |
88 | interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; |
89 | }; | |
90 | ||
91 | scu: scu@1e000 { | |
92 | compatible = "arm,cortex-a9-scu"; | |
93 | reg = <0x1e000 0x100>; | |
94 | }; | |
95 | ||
96 | gic: interrupt-controller@1e100 { | |
97 | compatible = "arm,cortex-a9-gic"; | |
98 | reg = <0x1f000 0x1000 | |
99 | 0x1e100 0x100>; | |
100 | #interrupt-cells = <3>; | |
101 | #address-cells = <0>; | |
102 | interrupt-controller; | |
103 | }; | |
104 | ||
105 | global_timer: timer@1e200 { | |
106 | compatible = "arm,cortex-a9-global-timer"; | |
107 | reg = <0x1e200 0x20>; | |
108 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
511d3044 | 109 | clocks = <&axi_clk>; |
46d4bca0 FF |
110 | }; |
111 | ||
112 | local_timer: local-timer@1e600 { | |
113 | compatible = "arm,cortex-a9-twd-timer"; | |
114 | reg = <0x1e600 0x20>; | |
115 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
511d3044 | 116 | clocks = <&axi_clk>; |
46d4bca0 FF |
117 | }; |
118 | ||
119 | twd_watchdog: watchdog@1e620 { | |
120 | compatible = "arm,cortex-a9-twd-wdt"; | |
121 | reg = <0x1e620 0x20>; | |
cbd25516 | 122 | interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>; |
46d4bca0 | 123 | }; |
39afb980 | 124 | |
511d3044 FF |
125 | armpll: armpll { |
126 | #clock-cells = <0>; | |
127 | compatible = "brcm,bcm63138-armpll"; | |
128 | clocks = <&periph_clk>; | |
129 | reg = <0x20000 0xf00>; | |
130 | }; | |
131 | ||
39afb980 FF |
132 | pmb0: reset-controller@4800c0 { |
133 | compatible = "brcm,bcm63138-pmb"; | |
134 | reg = <0x4800c0 0x10>; | |
135 | #reset-cells = <2>; | |
136 | }; | |
137 | ||
138 | pmb1: reset-controller@4800e0 { | |
139 | compatible = "brcm,bcm63138-pmb"; | |
140 | reg = <0x4800e0 0x10>; | |
141 | #reset-cells = <2>; | |
142 | }; | |
46d4bca0 FF |
143 | }; |
144 | ||
145 | /* Legacy UBUS base */ | |
146 | ubus@fffe8000 { | |
147 | compatible = "simple-bus"; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <1>; | |
150 | ranges = <0 0xfffe8000 0x8100>; | |
151 | ||
8ab14288 FF |
152 | timer: timer@80 { |
153 | compatible = "brcm,bcm6328-timer", "syscon"; | |
154 | reg = <0x80 0x3c>; | |
155 | }; | |
156 | ||
46d4bca0 FF |
157 | serial0: serial@600 { |
158 | compatible = "brcm,bcm6345-uart"; | |
159 | reg = <0x600 0x1b>; | |
160 | interrupts = <GIC_SPI 32 0>; | |
161 | clocks = <&periph_clk>; | |
162 | clock-names = "periph"; | |
163 | status = "disabled"; | |
164 | }; | |
165 | ||
166 | serial1: serial@620 { | |
167 | compatible = "brcm,bcm6345-uart"; | |
168 | reg = <0x620 0x1b>; | |
169 | interrupts = <GIC_SPI 33 0>; | |
170 | clocks = <&periph_clk>; | |
171 | clock-names = "periph"; | |
172 | status = "disabled"; | |
173 | }; | |
9f988029 | 174 | |
9d7ef1b7 FF |
175 | nand: nand@2000 { |
176 | #address-cells = <1>; | |
177 | #size-cells = <0>; | |
178 | compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; | |
179 | reg = <0x2000 0x600>, <0xf0 0x10>; | |
180 | reg-names = "nand", "nand-int-base"; | |
181 | status = "disabled"; | |
182 | interrupts = <GIC_SPI 38 0>; | |
183 | interrupt-names = "nand"; | |
184 | }; | |
185 | ||
9f988029 FF |
186 | bootlut: bootlut@8000 { |
187 | compatible = "brcm,bcm63138-bootlut"; | |
188 | reg = <0x8000 0x50>; | |
189 | }; | |
8ab14288 FF |
190 | |
191 | reboot { | |
192 | compatible = "syscon-reboot"; | |
193 | regmap = <&timer>; | |
194 | offset = <0x34>; | |
195 | mask = <1>; | |
196 | }; | |
46d4bca0 FF |
197 | }; |
198 | }; |