Commit | Line | Data |
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7d76d03b ZS |
1 | /* |
2 | * DTS file for CSR SiRFatlas7 SoC | |
3 | * | |
4 | * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | / { | |
11 | compatible = "sirf,atlas7"; | |
12 | #address-cells = <1>; | |
13 | #size-cells = <1>; | |
14 | interrupt-parent = <&gic>; | |
15 | aliases { | |
16 | serial0 = &uart0; | |
17 | serial1 = &uart1; | |
18 | serial2 = &uart2; | |
19 | serial3 = &uart3; | |
20 | serial4 = &uart4; | |
21 | serial5 = &uart5; | |
22 | serial6 = &uart6; | |
23 | serial9 = &usp2; | |
24 | }; | |
25 | cpus { | |
26 | #address-cells = <1>; | |
27 | #size-cells = <0>; | |
28 | ||
29 | cpu@0 { | |
30 | device_type = "cpu"; | |
31 | compatible = "arm,cortex-a7"; | |
32 | reg = <0>; | |
33 | }; | |
34 | cpu@1 { | |
35 | device_type = "cpu"; | |
36 | compatible = "arm,cortex-a7"; | |
37 | reg = <1>; | |
38 | }; | |
39 | }; | |
40 | ||
9c684e29 GZ |
41 | clocks { |
42 | xinw { | |
43 | compatible = "fixed-clock"; | |
44 | #clock-cells = <0>; | |
45 | clock-frequency = <32768>; | |
46 | clock-output-names = "xinw"; | |
47 | }; | |
48 | xin { | |
49 | compatible = "fixed-clock"; | |
50 | #clock-cells = <0>; | |
51 | clock-frequency = <26000000>; | |
52 | clock-output-names = "xin"; | |
53 | }; | |
54 | }; | |
55 | ||
c95c6211 YH |
56 | arm-pmu { |
57 | compatible = "arm,cortex-a7-pmu"; | |
58 | interrupts = <0 29 4>, <0 82 4>; | |
59 | }; | |
60 | ||
7d76d03b ZS |
61 | noc { |
62 | compatible = "simple-bus"; | |
63 | #address-cells = <1>; | |
64 | #size-cells = <1>; | |
65 | ranges = <0x10000000 0x10000000 0xc0000000>; | |
66 | ||
67 | gic: interrupt-controller@10301000 { | |
68 | compatible = "arm,cortex-a9-gic"; | |
69 | interrupt-controller; | |
70 | #interrupt-cells = <3>; | |
71 | reg = <0x10301000 0x1000>, | |
72 | <0x10302000 0x0100>; | |
73 | }; | |
74 | ||
75 | pmu_regulator: pmu_regulator@10E30020 { | |
76 | compatible = "sirf,atlas7-pmu-ldo"; | |
77 | reg = <0x10E30020 0x4>; | |
78 | ldo: ldo { | |
79 | regulator-name = "ldo"; | |
80 | }; | |
81 | }; | |
82 | ||
83 | atlas7_codec: atlas7_codec@10E30000 { | |
84 | #sound-dai-cells = <0>; | |
85 | compatible = "sirf,atlas7-codec"; | |
86 | reg = <0x10E30000 0x400>; | |
87 | clocks = <&car 62>; | |
88 | ldo-supply = <&ldo>; | |
89 | }; | |
90 | ||
91 | atlas7_iacc: atlas7_iacc@10D01000 { | |
92 | #sound-dai-cells = <0>; | |
93 | compatible = "sirf,atlas7-iacc"; | |
94 | reg = <0x10D01000 0x100>; | |
95 | dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>, | |
96 | <&dmac3 3>, <&dmac3 9>; | |
97 | dma-names = "rx", "tx0", "tx1", "tx2", "tx3"; | |
98 | clocks = <&car 62>; | |
99 | }; | |
100 | ||
101 | ipc@13240000 { | |
102 | compatible = "sirf,atlas7-ipc"; | |
103 | ranges = <0x13240000 0x13240000 0x00010000>; | |
104 | #address-cells = <1>; | |
105 | #size-cells = <1>; | |
106 | ||
107 | hwspinlock { | |
108 | compatible = "sirf,hwspinlock"; | |
109 | reg = <0x13240000 0x00010000>; | |
110 | ||
111 | num-spinlocks = <30>; | |
112 | }; | |
113 | ||
114 | ns_m3_rproc@0 { | |
115 | compatible = "sirf,ns2m30-rproc"; | |
116 | reg = <0x13240000 0x00010000>; | |
117 | interrupts = <0 123 0>; | |
118 | }; | |
119 | ||
120 | ns_m3_rproc@1 { | |
121 | compatible = "sirf,ns2m31-rproc"; | |
122 | reg = <0x13240000 0x00010000>; | |
123 | interrupts = <0 126 0>; | |
124 | }; | |
125 | ||
126 | ns_kal_rproc@0 { | |
127 | compatible = "sirf,ns2kal0-rproc"; | |
128 | reg = <0x13240000 0x00010000>; | |
129 | interrupts = <0 124 0>; | |
130 | }; | |
131 | ||
132 | ns_kal_rproc@1 { | |
133 | compatible = "sirf,ns2kal1-rproc"; | |
134 | reg = <0x13240000 0x00010000>; | |
135 | interrupts = <0 127 0>; | |
136 | }; | |
137 | }; | |
138 | ||
139 | pinctrl: ioc@18880000 { | |
140 | compatible = "sirf,atlas7-ioc"; | |
141 | reg = <0x18880000 0x1000>, | |
142 | <0x10E40000 0x1000>; | |
27b0d37e WC |
143 | |
144 | audio_ac97_pmx: audio_ac97@0 { | |
145 | audio_ac97 { | |
146 | groups = "audio_ac97_grp"; | |
147 | function = "audio_ac97"; | |
148 | }; | |
149 | }; | |
150 | ||
151 | audio_func_dbg_pmx: audio_func_dbg@0 { | |
152 | audio_func_dbg { | |
153 | groups = "audio_func_dbg_grp"; | |
154 | function = "audio_func_dbg"; | |
155 | }; | |
156 | }; | |
157 | ||
158 | audio_i2s_pmx: audio_i2s@0 { | |
159 | audio_i2s { | |
160 | groups = "audio_i2s_grp"; | |
161 | function = "audio_i2s"; | |
162 | }; | |
163 | }; | |
164 | ||
165 | audio_i2s_2ch_pmx: audio_i2s_2ch@0 { | |
166 | audio_i2s_2ch { | |
167 | groups = "audio_i2s_2ch_grp"; | |
168 | function = "audio_i2s_2ch"; | |
169 | }; | |
170 | }; | |
171 | ||
172 | audio_i2s_extclk_pmx: audio_i2s_extclk@0 { | |
173 | audio_i2s_extclk { | |
174 | groups = "audio_i2s_extclk_grp"; | |
175 | function = "audio_i2s_extclk"; | |
176 | }; | |
177 | }; | |
178 | ||
179 | audio_uart0_pmx: audio_uart0@0 { | |
180 | audio_uart0 { | |
181 | groups = "audio_uart0_grp"; | |
182 | function = "audio_uart0"; | |
183 | }; | |
184 | }; | |
185 | ||
186 | audio_uart1_pmx: audio_uart1@0 { | |
187 | audio_uart1 { | |
188 | groups = "audio_uart1_grp"; | |
189 | function = "audio_uart1"; | |
190 | }; | |
191 | }; | |
192 | ||
193 | audio_uart2_pmx0: audio_uart2@0 { | |
194 | audio_uart2_0 { | |
195 | groups = "audio_uart2_grp0"; | |
196 | function = "audio_uart2_m0"; | |
197 | }; | |
198 | }; | |
199 | ||
200 | audio_uart2_pmx1: audio_uart2@1 { | |
201 | audio_uart2_1 { | |
202 | groups = "audio_uart2_grp1"; | |
203 | function = "audio_uart2_m1"; | |
204 | }; | |
205 | }; | |
206 | ||
207 | c_can_trnsvr_pmx: c_can_trnsvr@0 { | |
208 | c_can_trnsvr { | |
209 | groups = "c_can_trnsvr_grp"; | |
210 | function = "c_can_trnsvr"; | |
211 | }; | |
212 | }; | |
213 | ||
214 | c0_can_pmx0: c0_can@0 { | |
215 | c0_can_0 { | |
216 | groups = "c0_can_grp0"; | |
217 | function = "c0_can_m0"; | |
218 | }; | |
219 | }; | |
220 | ||
221 | c0_can_pmx1: c0_can@1 { | |
222 | c0_can_1 { | |
223 | groups = "c0_can_grp1"; | |
224 | function = "c0_can_m1"; | |
225 | }; | |
226 | }; | |
227 | ||
228 | c1_can_pmx0: c1_can@0 { | |
229 | c1_can_0 { | |
230 | groups = "c1_can_grp0"; | |
231 | function = "c1_can_m0"; | |
232 | }; | |
233 | }; | |
234 | ||
235 | c1_can_pmx1: c1_can@1 { | |
236 | c1_can_1 { | |
237 | groups = "c1_can_grp1"; | |
238 | function = "c1_can_m1"; | |
239 | }; | |
240 | }; | |
241 | ||
242 | c1_can_pmx2: c1_can@2 { | |
243 | c1_can_2 { | |
244 | groups = "c1_can_grp2"; | |
245 | function = "c1_can_m2"; | |
246 | }; | |
247 | }; | |
248 | ||
249 | ca_audio_lpc_pmx: ca_audio_lpc@0 { | |
250 | ca_audio_lpc { | |
251 | groups = "ca_audio_lpc_grp"; | |
252 | function = "ca_audio_lpc"; | |
253 | }; | |
254 | }; | |
255 | ||
256 | ca_bt_lpc_pmx: ca_bt_lpc@0 { | |
257 | ca_bt_lpc { | |
258 | groups = "ca_bt_lpc_grp"; | |
259 | function = "ca_bt_lpc"; | |
260 | }; | |
261 | }; | |
262 | ||
263 | ca_coex_pmx: ca_coex@0 { | |
264 | ca_coex { | |
265 | groups = "ca_coex_grp"; | |
266 | function = "ca_coex"; | |
267 | }; | |
268 | }; | |
269 | ||
270 | ca_curator_lpc_pmx: ca_curator_lpc@0 { | |
271 | ca_curator_lpc { | |
272 | groups = "ca_curator_lpc_grp"; | |
273 | function = "ca_curator_lpc"; | |
274 | }; | |
275 | }; | |
276 | ||
277 | ca_pcm_debug_pmx: ca_pcm_debug@0 { | |
278 | ca_pcm_debug { | |
279 | groups = "ca_pcm_debug_grp"; | |
280 | function = "ca_pcm_debug"; | |
281 | }; | |
282 | }; | |
283 | ||
284 | ca_pio_pmx: ca_pio@0 { | |
285 | ca_pio { | |
286 | groups = "ca_pio_grp"; | |
287 | function = "ca_pio"; | |
288 | }; | |
289 | }; | |
290 | ||
291 | ca_sdio_debug_pmx: ca_sdio_debug@0 { | |
292 | ca_sdio_debug { | |
293 | groups = "ca_sdio_debug_grp"; | |
294 | function = "ca_sdio_debug"; | |
295 | }; | |
296 | }; | |
297 | ||
298 | ca_spi_pmx: ca_spi@0 { | |
299 | ca_spi { | |
300 | groups = "ca_spi_grp"; | |
301 | function = "ca_spi"; | |
302 | }; | |
303 | }; | |
304 | ||
305 | ca_trb_pmx: ca_trb@0 { | |
306 | ca_trb { | |
307 | groups = "ca_trb_grp"; | |
308 | function = "ca_trb"; | |
309 | }; | |
310 | }; | |
311 | ||
312 | ca_uart_debug_pmx: ca_uart_debug@0 { | |
313 | ca_uart_debug { | |
314 | groups = "ca_uart_debug_grp"; | |
315 | function = "ca_uart_debug"; | |
316 | }; | |
317 | }; | |
318 | ||
319 | clkc_pmx0: clkc@0 { | |
320 | clkc_0 { | |
321 | groups = "clkc_grp0"; | |
322 | function = "clkc_m0"; | |
323 | }; | |
324 | }; | |
325 | ||
326 | clkc_pmx1: clkc@1 { | |
327 | clkc_1 { | |
328 | groups = "clkc_grp1"; | |
329 | function = "clkc_m1"; | |
330 | }; | |
331 | }; | |
332 | ||
333 | gn_gnss_i2c_pmx: gn_gnss_i2c@0 { | |
334 | gn_gnss_i2c { | |
335 | groups = "gn_gnss_i2c_grp"; | |
336 | function = "gn_gnss_i2c"; | |
337 | }; | |
338 | }; | |
339 | ||
340 | gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 { | |
341 | gn_gnss_uart_nopause { | |
342 | groups = "gn_gnss_uart_nopause_grp"; | |
343 | function = "gn_gnss_uart_nopause"; | |
344 | }; | |
345 | }; | |
346 | ||
347 | gn_gnss_uart_pmx: gn_gnss_uart@0 { | |
348 | gn_gnss_uart { | |
349 | groups = "gn_gnss_uart_grp"; | |
350 | function = "gn_gnss_uart"; | |
351 | }; | |
352 | }; | |
353 | ||
354 | gn_trg_spi_pmx0: gn_trg_spi@0 { | |
355 | gn_trg_spi_0 { | |
356 | groups = "gn_trg_spi_grp0"; | |
357 | function = "gn_trg_spi_m0"; | |
358 | }; | |
359 | }; | |
360 | ||
361 | gn_trg_spi_pmx1: gn_trg_spi@1 { | |
362 | gn_trg_spi_1 { | |
363 | groups = "gn_trg_spi_grp1"; | |
364 | function = "gn_trg_spi_m1"; | |
365 | }; | |
366 | }; | |
367 | ||
368 | cvbs_dbg_pmx: cvbs_dbg@0 { | |
369 | cvbs_dbg { | |
370 | groups = "cvbs_dbg_grp"; | |
371 | function = "cvbs_dbg"; | |
372 | }; | |
373 | }; | |
374 | ||
375 | cvbs_dbg_test_pmx0: cvbs_dbg_test@0 { | |
376 | cvbs_dbg_test_0 { | |
377 | groups = "cvbs_dbg_test_grp0"; | |
378 | function = "cvbs_dbg_test_m0"; | |
379 | }; | |
380 | }; | |
381 | ||
382 | cvbs_dbg_test_pmx1: cvbs_dbg_test@1 { | |
383 | cvbs_dbg_test_1 { | |
384 | groups = "cvbs_dbg_test_grp1"; | |
385 | function = "cvbs_dbg_test_m1"; | |
386 | }; | |
387 | }; | |
388 | ||
389 | cvbs_dbg_test_pmx2: cvbs_dbg_test@2 { | |
390 | cvbs_dbg_test_2 { | |
391 | groups = "cvbs_dbg_test_grp2"; | |
392 | function = "cvbs_dbg_test_m2"; | |
393 | }; | |
394 | }; | |
395 | ||
396 | cvbs_dbg_test_pmx3: cvbs_dbg_test@3 { | |
397 | cvbs_dbg_test_3 { | |
398 | groups = "cvbs_dbg_test_grp3"; | |
399 | function = "cvbs_dbg_test_m3"; | |
400 | }; | |
401 | }; | |
402 | ||
403 | cvbs_dbg_test_pmx4: cvbs_dbg_test@4 { | |
404 | cvbs_dbg_test_4 { | |
405 | groups = "cvbs_dbg_test_grp4"; | |
406 | function = "cvbs_dbg_test_m4"; | |
407 | }; | |
408 | }; | |
409 | ||
410 | cvbs_dbg_test_pmx5: cvbs_dbg_test@5 { | |
411 | cvbs_dbg_test_5 { | |
412 | groups = "cvbs_dbg_test_grp5"; | |
413 | function = "cvbs_dbg_test_m5"; | |
414 | }; | |
415 | }; | |
416 | ||
417 | cvbs_dbg_test_pmx6: cvbs_dbg_test@6 { | |
418 | cvbs_dbg_test_6 { | |
419 | groups = "cvbs_dbg_test_grp6"; | |
420 | function = "cvbs_dbg_test_m6"; | |
421 | }; | |
422 | }; | |
423 | ||
424 | cvbs_dbg_test_pmx7: cvbs_dbg_test@7 { | |
425 | cvbs_dbg_test_7 { | |
426 | groups = "cvbs_dbg_test_grp7"; | |
427 | function = "cvbs_dbg_test_m7"; | |
428 | }; | |
429 | }; | |
430 | ||
431 | cvbs_dbg_test_pmx8: cvbs_dbg_test@8 { | |
432 | cvbs_dbg_test_8 { | |
433 | groups = "cvbs_dbg_test_grp8"; | |
434 | function = "cvbs_dbg_test_m8"; | |
435 | }; | |
436 | }; | |
437 | ||
438 | cvbs_dbg_test_pmx9: cvbs_dbg_test@9 { | |
439 | cvbs_dbg_test_9 { | |
440 | groups = "cvbs_dbg_test_grp9"; | |
441 | function = "cvbs_dbg_test_m9"; | |
442 | }; | |
443 | }; | |
444 | ||
445 | cvbs_dbg_test_pmx10: cvbs_dbg_test@10 { | |
446 | cvbs_dbg_test_10 { | |
447 | groups = "cvbs_dbg_test_grp10"; | |
448 | function = "cvbs_dbg_test_m10"; | |
449 | }; | |
450 | }; | |
451 | ||
452 | cvbs_dbg_test_pmx11: cvbs_dbg_test@11 { | |
453 | cvbs_dbg_test_11 { | |
454 | groups = "cvbs_dbg_test_grp11"; | |
455 | function = "cvbs_dbg_test_m11"; | |
456 | }; | |
457 | }; | |
458 | ||
459 | cvbs_dbg_test_pmx12: cvbs_dbg_test@12 { | |
460 | cvbs_dbg_test_12 { | |
461 | groups = "cvbs_dbg_test_grp12"; | |
462 | function = "cvbs_dbg_test_m12"; | |
463 | }; | |
464 | }; | |
465 | ||
466 | cvbs_dbg_test_pmx13: cvbs_dbg_test@13 { | |
467 | cvbs_dbg_test_13 { | |
468 | groups = "cvbs_dbg_test_grp13"; | |
469 | function = "cvbs_dbg_test_m13"; | |
470 | }; | |
471 | }; | |
472 | ||
473 | cvbs_dbg_test_pmx14: cvbs_dbg_test@14 { | |
474 | cvbs_dbg_test_14 { | |
475 | groups = "cvbs_dbg_test_grp14"; | |
476 | function = "cvbs_dbg_test_m14"; | |
477 | }; | |
478 | }; | |
479 | ||
480 | cvbs_dbg_test_pmx15: cvbs_dbg_test@15 { | |
481 | cvbs_dbg_test_15 { | |
482 | groups = "cvbs_dbg_test_grp15"; | |
483 | function = "cvbs_dbg_test_m15"; | |
484 | }; | |
485 | }; | |
486 | ||
487 | gn_gnss_power_pmx: gn_gnss_power@0 { | |
488 | gn_gnss_power { | |
489 | groups = "gn_gnss_power_grp"; | |
490 | function = "gn_gnss_power"; | |
491 | }; | |
492 | }; | |
493 | ||
494 | gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 { | |
495 | gn_gnss_sw_status { | |
496 | groups = "gn_gnss_sw_status_grp"; | |
497 | function = "gn_gnss_sw_status"; | |
498 | }; | |
499 | }; | |
500 | ||
501 | gn_gnss_eclk_pmx: gn_gnss_eclk@0 { | |
502 | gn_gnss_eclk { | |
503 | groups = "gn_gnss_eclk_grp"; | |
504 | function = "gn_gnss_eclk"; | |
505 | }; | |
506 | }; | |
507 | ||
508 | gn_gnss_irq1_pmx0: gn_gnss_irq1@0 { | |
509 | gn_gnss_irq1_0 { | |
510 | groups = "gn_gnss_irq1_grp0"; | |
511 | function = "gn_gnss_irq1_m0"; | |
512 | }; | |
513 | }; | |
514 | ||
515 | gn_gnss_irq2_pmx0: gn_gnss_irq2@0 { | |
516 | gn_gnss_irq2_0 { | |
517 | groups = "gn_gnss_irq2_grp0"; | |
518 | function = "gn_gnss_irq2_m0"; | |
519 | }; | |
520 | }; | |
521 | ||
522 | gn_gnss_tm_pmx: gn_gnss_tm@0 { | |
523 | gn_gnss_tm { | |
524 | groups = "gn_gnss_tm_grp"; | |
525 | function = "gn_gnss_tm"; | |
526 | }; | |
527 | }; | |
528 | ||
529 | gn_gnss_tsync_pmx: gn_gnss_tsync@0 { | |
530 | gn_gnss_tsync { | |
531 | groups = "gn_gnss_tsync_grp"; | |
532 | function = "gn_gnss_tsync"; | |
533 | }; | |
534 | }; | |
535 | ||
536 | gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 { | |
537 | gn_io_gnsssys_sw_cfg { | |
538 | groups = "gn_io_gnsssys_sw_cfg_grp"; | |
539 | function = "gn_io_gnsssys_sw_cfg"; | |
540 | }; | |
541 | }; | |
542 | ||
543 | gn_trg_pmx0: gn_trg@0 { | |
544 | gn_trg_0 { | |
545 | groups = "gn_trg_grp0"; | |
546 | function = "gn_trg_m0"; | |
547 | }; | |
548 | }; | |
549 | ||
550 | gn_trg_pmx1: gn_trg@1 { | |
551 | gn_trg_1 { | |
552 | groups = "gn_trg_grp1"; | |
553 | function = "gn_trg_m1"; | |
554 | }; | |
555 | }; | |
556 | ||
557 | gn_trg_shutdown_pmx0: gn_trg_shutdown@0 { | |
558 | gn_trg_shutdown_0 { | |
559 | groups = "gn_trg_shutdown_grp0"; | |
560 | function = "gn_trg_shutdown_m0"; | |
561 | }; | |
562 | }; | |
563 | ||
564 | gn_trg_shutdown_pmx1: gn_trg_shutdown@1 { | |
565 | gn_trg_shutdown_1 { | |
566 | groups = "gn_trg_shutdown_grp1"; | |
567 | function = "gn_trg_shutdown_m1"; | |
568 | }; | |
569 | }; | |
570 | ||
571 | gn_trg_shutdown_pmx2: gn_trg_shutdown@2 { | |
572 | gn_trg_shutdown_2 { | |
573 | groups = "gn_trg_shutdown_grp2"; | |
574 | function = "gn_trg_shutdown_m2"; | |
575 | }; | |
576 | }; | |
577 | ||
578 | gn_trg_shutdown_pmx3: gn_trg_shutdown@3 { | |
579 | gn_trg_shutdown_3 { | |
580 | groups = "gn_trg_shutdown_grp3"; | |
581 | function = "gn_trg_shutdown_m3"; | |
582 | }; | |
583 | }; | |
584 | ||
585 | i2c0_pmx: i2c0@0 { | |
586 | i2c0 { | |
587 | groups = "i2c0_grp"; | |
588 | function = "i2c0"; | |
589 | }; | |
590 | }; | |
591 | ||
592 | i2c1_pmx: i2c1@0 { | |
593 | i2c1 { | |
594 | groups = "i2c1_grp"; | |
595 | function = "i2c1"; | |
596 | }; | |
597 | }; | |
598 | ||
599 | jtag_pmx0: jtag@0 { | |
600 | jtag_0 { | |
601 | groups = "jtag_grp0"; | |
602 | function = "jtag_m0"; | |
603 | }; | |
604 | }; | |
605 | ||
606 | ks_kas_spi_pmx0: ks_kas_spi@0 { | |
607 | ks_kas_spi_0 { | |
608 | groups = "ks_kas_spi_grp0"; | |
609 | function = "ks_kas_spi_m0"; | |
610 | }; | |
611 | }; | |
612 | ||
613 | ld_ldd_pmx: ld_ldd@0 { | |
614 | ld_ldd { | |
615 | groups = "ld_ldd_grp"; | |
616 | function = "ld_ldd"; | |
617 | }; | |
618 | }; | |
619 | ||
620 | ld_ldd_16bit_pmx: ld_ldd_16bit@0 { | |
621 | ld_ldd_16bit { | |
622 | groups = "ld_ldd_16bit_grp"; | |
623 | function = "ld_ldd_16bit"; | |
624 | }; | |
625 | }; | |
626 | ||
627 | ld_ldd_fck_pmx: ld_ldd_fck@0 { | |
628 | ld_ldd_fck { | |
629 | groups = "ld_ldd_fck_grp"; | |
630 | function = "ld_ldd_fck"; | |
631 | }; | |
632 | }; | |
633 | ||
634 | ld_ldd_lck_pmx: ld_ldd_lck@0 { | |
635 | ld_ldd_lck { | |
636 | groups = "ld_ldd_lck_grp"; | |
637 | function = "ld_ldd_lck"; | |
638 | }; | |
639 | }; | |
640 | ||
641 | lr_lcdrom_pmx: lr_lcdrom@0 { | |
642 | lr_lcdrom { | |
643 | groups = "lr_lcdrom_grp"; | |
644 | function = "lr_lcdrom"; | |
645 | }; | |
646 | }; | |
647 | ||
648 | lvds_analog_pmx: lvds_analog@0 { | |
649 | lvds_analog { | |
650 | groups = "lvds_analog_grp"; | |
651 | function = "lvds_analog"; | |
652 | }; | |
653 | }; | |
654 | ||
655 | nd_df_pmx: nd_df@0 { | |
656 | nd_df { | |
657 | groups = "nd_df_grp"; | |
658 | function = "nd_df"; | |
659 | }; | |
660 | }; | |
661 | ||
662 | nd_df_nowp_pmx: nd_df_nowp@0 { | |
663 | nd_df_nowp { | |
664 | groups = "nd_df_nowp_grp"; | |
665 | function = "nd_df_nowp"; | |
666 | }; | |
667 | }; | |
668 | ||
669 | ps_pmx: ps@0 { | |
670 | ps { | |
671 | groups = "ps_grp"; | |
672 | function = "ps"; | |
673 | }; | |
674 | }; | |
675 | ||
676 | pwc_core_on_pmx: pwc_core_on@0 { | |
677 | pwc_core_on { | |
678 | groups = "pwc_core_on_grp"; | |
679 | function = "pwc_core_on"; | |
680 | }; | |
681 | }; | |
682 | ||
683 | pwc_ext_on_pmx: pwc_ext_on@0 { | |
684 | pwc_ext_on { | |
685 | groups = "pwc_ext_on_grp"; | |
686 | function = "pwc_ext_on"; | |
687 | }; | |
688 | }; | |
689 | ||
690 | pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 { | |
691 | pwc_gpio3_clk { | |
692 | groups = "pwc_gpio3_clk_grp"; | |
693 | function = "pwc_gpio3_clk"; | |
694 | }; | |
695 | }; | |
696 | ||
697 | pwc_io_on_pmx: pwc_io_on@0 { | |
698 | pwc_io_on { | |
699 | groups = "pwc_io_on_grp"; | |
700 | function = "pwc_io_on"; | |
701 | }; | |
702 | }; | |
703 | ||
704 | pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 { | |
705 | pwc_lowbatt_b_0 { | |
706 | groups = "pwc_lowbatt_b_grp0"; | |
707 | function = "pwc_lowbatt_b_m0"; | |
708 | }; | |
709 | }; | |
710 | ||
711 | pwc_mem_on_pmx: pwc_mem_on@0 { | |
712 | pwc_mem_on { | |
713 | groups = "pwc_mem_on_grp"; | |
714 | function = "pwc_mem_on"; | |
715 | }; | |
716 | }; | |
717 | ||
718 | pwc_on_key_b_pmx0: pwc_on_key_b@0 { | |
719 | pwc_on_key_b_0 { | |
720 | groups = "pwc_on_key_b_grp0"; | |
721 | function = "pwc_on_key_b_m0"; | |
722 | }; | |
723 | }; | |
724 | ||
725 | pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 { | |
726 | pwc_wakeup_src0 { | |
727 | groups = "pwc_wakeup_src0_grp"; | |
728 | function = "pwc_wakeup_src0"; | |
729 | }; | |
730 | }; | |
731 | ||
732 | pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 { | |
733 | pwc_wakeup_src1 { | |
734 | groups = "pwc_wakeup_src1_grp"; | |
735 | function = "pwc_wakeup_src1"; | |
736 | }; | |
737 | }; | |
738 | ||
739 | pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 { | |
740 | pwc_wakeup_src2 { | |
741 | groups = "pwc_wakeup_src2_grp"; | |
742 | function = "pwc_wakeup_src2"; | |
743 | }; | |
744 | }; | |
745 | ||
746 | pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 { | |
747 | pwc_wakeup_src3 { | |
748 | groups = "pwc_wakeup_src3_grp"; | |
749 | function = "pwc_wakeup_src3"; | |
750 | }; | |
751 | }; | |
752 | ||
753 | pw_cko0_pmx0: pw_cko0@0 { | |
754 | pw_cko0_0 { | |
755 | groups = "pw_cko0_grp0"; | |
756 | function = "pw_cko0_m0"; | |
757 | }; | |
758 | }; | |
759 | ||
760 | pw_cko0_pmx1: pw_cko0@1 { | |
761 | pw_cko0_1 { | |
762 | groups = "pw_cko0_grp1"; | |
763 | function = "pw_cko0_m1"; | |
764 | }; | |
765 | }; | |
766 | ||
767 | pw_cko0_pmx2: pw_cko0@2 { | |
768 | pw_cko0_2 { | |
769 | groups = "pw_cko0_grp2"; | |
770 | function = "pw_cko0_m2"; | |
771 | }; | |
772 | }; | |
773 | ||
774 | pw_cko1_pmx0: pw_cko1@0 { | |
775 | pw_cko1_0 { | |
776 | groups = "pw_cko1_grp0"; | |
777 | function = "pw_cko1_m0"; | |
778 | }; | |
779 | }; | |
780 | ||
781 | pw_cko1_pmx1: pw_cko1@1 { | |
782 | pw_cko1_1 { | |
783 | groups = "pw_cko1_grp1"; | |
784 | function = "pw_cko1_m1"; | |
785 | }; | |
786 | }; | |
787 | ||
788 | pw_i2s01_clk_pmx0: pw_i2s01_clk@0 { | |
789 | pw_i2s01_clk_0 { | |
790 | groups = "pw_i2s01_clk_grp0"; | |
791 | function = "pw_i2s01_clk_m0"; | |
792 | }; | |
793 | }; | |
794 | ||
795 | pw_i2s01_clk_pmx1: pw_i2s01_clk@1 { | |
796 | pw_i2s01_clk_1 { | |
797 | groups = "pw_i2s01_clk_grp1"; | |
798 | function = "pw_i2s01_clk_m1"; | |
799 | }; | |
800 | }; | |
801 | ||
802 | pw_pwm0_pmx: pw_pwm0@0 { | |
803 | pw_pwm0 { | |
804 | groups = "pw_pwm0_grp"; | |
805 | function = "pw_pwm0"; | |
806 | }; | |
807 | }; | |
808 | ||
809 | pw_pwm1_pmx: pw_pwm1@0 { | |
810 | pw_pwm1 { | |
811 | groups = "pw_pwm1_grp"; | |
812 | function = "pw_pwm1"; | |
813 | }; | |
814 | }; | |
815 | ||
816 | pw_pwm2_pmx0: pw_pwm2@0 { | |
817 | pw_pwm2_0 { | |
818 | groups = "pw_pwm2_grp0"; | |
819 | function = "pw_pwm2_m0"; | |
820 | }; | |
821 | }; | |
822 | ||
823 | pw_pwm2_pmx1: pw_pwm2@1 { | |
824 | pw_pwm2_1 { | |
825 | groups = "pw_pwm2_grp1"; | |
826 | function = "pw_pwm2_m1"; | |
827 | }; | |
828 | }; | |
829 | ||
830 | pw_pwm3_pmx0: pw_pwm3@0 { | |
831 | pw_pwm3_0 { | |
832 | groups = "pw_pwm3_grp0"; | |
833 | function = "pw_pwm3_m0"; | |
834 | }; | |
835 | }; | |
836 | ||
837 | pw_pwm3_pmx1: pw_pwm3@1 { | |
838 | pw_pwm3_1 { | |
839 | groups = "pw_pwm3_grp1"; | |
840 | function = "pw_pwm3_m1"; | |
841 | }; | |
842 | }; | |
843 | ||
844 | pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 { | |
845 | pw_pwm_cpu_vol_0 { | |
846 | groups = "pw_pwm_cpu_vol_grp0"; | |
847 | function = "pw_pwm_cpu_vol_m0"; | |
848 | }; | |
849 | }; | |
850 | ||
851 | pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 { | |
852 | pw_pwm_cpu_vol_1 { | |
853 | groups = "pw_pwm_cpu_vol_grp1"; | |
854 | function = "pw_pwm_cpu_vol_m1"; | |
855 | }; | |
856 | }; | |
857 | ||
858 | pw_backlight_pmx0: pw_backlight@0 { | |
859 | pw_backlight_0 { | |
860 | groups = "pw_backlight_grp0"; | |
861 | function = "pw_backlight_m0"; | |
862 | }; | |
863 | }; | |
864 | ||
865 | pw_backlight_pmx1: pw_backlight@1 { | |
866 | pw_backlight_1 { | |
867 | groups = "pw_backlight_grp1"; | |
868 | function = "pw_backlight_m1"; | |
869 | }; | |
870 | }; | |
871 | ||
872 | rg_eth_mac_pmx: rg_eth_mac@0 { | |
873 | rg_eth_mac { | |
874 | groups = "rg_eth_mac_grp"; | |
875 | function = "rg_eth_mac"; | |
876 | }; | |
877 | }; | |
878 | ||
879 | rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 { | |
880 | rg_gmac_phy_intr_n { | |
881 | groups = "rg_gmac_phy_intr_n_grp"; | |
882 | function = "rg_gmac_phy_intr_n"; | |
883 | }; | |
884 | }; | |
885 | ||
886 | rg_rgmii_mac_pmx: rg_rgmii_mac@0 { | |
887 | rg_rgmii_mac { | |
888 | groups = "rg_rgmii_mac_grp"; | |
889 | function = "rg_rgmii_mac"; | |
890 | }; | |
891 | }; | |
892 | ||
893 | rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 { | |
894 | rg_rgmii_phy_ref_clk_0 { | |
895 | groups = | |
896 | "rg_rgmii_phy_ref_clk_grp0"; | |
897 | function = | |
898 | "rg_rgmii_phy_ref_clk_m0"; | |
899 | }; | |
900 | }; | |
901 | ||
902 | rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 { | |
903 | rg_rgmii_phy_ref_clk_1 { | |
904 | groups = | |
905 | "rg_rgmii_phy_ref_clk_grp1"; | |
906 | function = | |
907 | "rg_rgmii_phy_ref_clk_m1"; | |
908 | }; | |
909 | }; | |
910 | ||
911 | sd0_pmx: sd0@0 { | |
912 | sd0 { | |
913 | groups = "sd0_grp"; | |
914 | function = "sd0"; | |
915 | }; | |
916 | }; | |
917 | ||
918 | sd0_4bit_pmx: sd0_4bit@0 { | |
919 | sd0_4bit { | |
920 | groups = "sd0_4bit_grp"; | |
921 | function = "sd0_4bit"; | |
922 | }; | |
923 | }; | |
924 | ||
925 | sd1_pmx: sd1@0 { | |
926 | sd1 { | |
927 | groups = "sd1_grp"; | |
928 | function = "sd1"; | |
929 | }; | |
930 | }; | |
931 | ||
932 | sd1_4bit_pmx0: sd1_4bit@0 { | |
933 | sd1_4bit_0 { | |
934 | groups = "sd1_4bit_grp0"; | |
935 | function = "sd1_4bit_m0"; | |
936 | }; | |
937 | }; | |
938 | ||
939 | sd1_4bit_pmx1: sd1_4bit@1 { | |
940 | sd1_4bit_1 { | |
941 | groups = "sd1_4bit_grp1"; | |
942 | function = "sd1_4bit_m1"; | |
943 | }; | |
944 | }; | |
945 | ||
946 | sd2_pmx0: sd2@0 { | |
947 | sd2_0 { | |
948 | groups = "sd2_grp0"; | |
949 | function = "sd2_m0"; | |
950 | }; | |
951 | }; | |
952 | ||
953 | sd2_no_cdb_pmx0: sd2_no_cdb@0 { | |
954 | sd2_no_cdb_0 { | |
955 | groups = "sd2_no_cdb_grp0"; | |
956 | function = "sd2_no_cdb_m0"; | |
957 | }; | |
958 | }; | |
959 | ||
960 | sd3_pmx: sd3@0 { | |
961 | sd3 { | |
962 | groups = "sd3_grp"; | |
963 | function = "sd3"; | |
964 | }; | |
965 | }; | |
966 | ||
967 | sd5_pmx: sd5@0 { | |
968 | sd5 { | |
969 | groups = "sd5_grp"; | |
970 | function = "sd5"; | |
971 | }; | |
972 | }; | |
973 | ||
974 | sd6_pmx0: sd6@0 { | |
975 | sd6_0 { | |
976 | groups = "sd6_grp0"; | |
977 | function = "sd6_m0"; | |
978 | }; | |
979 | }; | |
980 | ||
981 | sd6_pmx1: sd6@1 { | |
982 | sd6_1 { | |
983 | groups = "sd6_grp1"; | |
984 | function = "sd6_m1"; | |
985 | }; | |
986 | }; | |
987 | ||
988 | sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 { | |
989 | sp0_ext_ldo_on { | |
990 | groups = "sp0_ext_ldo_on_grp"; | |
991 | function = "sp0_ext_ldo_on"; | |
992 | }; | |
993 | }; | |
994 | ||
995 | sp0_qspi_pmx: sp0_qspi@0 { | |
996 | sp0_qspi { | |
997 | groups = "sp0_qspi_grp"; | |
998 | function = "sp0_qspi"; | |
999 | }; | |
1000 | }; | |
1001 | ||
1002 | sp1_spi_pmx: sp1_spi@0 { | |
1003 | sp1_spi { | |
1004 | groups = "sp1_spi_grp"; | |
1005 | function = "sp1_spi"; | |
1006 | }; | |
1007 | }; | |
1008 | ||
1009 | tpiu_trace_pmx: tpiu_trace@0 { | |
1010 | tpiu_trace { | |
1011 | groups = "tpiu_trace_grp"; | |
1012 | function = "tpiu_trace"; | |
1013 | }; | |
1014 | }; | |
1015 | ||
1016 | uart0_pmx: uart0@0 { | |
1017 | uart0 { | |
1018 | groups = "uart0_grp"; | |
1019 | function = "uart0"; | |
1020 | }; | |
1021 | }; | |
1022 | ||
1023 | uart0_nopause_pmx: uart0_nopause@0 { | |
1024 | uart0_nopause { | |
1025 | groups = "uart0_nopause_grp"; | |
1026 | function = "uart0_nopause"; | |
1027 | }; | |
1028 | }; | |
1029 | ||
1030 | uart1_pmx: uart1@0 { | |
1031 | uart1 { | |
1032 | groups = "uart1_grp"; | |
1033 | function = "uart1"; | |
1034 | }; | |
1035 | }; | |
1036 | ||
1037 | uart2_pmx: uart2@0 { | |
1038 | uart2 { | |
1039 | groups = "uart2_grp"; | |
1040 | function = "uart2"; | |
1041 | }; | |
1042 | }; | |
1043 | ||
1044 | uart3_pmx0: uart3@0 { | |
1045 | uart3_0 { | |
1046 | groups = "uart3_grp0"; | |
1047 | function = "uart3_m0"; | |
1048 | }; | |
1049 | }; | |
1050 | ||
1051 | uart3_pmx1: uart3@1 { | |
1052 | uart3_1 { | |
1053 | groups = "uart3_grp1"; | |
1054 | function = "uart3_m1"; | |
1055 | }; | |
1056 | }; | |
1057 | ||
1058 | uart3_pmx2: uart3@2 { | |
1059 | uart3_2 { | |
1060 | groups = "uart3_grp2"; | |
1061 | function = "uart3_m2"; | |
1062 | }; | |
1063 | }; | |
1064 | ||
1065 | uart3_pmx3: uart3@3 { | |
1066 | uart3_3 { | |
1067 | groups = "uart3_grp3"; | |
1068 | function = "uart3_m3"; | |
1069 | }; | |
1070 | }; | |
1071 | ||
1072 | uart3_nopause_pmx0: uart3_nopause@0 { | |
1073 | uart3_nopause_0 { | |
1074 | groups = "uart3_nopause_grp0"; | |
1075 | function = "uart3_nopause_m0"; | |
1076 | }; | |
1077 | }; | |
1078 | ||
1079 | uart3_nopause_pmx1: uart3_nopause@1 { | |
1080 | uart3_nopause_1 { | |
1081 | groups = "uart3_nopause_grp1"; | |
1082 | function = "uart3_nopause_m1"; | |
1083 | }; | |
1084 | }; | |
1085 | ||
1086 | uart4_pmx0: uart4@0 { | |
1087 | uart4_0 { | |
1088 | groups = "uart4_grp0"; | |
1089 | function = "uart4_m0"; | |
1090 | }; | |
1091 | }; | |
1092 | ||
1093 | uart4_pmx1: uart4@1 { | |
1094 | uart4_1 { | |
1095 | groups = "uart4_grp1"; | |
1096 | function = "uart4_m1"; | |
1097 | }; | |
1098 | }; | |
1099 | ||
1100 | uart4_pmx2: uart4@2 { | |
1101 | uart4_2 { | |
1102 | groups = "uart4_grp2"; | |
1103 | function = "uart4_m2"; | |
1104 | }; | |
1105 | }; | |
1106 | ||
1107 | uart4_nopause_pmx: uart4_nopause@0 { | |
1108 | uart4_nopause { | |
1109 | groups = "uart4_nopause_grp"; | |
1110 | function = "uart4_nopause"; | |
1111 | }; | |
1112 | }; | |
1113 | ||
1114 | usb0_drvvbus_pmx: usb0_drvvbus@0 { | |
1115 | usb0_drvvbus { | |
1116 | groups = "usb0_drvvbus_grp"; | |
1117 | function = "usb0_drvvbus"; | |
1118 | }; | |
1119 | }; | |
1120 | ||
1121 | usb1_drvvbus_pmx: usb1_drvvbus@0 { | |
1122 | usb1_drvvbus { | |
1123 | groups = "usb1_drvvbus_grp"; | |
1124 | function = "usb1_drvvbus"; | |
1125 | }; | |
1126 | }; | |
1127 | ||
1128 | visbus_dout_pmx: visbus_dout@0 { | |
1129 | visbus_dout { | |
1130 | groups = "visbus_dout_grp"; | |
1131 | function = "visbus_dout"; | |
1132 | }; | |
1133 | }; | |
1134 | ||
1135 | vi_vip1_pmx: vi_vip1@0 { | |
1136 | vi_vip1 { | |
1137 | groups = "vi_vip1_grp"; | |
1138 | function = "vi_vip1"; | |
1139 | }; | |
1140 | }; | |
1141 | ||
1142 | vi_vip1_ext_pmx: vi_vip1_ext@0 { | |
1143 | vi_vip1_ext { | |
1144 | groups = "vi_vip1_ext_grp"; | |
1145 | function = "vi_vip1_ext"; | |
1146 | }; | |
1147 | }; | |
1148 | ||
1149 | vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 { | |
1150 | vi_vip1_low8bit { | |
1151 | groups = "vi_vip1_low8bit_grp"; | |
1152 | function = "vi_vip1_low8bit"; | |
1153 | }; | |
1154 | }; | |
1155 | ||
1156 | vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 { | |
1157 | vi_vip1_high8bit { | |
1158 | groups = "vi_vip1_high8bit_grp"; | |
1159 | function = "vi_vip1_high8bit"; | |
1160 | }; | |
1161 | }; | |
7d76d03b ZS |
1162 | }; |
1163 | ||
1164 | pmipc { | |
1165 | compatible = "arteris, flexnoc", "simple-bus"; | |
1166 | #address-cells = <1>; | |
1167 | #size-cells = <1>; | |
1168 | ranges = <0x13240000 0x13240000 0x00010000>; | |
1169 | pmipc@0x13240000 { | |
1170 | compatible = "sirf,atlas7-pmipc"; | |
1171 | reg = <0x13240000 0x00010000>; | |
1172 | }; | |
1173 | }; | |
1174 | ||
1175 | dramfw { | |
1176 | compatible = "arteris, flexnoc", "simple-bus"; | |
1177 | #address-cells = <1>; | |
1178 | #size-cells = <1>; | |
1179 | ranges = <0x10830000 0x10830000 0x18000>; | |
1180 | dramfw@10820000 { | |
1181 | compatible = "sirf,nocfw-dramfw"; | |
1182 | reg = <0x10830000 0x18000>; | |
1183 | }; | |
1184 | }; | |
1185 | ||
1186 | spramfw { | |
1187 | compatible = "arteris, flexnoc", "simple-bus"; | |
1188 | #address-cells = <1>; | |
1189 | #size-cells = <1>; | |
1190 | ranges = <0x10250000 0x10250000 0x3000>; | |
1191 | spramfw@10820000 { | |
1192 | compatible = "sirf,nocfw-spramfw"; | |
1193 | reg = <0x10250000 0x3000>; | |
1194 | }; | |
1195 | }; | |
1196 | ||
1197 | cpum { | |
1198 | compatible = "arteris, flexnoc", "simple-bus"; | |
1199 | #address-cells = <1>; | |
1200 | #size-cells = <1>; | |
1201 | ranges = <0x10200000 0x10200000 0x3000>; | |
1202 | cpum@10200000 { | |
1203 | compatible = "sirf,nocfw-cpum"; | |
1204 | reg = <0x10200000 0x3000>; | |
1205 | }; | |
1206 | }; | |
1207 | ||
1208 | cgum { | |
1209 | compatible = "arteris, flexnoc", "simple-bus"; | |
1210 | #address-cells = <1>; | |
1211 | #size-cells = <1>; | |
1212 | ranges = <0x18641000 0x18641000 0x3000>, | |
1213 | <0x18620000 0x18620000 0x1000>; | |
1214 | ||
1215 | cgum@18641000 { | |
1216 | compatible = "sirf,nocfw-cgum"; | |
1217 | reg = <0x18641000 0x3000>; | |
1218 | }; | |
1219 | ||
1220 | car: clock-controller@18620000 { | |
1221 | compatible = "sirf,atlas7-car"; | |
1222 | reg = <0x18620000 0x1000>; | |
1223 | #clock-cells = <1>; | |
1224 | #reset-cells = <1>; | |
1225 | }; | |
1226 | }; | |
1227 | ||
1228 | gnssm { | |
1229 | compatible = "arteris, flexnoc", "simple-bus"; | |
1230 | #address-cells = <1>; | |
1231 | #size-cells = <1>; | |
1232 | ranges = <0x18000000 0x18000000 0x0000ffff>, | |
1233 | <0x18010000 0x18010000 0x1000>, | |
1234 | <0x18020000 0x18020000 0x1000>, | |
1235 | <0x18030000 0x18030000 0x1000>, | |
1236 | <0x18040000 0x18040000 0x1000>, | |
1237 | <0x18050000 0x18050000 0x1000>, | |
1238 | <0x18060000 0x18060000 0x1000>, | |
1239 | <0x18100000 0x18100000 0x3000>, | |
1240 | <0x18250000 0x18250000 0x10000>, | |
1241 | <0x18200000 0x18200000 0x1000>; | |
1242 | ||
1243 | dmac0: dma-controller@18000000 { | |
1244 | cell-index = <0>; | |
1245 | compatible = "sirf,atlas7-dmac"; | |
1246 | reg = <0x18000000 0x1000>; | |
1247 | interrupts = <0 12 0>; | |
1248 | clocks = <&car 89>; | |
1249 | dma-channels = <16>; | |
1250 | #dma-cells = <1>; | |
1251 | }; | |
1252 | ||
1253 | gnssmfw@0x18100000 { | |
1254 | compatible = "sirf,nocfw-gnssm"; | |
1255 | reg = <0x18100000 0x3000>; | |
1256 | }; | |
1257 | ||
1258 | uart0: uart@18010000 { | |
1259 | cell-index = <0>; | |
1260 | compatible = "sirf,atlas7-uart"; | |
1261 | reg = <0x18010000 0x1000>; | |
1262 | interrupts = <0 17 0>; | |
1263 | clocks = <&car 90>; | |
1264 | fifosize = <128>; | |
1265 | dmas = <&dmac0 3>, <&dmac0 2>; | |
1266 | dma-names = "rx", "tx"; | |
1267 | }; | |
1268 | ||
1269 | uart1: uart@18020000 { | |
1270 | cell-index = <1>; | |
1271 | compatible = "sirf,atlas7-uart"; | |
1272 | reg = <0x18020000 0x1000>; | |
1273 | interrupts = <0 18 0>; | |
1274 | clocks = <&car 88>; | |
1275 | fifosize = <32>; | |
1276 | }; | |
1277 | ||
1278 | uart2: uart@18030000 { | |
1279 | cell-index = <2>; | |
1280 | compatible = "sirf,atlas7-uart"; | |
1281 | reg = <0x18030000 0x1000>; | |
1282 | interrupts = <0 19 0>; | |
1283 | clocks = <&car 91>; | |
1284 | fifosize = <128>; | |
1285 | dmas = <&dmac0 6>, <&dmac0 7>; | |
1286 | dma-names = "rx", "tx"; | |
1287 | status = "disabled"; | |
1288 | }; | |
1289 | uart3: uart@18040000 { | |
1290 | cell-index = <3>; | |
1291 | compatible = "sirf,atlas7-uart"; | |
1292 | reg = <0x18040000 0x1000>; | |
1293 | interrupts = <0 66 0>; | |
1294 | clocks = <&car 92>; | |
1295 | fifosize = <128>; | |
1296 | dmas = <&dmac0 4>, <&dmac0 5>; | |
1297 | dma-names = "rx", "tx"; | |
1298 | status = "disabled"; | |
1299 | }; | |
1300 | uart4: uart@18050000 { | |
1301 | cell-index = <4>; | |
1302 | compatible = "sirf,atlas7-uart"; | |
1303 | reg = <0x18050000 0x1000>; | |
1304 | interrupts = <0 69 0>; | |
1305 | clocks = <&car 93>; | |
1306 | fifosize = <128>; | |
1307 | dmas = <&dmac0 0>, <&dmac0 1>; | |
1308 | dma-names = "rx", "tx"; | |
1309 | status = "disabled"; | |
1310 | }; | |
1311 | uart5: uart@18060000 { | |
1312 | cell-index = <5>; | |
1313 | compatible = "sirf,atlas7-uart"; | |
1314 | reg = <0x18060000 0x1000>; | |
1315 | interrupts = <0 71 0>; | |
1316 | clocks = <&car 94>; | |
1317 | fifosize = <128>; | |
1318 | dmas = <&dmac0 8>, <&dmac0 9>; | |
1319 | dma-names = "rx", "tx"; | |
1320 | status = "disabled"; | |
1321 | }; | |
1322 | dspub@18250000 { | |
1323 | compatible = "dx,cc44p"; | |
1324 | reg = <0x18250000 0x10000>; | |
1325 | interrupts = <0 27 0>; | |
1326 | }; | |
1327 | ||
1328 | spi1: spi@18200000 { | |
1329 | compatible = "sirf,prima2-spi"; | |
1330 | reg = <0x18200000 0x1000>; | |
1331 | interrupts = <0 16 0>; | |
1332 | clocks = <&car 95>; | |
1333 | #address-cells = <1>; | |
1334 | #size-cells = <0>; | |
1335 | dmas = <&dmac0 12>, <&dmac0 13>; | |
1336 | dma-names = "rx", "tx"; | |
1337 | status = "disabled"; | |
1338 | }; | |
1339 | }; | |
1340 | ||
1341 | ||
1342 | gpum { | |
1343 | compatible = "arteris, flexnoc", "simple-bus"; | |
1344 | #address-cells = <1>; | |
1345 | #size-cells = <1>; | |
1346 | ranges = <0x13000000 0x13000000 0x3000>; | |
1347 | gpum@0x13000000 { | |
1348 | compatible = "sirf,nocfw-gpum"; | |
1349 | reg = <0x13000000 0x3000>; | |
1350 | }; | |
1351 | }; | |
1352 | ||
1353 | mediam { | |
1354 | compatible = "arteris, flexnoc", "simple-bus"; | |
1355 | #address-cells = <1>; | |
1356 | #size-cells = <1>; | |
1357 | ranges = <0x16000000 0x16000000 0x00200000>, | |
81a85f9e | 1358 | <0x17000000 0x17000000 0x10000>, |
7d76d03b ZS |
1359 | <0x17020000 0x17020000 0x1000>, |
1360 | <0x17030000 0x17030000 0x1000>, | |
1361 | <0x17040000 0x17040000 0x1000>, | |
1362 | <0x17050000 0x17050000 0x10000>, | |
1363 | <0x17060000 0x17060000 0x200>, | |
1364 | <0x17060200 0x17060200 0x100>, | |
1365 | <0x17070000 0x17070000 0x200>, | |
1366 | <0x17070200 0x17070200 0x100>, | |
1367 | <0x170A0000 0x170A0000 0x3000>; | |
1368 | ||
1369 | mediam@170A0000 { | |
1370 | compatible = "sirf,nocfw-mediam"; | |
1371 | reg = <0x170A0000 0x3000>; | |
1372 | }; | |
1373 | ||
1374 | gpio_0: gpio_mediam@17040000 { | |
1375 | #gpio-cells = <2>; | |
1376 | #interrupt-cells = <2>; | |
1377 | compatible = "sirf,atlas7-gpio"; | |
1378 | reg = <0x17040000 0x1000>; | |
1379 | interrupts = <0 13 0>, <0 14 0>; | |
1380 | clocks = <&car 107>; | |
1381 | clock-names = "gpio0_io"; | |
1382 | gpio-controller; | |
1383 | interrupt-controller; | |
27b0d37e WC |
1384 | |
1385 | gpio-banks = <2>; | |
1386 | gpio-ranges = <&pinctrl 0 0 0>, | |
1387 | <&pinctrl 32 0 0>; | |
1388 | gpio-ranges-group-names = "lvds_gpio_grp", | |
1389 | "uart_nand_gpio_grp"; | |
7d76d03b ZS |
1390 | }; |
1391 | ||
1392 | nand@17050000 { | |
1393 | compatible = "sirf,atlas7-nand"; | |
1394 | reg = <0x17050000 0x10000>; | |
1395 | interrupts = <0 41 0>; | |
1396 | clocks = <&car 108>, <&car 112>; | |
1397 | clock-names = "nand_io", "nand_nand"; | |
1398 | }; | |
1399 | ||
1400 | sd0: sdhci@16000000 { | |
1401 | cell-index = <0>; | |
1402 | compatible = "sirf,atlas7-sdhc"; | |
1403 | reg = <0x16000000 0x100000>; | |
1404 | interrupts = <0 38 0>; | |
1405 | clocks = <&car 109>, <&car 111>; | |
1406 | clock-names = "core", "iface"; | |
1407 | wp-inverted; | |
1408 | non-removable; | |
1409 | status = "disabled"; | |
1410 | bus-width = <8>; | |
1411 | }; | |
1412 | ||
1413 | sd1: sdhci@16100000 { | |
1414 | cell-index = <1>; | |
1415 | compatible = "sirf,atlas7-sdhc"; | |
1416 | reg = <0x16100000 0x100000>; | |
1417 | interrupts = <0 38 0>; | |
1418 | clocks = <&car 109>, <&car 111>; | |
1419 | clock-names = "core", "iface"; | |
1420 | non-removable; | |
1421 | status = "disabled"; | |
1422 | bus-width = <8>; | |
1423 | }; | |
1424 | ||
81a85f9e LL |
1425 | jpeg@17000000 { |
1426 | compatible = "sirf,atlas7-jpeg"; | |
1427 | reg = <0x17000000 0x10000>; | |
1428 | interrupts = <0 72 0>, | |
1429 | <0 73 0>; | |
1430 | clocks = <&car 103>; | |
1431 | }; | |
1432 | ||
7d76d03b ZS |
1433 | usb0: usb@17060000 { |
1434 | cell-index = <0>; | |
1435 | compatible = "sirf,atlas7-usb"; | |
1436 | reg = <0x17060000 0x200>; | |
1437 | interrupts = <0 10 0>; | |
1438 | clocks = <&car 113>; | |
1439 | sirf,usbphy = <&usbphy0>; | |
1440 | phy_type = "utmi"; | |
1441 | dr_mode = "otg"; | |
1442 | maximum-speed = "high-speed"; | |
1443 | status = "okay"; | |
1444 | }; | |
1445 | ||
1446 | usb1: usb@17070000 { | |
1447 | cell-index = <1>; | |
1448 | compatible = "sirf,atlas7-usb"; | |
1449 | reg = <0x17070000 0x200>; | |
1450 | interrupts = <0 11 0>; | |
1451 | clocks = <&car 114>; | |
1452 | sirf,usbphy = <&usbphy1>; | |
1453 | phy_type = "utmi"; | |
1454 | dr_mode = "host"; | |
1455 | maximum-speed = "high-speed"; | |
1456 | status = "okay"; | |
1457 | }; | |
1458 | ||
1459 | usbphy0: usbphy@0 { | |
1460 | compatible = "sirf,atlas7-usbphy"; | |
1461 | reg = <0x17060200 0x100>; | |
1462 | clocks = <&car 115>; | |
1463 | status = "okay"; | |
1464 | }; | |
1465 | ||
1466 | usbphy1: usbphy@1 { | |
1467 | compatible = "sirf,atlas7-usbphy"; | |
1468 | reg = <0x17070200 0x100>; | |
1469 | clocks = <&car 116>; | |
1470 | status = "okay"; | |
1471 | }; | |
1472 | ||
1473 | i2c0: i2c@17020000 { | |
1474 | cell-index = <0>; | |
1475 | compatible = "sirf,prima2-i2c"; | |
1476 | reg = <0x17020000 0x1000>; | |
1477 | interrupts = <0 24 0>; | |
1478 | clocks = <&car 105>; | |
1479 | #address-cells = <1>; | |
1480 | #size-cells = <0>; | |
1481 | }; | |
1482 | ||
1483 | }; | |
1484 | ||
1485 | vdifm { | |
1486 | compatible = "arteris, flexnoc", "simple-bus"; | |
1487 | #address-cells = <1>; | |
1488 | #size-cells = <1>; | |
1489 | ranges = <0x13290000 0x13290000 0x3000>, | |
1490 | <0x13300000 0x13300000 0x1000>, | |
1491 | <0x14200000 0x14200000 0x600000>; | |
1492 | ||
1493 | vdifm@13290000 { | |
1494 | compatible = "sirf,nocfw-vdifm"; | |
1495 | reg = <0x13290000 0x3000>; | |
1496 | }; | |
1497 | ||
1498 | gpio_1: gpio_vdifm@13300000 { | |
1499 | #gpio-cells = <2>; | |
1500 | #interrupt-cells = <2>; | |
1501 | compatible = "sirf,atlas7-gpio"; | |
1502 | reg = <0x13300000 0x1000>; | |
27b0d37e WC |
1503 | interrupts = <0 43 0>, <0 44 0>, |
1504 | <0 45 0>, <0 46 0>; | |
7d76d03b ZS |
1505 | clocks = <&car 84>; |
1506 | clock-names = "gpio1_io"; | |
1507 | gpio-controller; | |
1508 | interrupt-controller; | |
27b0d37e WC |
1509 | |
1510 | gpio-banks = <4>; | |
1511 | gpio-ranges = <&pinctrl 0 0 0>, | |
1512 | <&pinctrl 32 0 0>, | |
1513 | <&pinctrl 64 0 0>, | |
1514 | <&pinctrl 96 0 0>; | |
1515 | gpio-ranges-group-names = "gnss_gpio_grp", | |
1516 | "lcd_vip_gpio_grp", | |
1517 | "sdio_i2s_gpio_grp", | |
1518 | "sp_rgmii_gpio_grp"; | |
7d76d03b ZS |
1519 | }; |
1520 | ||
1521 | sd2: sdhci@14200000 { | |
1522 | cell-index = <2>; | |
1523 | compatible = "sirf,atlas7-sdhc"; | |
1524 | reg = <0x14200000 0x100000>; | |
1525 | interrupts = <0 23 0>; | |
1526 | clocks = <&car 70>, <&car 75>; | |
1527 | clock-names = "core", "iface"; | |
1528 | status = "disabled"; | |
1529 | bus-width = <4>; | |
1530 | sd-uhs-sdr50; | |
1531 | vqmmc-supply = <&vqmmc>; | |
1532 | vqmmc: vqmmc@2 { | |
1533 | regulator-min-microvolt = <1650000>; | |
1534 | regulator-max-microvolt = <1950000>; | |
1535 | regulator-name = "vqmmc-ldo"; | |
1536 | regulator-type = "voltage"; | |
1537 | regulator-boot-on; | |
1538 | regulator-allow-bypass; | |
1539 | }; | |
1540 | }; | |
1541 | ||
1542 | sd3: sdhci@14300000 { | |
1543 | cell-index = <3>; | |
1544 | compatible = "sirf,atlas7-sdhc"; | |
1545 | reg = <0x14300000 0x100000>; | |
1546 | interrupts = <0 23 0>; | |
1547 | clocks = <&car 76>, <&car 81>; | |
1548 | clock-names = "core", "iface"; | |
1549 | status = "disabled"; | |
1550 | bus-width = <4>; | |
1551 | }; | |
1552 | ||
1553 | sd5: sdhci@14500000 { | |
1554 | cell-index = <5>; | |
1555 | compatible = "sirf,atlas7-sdhc"; | |
1556 | reg = <0x14500000 0x100000>; | |
1557 | interrupts = <0 39 0>; | |
1558 | clocks = <&car 71>, <&car 76>; | |
1559 | clock-names = "core", "iface"; | |
1560 | status = "disabled"; | |
1561 | bus-width = <4>; | |
1562 | loop-dma; | |
1563 | }; | |
1564 | ||
1565 | sd6: sdhci@14600000 { | |
1566 | cell-index = <6>; | |
1567 | compatible = "sirf,atlas7-sdhc"; | |
1568 | reg = <0x14600000 0x100000>; | |
1569 | interrupts = <0 98 0>; | |
1570 | clocks = <&car 72>, <&car 77>; | |
1571 | clock-names = "core", "iface"; | |
1572 | status = "disabled"; | |
1573 | bus-width = <4>; | |
1574 | }; | |
1575 | ||
1576 | sd7: sdhci@14700000 { | |
1577 | cell-index = <7>; | |
1578 | compatible = "sirf,atlas7-sdhc"; | |
1579 | reg = <0x14700000 0x100000>; | |
1580 | interrupts = <0 98 0>; | |
1581 | clocks = <&car 72>, <&car 77>; | |
1582 | clock-names = "core", "iface"; | |
1583 | status = "disabled"; | |
1584 | bus-width = <4>; | |
1585 | }; | |
1586 | }; | |
1587 | ||
1588 | audiom { | |
1589 | compatible = "arteris, flexnoc", "simple-bus"; | |
1590 | #address-cells = <1>; | |
1591 | #size-cells = <1>; | |
1592 | ranges = <0x10d50000 0x10d50000 0x0000ffff>, | |
1593 | <0x10d60000 0x10d60000 0x0000ffff>, | |
1594 | <0x10d80000 0x10d80000 0x0000ffff>, | |
1595 | <0x10d90000 0x10d90000 0x0000ffff>, | |
1596 | <0x10ED0000 0x10ED0000 0x3000>, | |
1597 | <0x10dc8000 0x10dc8000 0x1000>, | |
1598 | <0x10dc0000 0x10dc0000 0x1000>, | |
1599 | <0x10db0000 0x10db0000 0x4000>, | |
1600 | <0x10d40000 0x10d40000 0x1000>, | |
1601 | <0x10d30000 0x10d30000 0x1000>; | |
1602 | ||
1603 | timer@10dc0000 { | |
1604 | compatible = "sirf,atlas7-tick"; | |
1605 | reg = <0x10dc0000 0x1000>; | |
1606 | interrupts = <0 0 0>, | |
1607 | <0 1 0>, | |
1608 | <0 2 0>, | |
1609 | <0 49 0>, | |
1610 | <0 50 0>, | |
1611 | <0 51 0>; | |
1612 | clocks = <&car 47>; | |
1613 | }; | |
1614 | ||
1615 | timerb@10dc8000 { | |
1616 | compatible = "sirf,atlas7-tick"; | |
1617 | reg = <0x10dc8000 0x1000>; | |
1618 | interrupts = <0 74 0>, | |
1619 | <0 75 0>, | |
1620 | <0 76 0>, | |
1621 | <0 77 0>, | |
1622 | <0 78 0>, | |
1623 | <0 79 0>; | |
1624 | clocks = <&car 47>; | |
1625 | }; | |
1626 | ||
1627 | vip0@10db0000 { | |
1628 | compatible = "sirf,atlas7-vip0"; | |
1629 | reg = <0x10db0000 0x2000>; | |
1630 | interrupts = <0 85 0>; | |
1631 | sirf,vip_cma_size = <0xC00000>; | |
1632 | }; | |
1633 | ||
1634 | cvd@10db2000 { | |
1635 | compatible = "sirf,cvd"; | |
1636 | reg = <0x10db2000 0x2000>; | |
1637 | clocks = <&car 46>; | |
1638 | }; | |
1639 | ||
1640 | dmac2: dma-controller@10d50000 { | |
1641 | cell-index = <2>; | |
1642 | compatible = "sirf,atlas7-dmac"; | |
1643 | reg = <0x10d50000 0xffff>; | |
1644 | interrupts = <0 55 0>; | |
1645 | clocks = <&car 60>; | |
1646 | dma-channels = <16>; | |
1647 | #dma-cells = <1>; | |
1648 | }; | |
1649 | ||
1650 | dmac3: dma-controller@10d60000 { | |
1651 | cell-index = <3>; | |
1652 | compatible = "sirf,atlas7-dmac"; | |
1653 | reg = <0x10d60000 0xffff>; | |
1654 | interrupts = <0 56 0>; | |
1655 | clocks = <&car 61>; | |
1656 | dma-channels = <16>; | |
1657 | #dma-cells = <1>; | |
1658 | }; | |
1659 | ||
1660 | adc: adc@10d80000 { | |
1661 | compatible = "sirf,atlas7-adc"; | |
1662 | reg = <0x10d80000 0xffff>; | |
1663 | interrupts = <0 34 0>; | |
1664 | clocks = <&car 49>; | |
1665 | #io-channel-cells = <1>; | |
1666 | }; | |
1667 | ||
1668 | pulsec@10d90000 { | |
1669 | compatible = "sirf,prima2-pulsec"; | |
1670 | reg = <0x10d90000 0xffff>; | |
1671 | interrupts = <0 42 0>; | |
1672 | clocks = <&car 54>; | |
1673 | }; | |
1674 | ||
1675 | audiom@10ED0000 { | |
1676 | compatible = "sirf,nocfw-audiom"; | |
1677 | reg = <0x10ED0000 0x3000>; | |
1678 | interrupts = <0 102 0>; | |
1679 | }; | |
1680 | ||
1681 | usp1: usp@10d30000 { | |
1682 | cell-index = <1>; | |
1683 | reg = <0x10d30000 0x1000>; | |
1684 | fifosize = <512>; | |
1685 | clocks = <&car 58>; | |
1686 | dmas = <&dmac2 6>, <&dmac2 7>; | |
1687 | dma-names = "rx", "tx"; | |
1688 | }; | |
1689 | ||
1690 | usp2: usp@10d40000 { | |
1691 | cell-index = <2>; | |
1692 | reg = <0x10d40000 0x1000>; | |
1693 | interrupts = <0 22 0>; | |
1694 | clocks = <&car 59>; | |
1695 | dmas = <&dmac2 12>, <&dmac2 13>; | |
1696 | dma-names = "rx", "tx"; | |
1697 | #address-cells = <1>; | |
1698 | #size-cells = <0>; | |
1699 | status = "disabled"; | |
1700 | }; | |
1701 | }; | |
1702 | ||
1703 | ddrm { | |
1704 | compatible = "arteris, flexnoc", "simple-bus"; | |
1705 | #address-cells = <1>; | |
1706 | #size-cells = <1>; | |
1707 | ranges = <0x10820000 0x10820000 0x3000>, | |
1708 | <0x10800000 0x10800000 0x2000>; | |
1709 | ddrm@10820000 { | |
1710 | compatible = "sirf,nocfw-ddrm"; | |
1711 | reg = <0x10820000 0x3000>; | |
1712 | interrupts = <0 105 0>; | |
1713 | }; | |
1714 | ||
1715 | memory-controller@0x10800000 { | |
1716 | compatible = "sirf,atlas7-memc"; | |
1717 | reg = <0x10800000 0x2000>; | |
1718 | }; | |
1719 | ||
1720 | }; | |
1721 | ||
1722 | btm { | |
1723 | compatible = "arteris, flexnoc", "simple-bus"; | |
1724 | #address-cells = <1>; | |
1725 | #size-cells = <1>; | |
1726 | ranges = <0x11002000 0x11002000 0x0000ffff>, | |
1727 | <0x11010000 0x11010000 0x3000>, | |
1728 | <0x11000000 0x11000000 0x1000>, | |
1729 | <0x11001000 0x11001000 0x1000>; | |
1730 | ||
1731 | dmac4: dma-controller@11002000 { | |
1732 | cell-index = <4>; | |
1733 | compatible = "sirf,atlas7-dmac"; | |
1734 | reg = <0x11002000 0x1000>; | |
1735 | interrupts = <0 99 0>; | |
1736 | clocks = <&car 130>; | |
1737 | dma-channels = <16>; | |
1738 | #dma-cells = <1>; | |
1739 | }; | |
1740 | uart6: uart@11000000 { | |
1741 | cell-index = <6>; | |
1742 | compatible = "sirf,atlas7-bt-uart", | |
1743 | "sirf,atlas7-uart"; | |
1744 | reg = <0x11000000 0x1000>; | |
1745 | interrupts = <0 100 0>; | |
1746 | clocks = <&car 131>, <&car 133>, <&car 134>; | |
1747 | clock-names = "uart", "general", "noc"; | |
1748 | fifosize = <128>; | |
1749 | dmas = <&dmac4 12>, <&dmac4 13>; | |
1750 | dma-names = "rx", "tx"; | |
1751 | status = "disabled"; | |
1752 | }; | |
1753 | ||
1754 | usp3: usp@11001000 { | |
1755 | compatible = "sirf,atlas7-bt-usp", | |
1756 | "sirf,prima2-usp-pcm"; | |
1757 | cell-index = <3>; | |
1758 | reg = <0x11001000 0x1000>; | |
1759 | fifosize = <512>; | |
1760 | clocks = <&car 132>, <&car 129>, <&car 133>, | |
1761 | <&car 134>, <&car 135>; | |
1762 | clock-names = "usp3_io", "a7ca_btss", "a7ca_io", | |
1763 | "noc_btm_io", "thbtm_io"; | |
1764 | dmas = <&dmac4 0>, <&dmac4 1>; | |
1765 | dma-names = "rx", "tx"; | |
1766 | }; | |
1767 | ||
1768 | btm@11010000 { | |
1769 | compatible = "sirf,nocfw-btm"; | |
1770 | reg = <0x11010000 0x3000>; | |
1771 | }; | |
1772 | }; | |
1773 | ||
1774 | rtcm { | |
1775 | compatible = "arteris, flexnoc", "simple-bus"; | |
1776 | #address-cells = <1>; | |
1777 | #size-cells = <1>; | |
1778 | ranges = <0x18810000 0x18810000 0x3000>, | |
1779 | <0x18840000 0x18840000 0x1000>, | |
1780 | <0x18890000 0x18890000 0x1000>, | |
1781 | <0x188B0000 0x188B0000 0x10000>, | |
1782 | <0x188D0000 0x188D0000 0x1000>; | |
1783 | rtcm@18810000 { | |
1784 | compatible = "sirf,nocfw-rtcm"; | |
1785 | reg = <0x18810000 0x3000>; | |
1786 | interrupts = <0 109 0>; | |
1787 | }; | |
1788 | ||
1789 | gpio_2: gpio_rtcm@18890000 { | |
1790 | #gpio-cells = <2>; | |
1791 | #interrupt-cells = <2>; | |
1792 | compatible = "sirf,atlas7-gpio"; | |
1793 | reg = <0x18890000 0x1000>; | |
1794 | interrupts = <0 47 0>; | |
1795 | gpio-controller; | |
1796 | interrupt-controller; | |
27b0d37e WC |
1797 | |
1798 | gpio-banks = <1>; | |
1799 | gpio-ranges = <&pinctrl 0 0 0>; | |
1800 | gpio-ranges-group-names = "rtc_gpio_grp"; | |
7d76d03b ZS |
1801 | }; |
1802 | ||
1803 | rtc-iobg@18840000 { | |
1804 | compatible = "sirf,prima2-rtciobg", | |
1805 | "sirf-prima2-rtciobg-bus", | |
1806 | "simple-bus"; | |
1807 | #address-cells = <1>; | |
1808 | #size-cells = <1>; | |
1809 | reg = <0x18840000 0x1000>; | |
1810 | ||
1811 | sysrtc@2000 { | |
1812 | compatible = "sirf,prima2-sysrtc"; | |
1813 | reg = <0x2000 0x100>; | |
1814 | interrupts = <0 52 0>; | |
1815 | }; | |
1816 | pwrc@3000 { | |
1817 | compatible = "sirf,atlas7-pwrc"; | |
1818 | reg = <0x3000 0x100>; | |
1819 | }; | |
1820 | }; | |
1821 | ||
1822 | qspi: flash@188B0000 { | |
1823 | cell-index = <0>; | |
1824 | compatible = "sirf,atlas7-qspi-nor"; | |
1825 | reg = <0x188B0000 0x10000>; | |
1826 | interrupts = <0 15 0>; | |
1827 | #address-cells = <1>; | |
1828 | #size-cells = <0>; | |
1829 | }; | |
1830 | ||
1831 | retain@0x188D0000 { | |
1832 | compatible = "sirf,atlas7-retain"; | |
1833 | reg = <0x188D0000 0x1000>; | |
1834 | }; | |
1835 | ||
1836 | }; | |
1837 | disp-iobg { | |
1838 | /* lcdc0 */ | |
1839 | compatible = "simple-bus"; | |
1840 | #address-cells = <1>; | |
1841 | #size-cells = <1>; | |
1842 | ranges = <0x13100000 0x13100000 0x20000>, | |
1843 | <0x10e10000 0x10e10000 0x10000>; | |
1844 | ||
1845 | lcd@13100000 { | |
1846 | compatible = "sirf,atlas7-lcdc"; | |
1847 | reg = <0x13100000 0x10000>; | |
1848 | interrupts = <0 30 0>; | |
1849 | clocks = <&car 79>; | |
1850 | }; | |
1851 | vpp@13110000 { | |
1852 | compatible = "sirf,atlas7-vpp"; | |
1853 | reg = <0x13110000 0x10000>; | |
1854 | interrupts = <0 31 0>; | |
1855 | clocks = <&car 78>; | |
1856 | resets = <&car 29>; | |
1857 | }; | |
1858 | lvds@10e10000 { | |
1859 | compatible = "sirf,atlas7-lvdsc"; | |
1860 | reg = <0x10e10000 0x10000>; | |
1861 | interrupts = <0 64 0>; | |
1862 | clocks = <&car 54>; | |
1863 | resets = <&car 29>; | |
1864 | }; | |
1865 | ||
1866 | }; | |
1867 | ||
1868 | graphics-iobg { | |
1869 | compatible = "simple-bus"; | |
1870 | #address-cells = <1>; | |
1871 | #size-cells = <1>; | |
1872 | ranges = <0x12000000 0x12000000 0x1000000>; | |
1873 | ||
1874 | graphics@12000000 { | |
1875 | compatible = "powervr,sgx531"; | |
1876 | reg = <0x12000000 0x1000000>; | |
1877 | interrupts = <0 6 0>; | |
1878 | clocks = <&car 126>; | |
1879 | }; | |
1880 | }; | |
1881 | }; | |
1882 | }; |