projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 467f1cf5 NF |
1 | /* |
| 2 | * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC | |
| 3 | * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, | |
| 4 | * AT91SAM9X25, AT91SAM9X35 SoC | |
| 5 | * | |
| 6 | * Copyright (C) 2012 Atmel, | |
| 7 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | |
| 8 | * | |
| 9 | * Licensed under GPLv2 or later. | |
| 10 | */ | |
| 11 | ||
| 6db64d29 | 12 | #include "skeleton.dtsi" |
| 92f8629b | 13 | #include <dt-bindings/gpio/gpio.h> |
| 467f1cf5 NF |
14 | |
| 15 | / { | |
| 16 | model = "Atmel AT91SAM9x5 family SoC"; | |
| 17 | compatible = "atmel,at91sam9x5"; | |
| 18 | interrupt-parent = <&aic>; | |
| 19 | ||
| 20 | aliases { | |
| 21 | serial0 = &dbgu; | |
| 22 | serial1 = &usart0; | |
| 23 | serial2 = &usart1; | |
| 24 | serial3 = &usart2; | |
| 25 | gpio0 = &pioA; | |
| 26 | gpio1 = &pioB; | |
| 27 | gpio2 = &pioC; | |
| 28 | gpio3 = &pioD; | |
| 29 | tcb0 = &tcb0; | |
| 30 | tcb1 = &tcb1; | |
| 05dcd361 LD |
31 | i2c0 = &i2c0; |
| 32 | i2c1 = &i2c1; | |
| 33 | i2c2 = &i2c2; | |
| 099343c6 | 34 | ssc0 = &ssc0; |
| 467f1cf5 NF |
35 | }; |
| 36 | cpus { | |
| 37 | cpu@0 { | |
| 38 | compatible = "arm,arm926ejs"; | |
| 39 | }; | |
| 40 | }; | |
| 41 | ||
| dcce6ce8 | 42 | memory { |
| 467f1cf5 NF |
43 | reg = <0x20000000 0x10000000>; |
| 44 | }; | |
| 45 | ||
| 46 | ahb { | |
| 47 | compatible = "simple-bus"; | |
| 48 | #address-cells = <1>; | |
| 49 | #size-cells = <1>; | |
| 50 | ranges; | |
| 51 | ||
| 52 | apb { | |
| 53 | compatible = "simple-bus"; | |
| 54 | #address-cells = <1>; | |
| 55 | #size-cells = <1>; | |
| 56 | ranges; | |
| 57 | ||
| 58 | aic: interrupt-controller@fffff000 { | |
| f8a073ee | 59 | #interrupt-cells = <3>; |
| 467f1cf5 NF |
60 | compatible = "atmel,at91rm9200-aic"; |
| 61 | interrupt-controller; | |
| 467f1cf5 | 62 | reg = <0xfffff000 0x200>; |
| c6573943 | 63 | atmel,external-irqs = <31>; |
| 467f1cf5 NF |
64 | }; |
| 65 | ||
| a7776ec6 JCPV |
66 | ramc0: ramc@ffffe800 { |
| 67 | compatible = "atmel,at91sam9g45-ddramc"; | |
| 68 | reg = <0xffffe800 0x200>; | |
| 69 | }; | |
| 70 | ||
| eb5e76ff JCPV |
71 | pmc: pmc@fffffc00 { |
| 72 | compatible = "atmel,at91rm9200-pmc"; | |
| 73 | reg = <0xfffffc00 0x100>; | |
| 74 | }; | |
| 75 | ||
| c8082d34 JCPV |
76 | rstc@fffffe00 { |
| 77 | compatible = "atmel,at91sam9g45-rstc"; | |
| 78 | reg = <0xfffffe00 0x10>; | |
| 79 | }; | |
| 80 | ||
| 82015c4e JCPV |
81 | shdwc@fffffe10 { |
| 82 | compatible = "atmel,at91sam9x5-shdwc"; | |
| 83 | reg = <0xfffffe10 0x10>; | |
| 84 | }; | |
| 85 | ||
| 467f1cf5 NF |
86 | pit: timer@fffffe30 { |
| 87 | compatible = "atmel,at91sam9260-pit"; | |
| 88 | reg = <0xfffffe30 0xf>; | |
| f8a073ee | 89 | interrupts = <1 4 7>; |
| 467f1cf5 NF |
90 | }; |
| 91 | ||
| 92 | tcb0: timer@f8008000 { | |
| 93 | compatible = "atmel,at91sam9x5-tcb"; | |
| 94 | reg = <0xf8008000 0x100>; | |
| f8a073ee | 95 | interrupts = <17 4 0>; |
| 467f1cf5 NF |
96 | }; |
| 97 | ||
| 98 | tcb1: timer@f800c000 { | |
| 99 | compatible = "atmel,at91sam9x5-tcb"; | |
| 100 | reg = <0xf800c000 0x100>; | |
| f8a073ee | 101 | interrupts = <17 4 0>; |
| 467f1cf5 NF |
102 | }; |
| 103 | ||
| 104 | dma0: dma-controller@ffffec00 { | |
| 105 | compatible = "atmel,at91sam9g45-dma"; | |
| 106 | reg = <0xffffec00 0x200>; | |
| f8a073ee | 107 | interrupts = <20 4 0>; |
| 980ce7d9 | 108 | #dma-cells = <2>; |
| 467f1cf5 NF |
109 | }; |
| 110 | ||
| 111 | dma1: dma-controller@ffffee00 { | |
| 112 | compatible = "atmel,at91sam9g45-dma"; | |
| 113 | reg = <0xffffee00 0x200>; | |
| f8a073ee | 114 | interrupts = <21 4 0>; |
| 980ce7d9 | 115 | #dma-cells = <2>; |
| 467f1cf5 NF |
116 | }; |
| 117 | ||
| ec6754a7 | 118 | pinctrl@fffff400 { |
| e4541ff2 JCPV |
119 | #address-cells = <1>; |
| 120 | #size-cells = <1>; | |
| 5314ec8e | 121 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
| e4541ff2 JCPV |
122 | ranges = <0xfffff400 0xfffff400 0x800>; |
| 123 | ||
| 5314ec8e | 124 | /* shared pinctrl settings */ |
| ec6754a7 JCPV |
125 | dbgu { |
| 126 | pinctrl_dbgu: dbgu-0 { | |
| 127 | atmel,pins = | |
| 128 | <0 9 0x1 0x0 /* PA9 periph A */ | |
| 129 | 0 10 0x1 0x1>; /* PA10 periph A with pullup */ | |
| 130 | }; | |
| 131 | }; | |
| 132 | ||
| 9e3129e9 JCPV |
133 | usart0 { |
| 134 | pinctrl_usart0: usart0-0 { | |
| ec6754a7 JCPV |
135 | atmel,pins = |
| 136 | <0 0 0x1 0x1 /* PA0 periph A with pullup */ | |
| 137 | 0 1 0x1 0x0>; /* PA1 periph A */ | |
| 138 | }; | |
| 139 | ||
| c58c0c5a | 140 | pinctrl_usart0_rts: usart0_rts-0 { |
| ec6754a7 | 141 | atmel,pins = |
| c58c0c5a JCPV |
142 | <0 2 0x1 0x0>; /* PA2 periph A */ |
| 143 | }; | |
| 144 | ||
| 145 | pinctrl_usart0_cts: usart0_cts-0 { | |
| 146 | atmel,pins = | |
| 147 | <0 3 0x1 0x0>; /* PA3 periph A */ | |
| ec6754a7 | 148 | }; |
| 1bab02ec RG |
149 | |
| 150 | pinctrl_usart0_sck: usart0_sck-0 { | |
| 151 | atmel,pins = | |
| 152 | <0 4 0x1 0x0>; /* PA4 periph A */ | |
| 153 | }; | |
| ec6754a7 JCPV |
154 | }; |
| 155 | ||
| 9e3129e9 JCPV |
156 | usart1 { |
| 157 | pinctrl_usart1: usart1-0 { | |
| ec6754a7 JCPV |
158 | atmel,pins = |
| 159 | <0 5 0x1 0x1 /* PA5 periph A with pullup */ | |
| 160 | 0 6 0x1 0x0>; /* PA6 periph A */ | |
| 161 | }; | |
| 162 | ||
| c58c0c5a JCPV |
163 | pinctrl_usart1_rts: usart1_rts-0 { |
| 164 | atmel,pins = | |
| c89cec3a | 165 | <2 27 0x3 0x0>; /* PC27 periph C */ |
| c58c0c5a JCPV |
166 | }; |
| 167 | ||
| 168 | pinctrl_usart1_cts: usart1_cts-0 { | |
| ec6754a7 | 169 | atmel,pins = |
| c89cec3a | 170 | <2 28 0x3 0x0>; /* PC28 periph C */ |
| ec6754a7 | 171 | }; |
| 1bab02ec RG |
172 | |
| 173 | pinctrl_usart1_sck: usart1_sck-0 { | |
| 174 | atmel,pins = | |
| 175 | <2 28 0x3 0x0>; /* PC29 periph C */ | |
| 176 | }; | |
| ec6754a7 JCPV |
177 | }; |
| 178 | ||
| 9e3129e9 JCPV |
179 | usart2 { |
| 180 | pinctrl_usart2: usart2-0 { | |
| ec6754a7 JCPV |
181 | atmel,pins = |
| 182 | <0 7 0x1 0x1 /* PA7 periph A with pullup */ | |
| 183 | 0 8 0x1 0x0>; /* PA8 periph A */ | |
| 184 | }; | |
| 185 | ||
| c58c0c5a | 186 | pinctrl_uart2_rts: uart2_rts-0 { |
| ec6754a7 | 187 | atmel,pins = |
| c89cec3a | 188 | <1 0 0x2 0x0>; /* PB0 periph B */ |
| c58c0c5a JCPV |
189 | }; |
| 190 | ||
| 191 | pinctrl_uart2_cts: uart2_cts-0 { | |
| 192 | atmel,pins = | |
| c89cec3a | 193 | <1 1 0x2 0x0>; /* PB1 periph B */ |
| ec6754a7 | 194 | }; |
| 1bab02ec RG |
195 | |
| 196 | pinctrl_usart2_sck: usart2_sck-0 { | |
| 197 | atmel,pins = | |
| 198 | <1 2 0x2 0x0>; /* PB2 periph B */ | |
| 199 | }; | |
| ec6754a7 JCPV |
200 | }; |
| 201 | ||
| 9e3129e9 | 202 | usart3 { |
| 65a0fe04 | 203 | pinctrl_usart3: usart3-0 { |
| ec6754a7 | 204 | atmel,pins = |
| 7d4cfece | 205 | <2 22 0x2 0x1 /* PC22 periph B with pullup */ |
| c89cec3a | 206 | 2 23 0x2 0x0>; /* PC23 periph B */ |
| ec6754a7 JCPV |
207 | }; |
| 208 | ||
| c58c0c5a JCPV |
209 | pinctrl_usart3_rts: usart3_rts-0 { |
| 210 | atmel,pins = | |
| c89cec3a | 211 | <2 24 0x2 0x0>; /* PC24 periph B */ |
| c58c0c5a JCPV |
212 | }; |
| 213 | ||
| 214 | pinctrl_usart3_cts: usart3_cts-0 { | |
| ec6754a7 | 215 | atmel,pins = |
| c89cec3a | 216 | <2 25 0x2 0x0>; /* PC25 periph B */ |
| ec6754a7 | 217 | }; |
| 1bab02ec RG |
218 | |
| 219 | pinctrl_usart3_sck: usart3_sck-0 { | |
| 220 | atmel,pins = | |
| 221 | <2 26 0x2 0x0>; /* PC26 periph B */ | |
| 222 | }; | |
| ec6754a7 JCPV |
223 | }; |
| 224 | ||
| 9e3129e9 JCPV |
225 | uart0 { |
| 226 | pinctrl_uart0: uart0-0 { | |
| ec6754a7 | 227 | atmel,pins = |
| c89cec3a RG |
228 | <2 8 0x3 0x0 /* PC8 periph C */ |
| 229 | 2 9 0x3 0x1>; /* PC9 periph C with pullup */ | |
| ec6754a7 JCPV |
230 | }; |
| 231 | }; | |
| 232 | ||
| 9e3129e9 JCPV |
233 | uart1 { |
| 234 | pinctrl_uart1: uart1-0 { | |
| ec6754a7 | 235 | atmel,pins = |
| c89cec3a RG |
236 | <2 16 0x3 0x0 /* PC16 periph C */ |
| 237 | 2 17 0x3 0x1>; /* PC17 periph C with pullup */ | |
| ec6754a7 JCPV |
238 | }; |
| 239 | }; | |
| 5314ec8e | 240 | |
| 7a38d450 JCPV |
241 | nand { |
| 242 | pinctrl_nand: nand-0 { | |
| 243 | atmel,pins = | |
| 7f06472f RG |
244 | <3 0 0x1 0x0 /* PD0 periph A Read Enable */ |
| 245 | 3 1 0x1 0x0 /* PD1 periph A Write Enable */ | |
| 246 | 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */ | |
| 247 | 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */ | |
| 248 | 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ | |
| 249 | 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */ | |
| 250 | 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */ | |
| 251 | 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */ | |
| 252 | 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */ | |
| 253 | 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */ | |
| 254 | 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */ | |
| 255 | 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */ | |
| 256 | 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */ | |
| 257 | 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */ | |
| 258 | }; | |
| 259 | ||
| 260 | pinctrl_nand_16bits: nand_16bits-0 { | |
| 261 | atmel,pins = | |
| 262 | <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */ | |
| 263 | 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */ | |
| 264 | 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */ | |
| 265 | 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */ | |
| 266 | 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */ | |
| 267 | 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */ | |
| 268 | 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */ | |
| 269 | 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */ | |
| 7a38d450 JCPV |
270 | }; |
| 271 | }; | |
| 272 | ||
| d9b4fe83 JCPV |
273 | macb0 { |
| 274 | pinctrl_macb0_rmii: macb0_rmii-0 { | |
| 275 | atmel,pins = | |
| 276 | <1 0 0x1 0x0 /* PB0 periph A */ | |
| 277 | 1 1 0x1 0x0 /* PB1 periph A */ | |
| 278 | 1 2 0x1 0x0 /* PB2 periph A */ | |
| 279 | 1 3 0x1 0x0 /* PB3 periph A */ | |
| 280 | 1 4 0x1 0x0 /* PB4 periph A */ | |
| 281 | 1 5 0x1 0x0 /* PB5 periph A */ | |
| 282 | 1 6 0x1 0x0 /* PB6 periph A */ | |
| 283 | 1 7 0x1 0x0 /* PB7 periph A */ | |
| 284 | 1 9 0x1 0x0 /* PB9 periph A */ | |
| 285 | 1 10 0x1 0x0>; /* PB10 periph A */ | |
| 286 | }; | |
| 287 | ||
| 288 | pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { | |
| 289 | atmel,pins = | |
| 8461c2f6 DG |
290 | <1 8 0x1 0x0 /* PB8 periph A */ |
| 291 | 1 11 0x1 0x0 /* PB11 periph A */ | |
| 292 | 1 12 0x1 0x0 /* PB12 periph A */ | |
| 293 | 1 13 0x1 0x0 /* PB13 periph A */ | |
| 294 | 1 14 0x1 0x0 /* PB14 periph A */ | |
| 295 | 1 15 0x1 0x0 /* PB15 periph A */ | |
| 296 | 1 16 0x1 0x0 /* PB16 periph A */ | |
| 297 | 1 17 0x1 0x0>; /* PB17 periph A */ | |
| d9b4fe83 JCPV |
298 | }; |
| 299 | }; | |
| 300 | ||
| d4fe9ac7 JCPV |
301 | mmc0 { |
| 302 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | |
| 303 | atmel,pins = | |
| 304 | <0 17 0x1 0x0 /* PA17 periph A */ | |
| 305 | 0 16 0x1 0x1 /* PA16 periph A with pullup */ | |
| 306 | 0 15 0x1 0x1>; /* PA15 periph A with pullup */ | |
| 307 | }; | |
| 308 | ||
| 309 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | |
| 310 | atmel,pins = | |
| 311 | <0 18 0x1 0x1 /* PA18 periph A with pullup */ | |
| 312 | 0 19 0x1 0x1 /* PA19 periph A with pullup */ | |
| 313 | 0 20 0x1 0x1>; /* PA20 periph A with pullup */ | |
| 314 | }; | |
| 315 | }; | |
| 316 | ||
| 317 | mmc1 { | |
| 318 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { | |
| 319 | atmel,pins = | |
| 320 | <0 13 0x2 0x0 /* PA13 periph B */ | |
| 321 | 0 12 0x2 0x1 /* PA12 periph B with pullup */ | |
| 322 | 0 11 0x2 0x1>; /* PA11 periph B with pullup */ | |
| 323 | }; | |
| 324 | ||
| 325 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | |
| 326 | atmel,pins = | |
| 327 | <0 2 0x2 0x1 /* PA2 periph B with pullup */ | |
| 328 | 0 3 0x2 0x1 /* PA3 periph B with pullup */ | |
| 329 | 0 4 0x2 0x1>; /* PA4 periph B with pullup */ | |
| 330 | }; | |
| 331 | }; | |
| 332 | ||
| 544ae6b2 BS |
333 | ssc0 { |
| 334 | pinctrl_ssc0_tx: ssc0_tx-0 { | |
| 335 | atmel,pins = | |
| 336 | <0 24 0x2 0x0 /* PA24 periph B */ | |
| 337 | 0 25 0x2 0x0 /* PA25 periph B */ | |
| 338 | 0 26 0x2 0x0>; /* PA26 periph B */ | |
| 339 | }; | |
| 340 | ||
| 341 | pinctrl_ssc0_rx: ssc0_rx-0 { | |
| 342 | atmel,pins = | |
| 343 | <0 27 0x2 0x0 /* PA27 periph B */ | |
| 344 | 0 28 0x2 0x0 /* PA28 periph B */ | |
| 345 | 0 29 0x2 0x0>; /* PA29 periph B */ | |
| 346 | }; | |
| 347 | }; | |
| 348 | ||
| a68b728f WY |
349 | spi0 { |
| 350 | pinctrl_spi0: spi0-0 { | |
| 351 | atmel,pins = | |
| 352 | <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ | |
| 353 | 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ | |
| 354 | 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ | |
| 355 | }; | |
| 356 | }; | |
| 357 | ||
| 358 | spi1 { | |
| 359 | pinctrl_spi1: spi1-0 { | |
| 360 | atmel,pins = | |
| 361 | <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ | |
| 362 | 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ | |
| 363 | 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ | |
| 364 | }; | |
| 365 | }; | |
| 366 | ||
| e9a72ee8 RG |
367 | i2c0 { |
| 368 | pinctrl_i2c0: i2c0-0 { | |
| 369 | atmel,pins = | |
| 370 | <0 30 0x1 0x0 /* PA30 periph A I2C0 data */ | |
| 371 | 0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */ | |
| 372 | }; | |
| 373 | }; | |
| 374 | ||
| 375 | i2c1 { | |
| 376 | pinctrl_i2c1: i2c1-0 { | |
| 377 | atmel,pins = | |
| 378 | <2 0 0x3 0x0 /* PC0 periph C I2C1 data */ | |
| 379 | 2 1 0x3 0x0>; /* PC1 periph C I2C1 clock */ | |
| 380 | }; | |
| 381 | }; | |
| 382 | ||
| 383 | i2c2 { | |
| 384 | pinctrl_i2c2: i2c2-0 { | |
| 385 | atmel,pins = | |
| 386 | <1 4 0x2 0x0 /* PB4 periph B I2C2 data */ | |
| 387 | 1 5 0x2 0x0>; /* PB5 periph B I2C2 clock */ | |
| 388 | }; | |
| 389 | }; | |
| 390 | ||
| 463c9c7b RG |
391 | i2c_gpio0 { |
| 392 | pinctrl_i2c_gpio0: i2c_gpio0-0 { | |
| 393 | atmel,pins = | |
| 394 | <0 30 0x0 0x2 /* PA30 gpio multidrive I2C0 data */ | |
| 395 | 0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */ | |
| 396 | }; | |
| 397 | }; | |
| 398 | ||
| 399 | i2c_gpio1 { | |
| 400 | pinctrl_i2c_gpio1: i2c_gpio1-0 { | |
| 401 | atmel,pins = | |
| 402 | <2 0 0x0 0x2 /* PC0 gpio multidrive I2C1 data */ | |
| 403 | 2 1 0x0 0x2>; /* PC1 gpio multidrive I2C1 clock */ | |
| 404 | }; | |
| 405 | }; | |
| 406 | ||
| 407 | i2c_gpio2 { | |
| 408 | pinctrl_i2c_gpio2: i2c_gpio2-0 { | |
| 409 | atmel,pins = | |
| 410 | <1 4 0x0 0x2 /* PB4 gpio multidrive I2C2 data */ | |
| 411 | 1 5 0x0 0x2>; /* PB5 gpio multidrive I2C2 clock */ | |
| 412 | }; | |
| 413 | }; | |
| 414 | ||
| e4541ff2 JCPV |
415 | pioA: gpio@fffff400 { |
| 416 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 417 | reg = <0xfffff400 0x200>; | |
| 418 | interrupts = <2 4 1>; | |
| 419 | #gpio-cells = <2>; | |
| 420 | gpio-controller; | |
| 421 | interrupt-controller; | |
| 422 | #interrupt-cells = <2>; | |
| 423 | }; | |
| 424 | ||
| 425 | pioB: gpio@fffff600 { | |
| 426 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 427 | reg = <0xfffff600 0x200>; | |
| 428 | interrupts = <2 4 1>; | |
| 429 | #gpio-cells = <2>; | |
| 430 | gpio-controller; | |
| fc33ff43 | 431 | #gpio-lines = <19>; |
| e4541ff2 JCPV |
432 | interrupt-controller; |
| 433 | #interrupt-cells = <2>; | |
| 434 | }; | |
| 435 | ||
| 436 | pioC: gpio@fffff800 { | |
| 437 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 438 | reg = <0xfffff800 0x200>; | |
| 439 | interrupts = <3 4 1>; | |
| 440 | #gpio-cells = <2>; | |
| 441 | gpio-controller; | |
| 442 | interrupt-controller; | |
| 443 | #interrupt-cells = <2>; | |
| 444 | }; | |
| 445 | ||
| 446 | pioD: gpio@fffffa00 { | |
| 447 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 448 | reg = <0xfffffa00 0x200>; | |
| 449 | interrupts = <3 4 1>; | |
| 450 | #gpio-cells = <2>; | |
| 451 | gpio-controller; | |
| fc33ff43 | 452 | #gpio-lines = <22>; |
| e4541ff2 JCPV |
453 | interrupt-controller; |
| 454 | #interrupt-cells = <2>; | |
| 455 | }; | |
| 467f1cf5 NF |
456 | }; |
| 457 | ||
| 544ae6b2 BS |
458 | ssc0: ssc@f0010000 { |
| 459 | compatible = "atmel,at91sam9g45-ssc"; | |
| 460 | reg = <0xf0010000 0x4000>; | |
| 461 | interrupts = <28 4 5>; | |
| 462 | pinctrl-names = "default"; | |
| 463 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
| 464 | status = "disabled"; | |
| 465 | }; | |
| 466 | ||
| 9873137a LD |
467 | mmc0: mmc@f0008000 { |
| 468 | compatible = "atmel,hsmci"; | |
| 469 | reg = <0xf0008000 0x600>; | |
| 470 | interrupts = <12 4 0>; | |
| 05c1bc97 LD |
471 | dmas = <&dma0 1 0>; |
| 472 | dma-names = "rxtx"; | |
| 9873137a LD |
473 | #address-cells = <1>; |
| 474 | #size-cells = <0>; | |
| 475 | status = "disabled"; | |
| 476 | }; | |
| 477 | ||
| 478 | mmc1: mmc@f000c000 { | |
| 479 | compatible = "atmel,hsmci"; | |
| 480 | reg = <0xf000c000 0x600>; | |
| 481 | interrupts = <26 4 0>; | |
| 05c1bc97 LD |
482 | dmas = <&dma1 1 0>; |
| 483 | dma-names = "rxtx"; | |
| 9873137a LD |
484 | #address-cells = <1>; |
| 485 | #size-cells = <0>; | |
| 486 | status = "disabled"; | |
| 487 | }; | |
| 488 | ||
| 467f1cf5 NF |
489 | dbgu: serial@fffff200 { |
| 490 | compatible = "atmel,at91sam9260-usart"; | |
| 491 | reg = <0xfffff200 0x200>; | |
| f8a073ee | 492 | interrupts = <1 4 7>; |
| ec6754a7 JCPV |
493 | pinctrl-names = "default"; |
| 494 | pinctrl-0 = <&pinctrl_dbgu>; | |
| 467f1cf5 NF |
495 | status = "disabled"; |
| 496 | }; | |
| 497 | ||
| 498 | usart0: serial@f801c000 { | |
| 499 | compatible = "atmel,at91sam9260-usart"; | |
| 500 | reg = <0xf801c000 0x200>; | |
| f8a073ee | 501 | interrupts = <5 4 5>; |
| ec6754a7 | 502 | pinctrl-names = "default"; |
| 9e3129e9 | 503 | pinctrl-0 = <&pinctrl_usart0>; |
| 467f1cf5 NF |
504 | status = "disabled"; |
| 505 | }; | |
| 506 | ||
| 507 | usart1: serial@f8020000 { | |
| 508 | compatible = "atmel,at91sam9260-usart"; | |
| 509 | reg = <0xf8020000 0x200>; | |
| f8a073ee | 510 | interrupts = <6 4 5>; |
| ec6754a7 | 511 | pinctrl-names = "default"; |
| 9e3129e9 | 512 | pinctrl-0 = <&pinctrl_usart1>; |
| 467f1cf5 NF |
513 | status = "disabled"; |
| 514 | }; | |
| 515 | ||
| 516 | usart2: serial@f8024000 { | |
| 517 | compatible = "atmel,at91sam9260-usart"; | |
| 518 | reg = <0xf8024000 0x200>; | |
| f8a073ee | 519 | interrupts = <7 4 5>; |
| ec6754a7 | 520 | pinctrl-names = "default"; |
| 9e3129e9 | 521 | pinctrl-0 = <&pinctrl_usart2>; |
| 467f1cf5 NF |
522 | status = "disabled"; |
| 523 | }; | |
| 524 | ||
| 525 | macb0: ethernet@f802c000 { | |
| 526 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
| 527 | reg = <0xf802c000 0x100>; | |
| f8a073ee | 528 | interrupts = <24 4 3>; |
| d9b4fe83 JCPV |
529 | pinctrl-names = "default"; |
| 530 | pinctrl-0 = <&pinctrl_macb0_rmii>; | |
| 467f1cf5 NF |
531 | status = "disabled"; |
| 532 | }; | |
| 533 | ||
| 534 | macb1: ethernet@f8030000 { | |
| 535 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
| 536 | reg = <0xf8030000 0x100>; | |
| f8a073ee | 537 | interrupts = <27 4 3>; |
| 467f1cf5 NF |
538 | status = "disabled"; |
| 539 | }; | |
| d029f371 | 540 | |
| 05dcd361 LD |
541 | i2c0: i2c@f8010000 { |
| 542 | compatible = "atmel,at91sam9x5-i2c"; | |
| 543 | reg = <0xf8010000 0x100>; | |
| 544 | interrupts = <9 4 6>; | |
| d9a63a45 LD |
545 | dmas = <&dma0 1 7>, |
| 546 | <&dma0 1 8>; | |
| 547 | dma-names = "tx", "rx"; | |
| 05dcd361 LD |
548 | #address-cells = <1>; |
| 549 | #size-cells = <0>; | |
| e9a72ee8 RG |
550 | pinctrl-names = "default"; |
| 551 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 05dcd361 LD |
552 | status = "disabled"; |
| 553 | }; | |
| 554 | ||
| 555 | i2c1: i2c@f8014000 { | |
| 556 | compatible = "atmel,at91sam9x5-i2c"; | |
| 557 | reg = <0xf8014000 0x100>; | |
| 558 | interrupts = <10 4 6>; | |
| d9a63a45 LD |
559 | dmas = <&dma1 1 5>, |
| 560 | <&dma1 1 6>; | |
| 561 | dma-names = "tx", "rx"; | |
| 05dcd361 LD |
562 | #address-cells = <1>; |
| 563 | #size-cells = <0>; | |
| e9a72ee8 RG |
564 | pinctrl-names = "default"; |
| 565 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 05dcd361 LD |
566 | status = "disabled"; |
| 567 | }; | |
| 568 | ||
| 569 | i2c2: i2c@f8018000 { | |
| 570 | compatible = "atmel,at91sam9x5-i2c"; | |
| 571 | reg = <0xf8018000 0x100>; | |
| 572 | interrupts = <11 4 6>; | |
| d9a63a45 LD |
573 | dmas = <&dma0 1 9>, |
| 574 | <&dma0 1 10>; | |
| 575 | dma-names = "tx", "rx"; | |
| 05dcd361 LD |
576 | #address-cells = <1>; |
| 577 | #size-cells = <0>; | |
| e9a72ee8 RG |
578 | pinctrl-names = "default"; |
| 579 | pinctrl-0 = <&pinctrl_i2c2>; | |
| 05dcd361 LD |
580 | status = "disabled"; |
| 581 | }; | |
| 582 | ||
| d029f371 MR |
583 | adc0: adc@f804c000 { |
| 584 | compatible = "atmel,at91sam9260-adc"; | |
| 585 | reg = <0xf804c000 0x100>; | |
| f8a073ee | 586 | interrupts = <19 4 0>; |
| d029f371 MR |
587 | atmel,adc-use-external; |
| 588 | atmel,adc-channels-used = <0xffff>; | |
| 589 | atmel,adc-vref = <3300>; | |
| 590 | atmel,adc-num-channels = <12>; | |
| 591 | atmel,adc-startup-time = <40>; | |
| 592 | atmel,adc-channel-base = <0x50>; | |
| 593 | atmel,adc-drdy-mask = <0x1000000>; | |
| 594 | atmel,adc-status-register = <0x30>; | |
| 595 | atmel,adc-trigger-register = <0xc0>; | |
| 4b50da65 LD |
596 | atmel,adc-res = <8 10>; |
| 597 | atmel,adc-res-names = "lowres", "highres"; | |
| 598 | atmel,adc-use-res = "highres"; | |
| d029f371 MR |
599 | |
| 600 | trigger@0 { | |
| 601 | trigger-name = "external-rising"; | |
| 602 | trigger-value = <0x1>; | |
| 603 | trigger-external; | |
| 604 | }; | |
| 605 | ||
| 606 | trigger@1 { | |
| 607 | trigger-name = "external-falling"; | |
| 608 | trigger-value = <0x2>; | |
| 609 | trigger-external; | |
| 610 | }; | |
| 611 | ||
| 612 | trigger@2 { | |
| 613 | trigger-name = "external-any"; | |
| 614 | trigger-value = <0x3>; | |
| 615 | trigger-external; | |
| 616 | }; | |
| 617 | ||
| 618 | trigger@3 { | |
| 619 | trigger-name = "continuous"; | |
| 620 | trigger-value = <0x6>; | |
| 621 | }; | |
| 622 | }; | |
| d50f88a0 RG |
623 | |
| 624 | spi0: spi@f0000000 { | |
| 625 | #address-cells = <1>; | |
| 626 | #size-cells = <0>; | |
| 627 | compatible = "atmel,at91rm9200-spi"; | |
| 628 | reg = <0xf0000000 0x100>; | |
| 629 | interrupts = <13 4 3>; | |
| a68b728f WY |
630 | pinctrl-names = "default"; |
| 631 | pinctrl-0 = <&pinctrl_spi0>; | |
| d50f88a0 RG |
632 | status = "disabled"; |
| 633 | }; | |
| 634 | ||
| 635 | spi1: spi@f0004000 { | |
| 636 | #address-cells = <1>; | |
| 637 | #size-cells = <0>; | |
| 638 | compatible = "atmel,at91rm9200-spi"; | |
| 639 | reg = <0xf0004000 0x100>; | |
| 640 | interrupts = <14 4 3>; | |
| a68b728f WY |
641 | pinctrl-names = "default"; |
| 642 | pinctrl-0 = <&pinctrl_spi1>; | |
| d50f88a0 RG |
643 | status = "disabled"; |
| 644 | }; | |
| dfab34aa | 645 | |
| b909c6c9 NF |
646 | rtc@fffffeb0 { |
| 647 | compatible = "atmel,at91rm9200-rtc"; | |
| 648 | reg = <0xfffffeb0 0x40>; | |
| 649 | interrupts = <1 4 7>; | |
| 650 | status = "disabled"; | |
| 651 | }; | |
| 467f1cf5 | 652 | }; |
| 86a89f4f JCPV |
653 | |
| 654 | nand0: nand@40000000 { | |
| 655 | compatible = "atmel,at91rm9200-nand"; | |
| 656 | #address-cells = <1>; | |
| 657 | #size-cells = <1>; | |
| 658 | reg = <0x40000000 0x10000000 | |
| 5314bc2d JW |
659 | 0xffffe000 0x600 /* PMECC Registers */ |
| 660 | 0xffffe600 0x200 /* PMECC Error Location Registers */ | |
| 661 | 0x00108000 0x18000 /* PMECC looup table in ROM code */ | |
| 86a89f4f | 662 | >; |
| 5314bc2d | 663 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
| 86a89f4f JCPV |
664 | atmel,nand-addr-offset = <21>; |
| 665 | atmel,nand-cmd-offset = <22>; | |
| 7a38d450 JCPV |
666 | pinctrl-names = "default"; |
| 667 | pinctrl-0 = <&pinctrl_nand>; | |
| 92f8629b JCPV |
668 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
| 669 | &pioD 4 GPIO_ACTIVE_HIGH | |
| 86a89f4f JCPV |
670 | 0 |
| 671 | >; | |
| 672 | status = "disabled"; | |
| 673 | }; | |
| 6a062459 JCPV |
674 | |
| 675 | usb0: ohci@00600000 { | |
| 676 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
| 677 | reg = <0x00600000 0x100000>; | |
| f8a073ee | 678 | interrupts = <22 4 2>; |
| 6a062459 JCPV |
679 | status = "disabled"; |
| 680 | }; | |
| 62c5553a JCPV |
681 | |
| 682 | usb1: ehci@00700000 { | |
| 683 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
| 684 | reg = <0x00700000 0x100000>; | |
| f8a073ee | 685 | interrupts = <22 4 2>; |
| 62c5553a JCPV |
686 | status = "disabled"; |
| 687 | }; | |
| 467f1cf5 | 688 | }; |
| 10f71c28 JCPV |
689 | |
| 690 | i2c@0 { | |
| 691 | compatible = "i2c-gpio"; | |
| 92f8629b JCPV |
692 | gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ |
| 693 | &pioA 31 GPIO_ACTIVE_HIGH /* scl */ | |
| 10f71c28 JCPV |
694 | >; |
| 695 | i2c-gpio,sda-open-drain; | |
| 696 | i2c-gpio,scl-open-drain; | |
| 697 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
| 698 | #address-cells = <1>; | |
| 699 | #size-cells = <0>; | |
| 463c9c7b RG |
700 | pinctrl-names = "default"; |
| 701 | pinctrl-0 = <&pinctrl_i2c_gpio0>; | |
| 10f71c28 JCPV |
702 | status = "disabled"; |
| 703 | }; | |
| 704 | ||
| 705 | i2c@1 { | |
| 706 | compatible = "i2c-gpio"; | |
| 92f8629b JCPV |
707 | gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ |
| 708 | &pioC 1 GPIO_ACTIVE_HIGH /* scl */ | |
| 10f71c28 JCPV |
709 | >; |
| 710 | i2c-gpio,sda-open-drain; | |
| 711 | i2c-gpio,scl-open-drain; | |
| 712 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
| 713 | #address-cells = <1>; | |
| 714 | #size-cells = <0>; | |
| 463c9c7b RG |
715 | pinctrl-names = "default"; |
| 716 | pinctrl-0 = <&pinctrl_i2c_gpio1>; | |
| 10f71c28 JCPV |
717 | status = "disabled"; |
| 718 | }; | |
| 719 | ||
| 720 | i2c@2 { | |
| 721 | compatible = "i2c-gpio"; | |
| 92f8629b JCPV |
722 | gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ |
| 723 | &pioB 5 GPIO_ACTIVE_HIGH /* scl */ | |
| 10f71c28 JCPV |
724 | >; |
| 725 | i2c-gpio,sda-open-drain; | |
| 726 | i2c-gpio,scl-open-drain; | |
| 727 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
| 728 | #address-cells = <1>; | |
| 729 | #size-cells = <0>; | |
| 463c9c7b RG |
730 | pinctrl-names = "default"; |
| 731 | pinctrl-0 = <&pinctrl_i2c_gpio2>; | |
| 10f71c28 JCPV |
732 | status = "disabled"; |
| 733 | }; | |
| 467f1cf5 | 734 | }; |