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ARM: dts: aspeed: Add LPC and child devices
[linux-2.6-block.git] / arch / arm / boot / dts / aspeed-g4.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
d44a1138
JS		 2#include "skeleton.dtsi"
3
4/ {
5 model = "Aspeed BMC";
6 compatible = "aspeed,ast2400";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
10
ef856378
JS		 11 aliases {
12 i2c0 = &i2c0;
13 i2c1 = &i2c1;
14 i2c2 = &i2c2;
15 i2c3 = &i2c3;
16 i2c4 = &i2c4;
17 i2c5 = &i2c5;
18 i2c6 = &i2c6;
19 i2c7 = &i2c7;
20 i2c8 = &i2c8;
21 i2c9 = &i2c9;
22 i2c10 = &i2c10;
23 i2c11 = &i2c11;
24 i2c12 = &i2c12;
25 i2c13 = &i2c13;
0bae3904
JS		 26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 serial4 = &uart5;
a19331ca 31 serial5 = &vuart;
ef856378
JS		 32 };
33
d44a1138
JS		 34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
41 reg = <0>;
42 };
43 };
44
d44a1138
JS		 45 ahb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
74dc3cd3
CLG		 51 fmc: flash-controller@1e620000 {
52 reg = < 0x1e620000 0x94
bcbd328d 53 0x20000000 0x10000000 >;
74dc3cd3
CLG		 54 #address-cells = <1>;
55 #size-cells = <0>;
56 compatible = "aspeed,ast2400-fmc";
57 status = "disabled";
58 interrupts = <19>;
59 flash@0 {
60 reg = < 0 >;
61 compatible = "jedec,spi-nor";
62 status = "disabled";
63 };
64 };
65
66 spi: flash-controller@1e630000 {
67 reg = < 0x1e630000 0x18
bcbd328d 68 0x30000000 0x10000000 >;
74dc3cd3
CLG		 69 #address-cells = <1>;
70 #size-cells = <0>;
71 compatible = "aspeed,ast2400-spi";
72 status = "disabled";
73 flash@0 {
74 reg = < 0 >;
75 compatible = "jedec,spi-nor";
76 status = "disabled";
77 };
78 };
79
d44a1138
JS		 80 vic: interrupt-controller@1e6c0080 {
81 compatible = "aspeed,ast2400-vic";
82 interrupt-controller;
83 #interrupt-cells = <1>;
84 valid-sources = <0xffffffff 0x0007ffff>;
85 reg = <0x1e6c0080 0x80>;
86 };
87
34ea5c9d 88 mac0: ethernet@1e660000 {
78d28543 89 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
34ea5c9d
JS		 90 reg = <0x1e660000 0x180>;
91 interrupts = <2>;
34ea5c9d
JS		 92 status = "disabled";
93 };
94
95 mac1: ethernet@1e680000 {
78d28543 96 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
34ea5c9d
JS		 97 reg = <0x1e680000 0x180>;
98 interrupts = <3>;
34ea5c9d
JS		 99 status = "disabled";
100 };
101
d44a1138
JS		 102 apb {
103 compatible = "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 ranges;
107
d9072279
AJ		 108 syscon: syscon@1e6e2000 {
109 compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
110 reg = <0x1e6e2000 0x1a8>;
491bdcfa
JS		 111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 clk_clkin: clk_clkin {
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
117 clock-frequency = <48000000>;
118 };
119
120 clk_hpll: clk_hpll@70 {
121 #clock-cells = <0>;
122 compatible = "aspeed,g4-hpll-clock", "fixed-clock";
123 reg = <0x70>;
124 clocks = <&clk_clkin>;
125 clock-frequency = <384000000>;
126 };
127
128 clk_ahb: clk_ahb@70 {
129 #clock-cells = <0>;
130 compatible = "aspeed,g4-ahb-clock", "fixed-clock";
131 reg = <0x70>;
132 clocks = <&clk_hpll>;
133 clock-frequency = <192000000>;
134 };
135
8dccafaa 136 clk_apb: clk_apb@8 {
491bdcfa
JS		 137 #clock-cells = <0>;
138 compatible = "aspeed,g4-apb-clock", "fixed-clock";
139 reg = <0x08>;
140 clocks = <&clk_hpll>;
141 clock-frequency = <48000000>;
142 };
143
144 clk_uart: clk_uart@2c{
145 #clock-cells = <0>;
146 compatible = "aspeed,g4-uart-clock", "fixed-clock";
147 reg = <0x2c>;
148 clock-frequency = <24000000>;
149 };
d9072279
AJ		 150
151 pinctrl: pinctrl {
152 compatible = "aspeed,g4-pinctrl";
d9072279
AJ		 153 };
154 };
155
29b24640
JS		 156 adc: adc@1e6e9000 {
157 compatible = "aspeed,ast2400-adc";
158 reg = <0x1e6e9000 0xb0>;
159 clocks = <&clk_apb>;
160 #io-channel-cells = <1>;
161 status = "disabled";
162 };
163
d44a1138
JS		 164 sram@1e720000 {
165 compatible = "mmio-sram";
166 reg = <0x1e720000 0x8000>; // 32K
167 };
168
09955007
AJ		 169 gpio: gpio@1e780000 {
170 #gpio-cells = <2>;
171 gpio-controller;
172 compatible = "aspeed,ast2400-gpio";
173 reg = <0x1e780000 0x1000>;
174 interrupts = <20>;
175 gpio-ranges = <&pinctrl 0 0 220>;
176 interrupt-controller;
177 };
178
d44a1138 179 timer: timer@1e782000 {
f46b563f 180 /* This timer is a Faraday FTTMR010 derivative */
d44a1138
JS		 181 compatible = "aspeed,ast2400-timer";
182 reg = <0x1e782000 0x90>;
f46b563f 183 interrupts = <16 17 18 35 36 37 38 39>;
d44a1138 184 clocks = <&clk_apb>;
f46b563f 185 clock-names = "PCLK";
d44a1138
JS		 186 };
187
d44a1138
JS		 188 uart1: serial@1e783000 {
189 compatible = "ns16550a";
a19331ca 190 reg = <0x1e783000 0x20>;
d44a1138
JS		 191 reg-shift = <2>;
192 interrupts = <9>;
193 clocks = <&clk_uart>;
194 no-loopback-test;
195 status = "disabled";
196 };
197
db4d6d9d 198 uart5: serial@1e784000 {
d44a1138 199 compatible = "ns16550a";
a19331ca 200 reg = <0x1e784000 0x20>;
d44a1138 201 reg-shift = <2>;
db4d6d9d 202 interrupts = <10>;
d44a1138
JS		 203 clocks = <&clk_uart>;
204 no-loopback-test;
205 status = "disabled";
206 };
207
424bd7e6 208 wdt1: watchdog@1e785000 {
23491da8 209 compatible = "aspeed,ast2400-wdt";
d44a1138 210 reg = <0x1e785000 0x1c>;
d44a1138
JS		 211 };
212
424bd7e6 213 wdt2: watchdog@1e785020 {
23491da8 214 compatible = "aspeed,ast2400-wdt";
d44a1138 215 reg = <0x1e785020 0x1c>;
d44a1138
JS		 216 };
217
a19331ca
JS		 218 vuart: serial@1e787000 {
219 compatible = "aspeed,ast2400-vuart";
220 reg = <0x1e787000 0x40>;
d44a1138 221 reg-shift = <2>;
db4d6d9d 222 interrupts = <10>;
d44a1138
JS		 223 clocks = <&clk_uart>;
224 no-loopback-test;
225 status = "disabled";
226 };
227
b6436f76
AJ		 228 lpc: lpc@1e789000 {
229 compatible = "aspeed,ast2400-lpc", "simple-mfd";
230 reg = <0x1e789000 0x1000>;
231
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges = <0x0 0x1e789000 0x1000>;
235
236 lpc_bmc: lpc-bmc@0 {
237 compatible = "aspeed,ast2400-lpc-bmc";
238 reg = <0x0 0x80>;
239 };
240
241 lpc_host: lpc-host@80 {
242 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
243 reg = <0x80 0x1e0>;
244 reg-io-width = <4>;
245
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0x0 0x80 0x1e0>;
249
250 lpc_ctrl: lpc-ctrl@0 {
251 compatible = "aspeed,ast2400-lpc-ctrl";
252 reg = <0x0 0x80>;
253 status = "disabled";
254 };
255
256 lhc: lhc@20 {
257 compatible = "aspeed,ast2400-lhc";
258 reg = <0x20 0x24 0x48 0x8>;
259 };
260 };
261 };
262
d44a1138 263 uart2: serial@1e78d000 {
d44a1138 264 compatible = "ns16550a";
a19331ca 265 reg = <0x1e78d000 0x20>;
d44a1138 266 reg-shift = <2>;
d44a1138 267 interrupts = <32>;
d44a1138
JS		 268 clocks = <&clk_uart>;
269 no-loopback-test;
270 status = "disabled";
271 };
272
d44a1138 273 uart3: serial@1e78e000 {
d44a1138 274 compatible = "ns16550a";
a19331ca 275 reg = <0x1e78e000 0x20>;
d44a1138 276 reg-shift = <2>;
d44a1138 277 interrupts = <33>;
d44a1138 278 clocks = <&clk_uart>;
d44a1138
JS		 279 no-loopback-test;
280 status = "disabled";
281 };
282
d44a1138 283 uart4: serial@1e78f000 {
d44a1138 284 compatible = "ns16550a";
a19331ca 285 reg = <0x1e78f000 0x20>;
d44a1138 286 reg-shift = <2>;
d44a1138 287 interrupts = <34>;
d44a1138
JS		 288 clocks = <&clk_uart>;
289 no-loopback-test;
290 status = "disabled";
291 };
78a2569f 292
ef856378
JS		 293 i2c: i2c@1e78a000 {
294 compatible = "simple-bus";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 ranges = <0 0x1e78a000 0x1000>;
78a2569f 298 };
d44a1138
JS		 299 };
300 };
301};
cd7df3f7 302
ef856378
JS		 303&i2c {
304 i2c_ic: interrupt-controller@0 {
305 #interrupt-cells = <1>;
306 compatible = "aspeed,ast2400-i2c-ic";
307 reg = <0x0 0x40>;
308 interrupts = <12>;
309 interrupt-controller;
310 };
311
312 i2c0: i2c-bus@40 {
313 #address-cells = <1>;
314 #size-cells = <0>;
315 #interrupt-cells = <1>;
316
317 reg = <0x40 0x40>;
318 compatible = "aspeed,ast2400-i2c-bus";
319 clocks = <&clk_apb>;
320 bus-frequency = <100000>;
321 interrupts = <0>;
322 interrupt-parent = <&i2c_ic>;
323 status = "disabled";
324 /* Does not need pinctrl properties */
325 };
326
327 i2c1: i2c-bus@80 {
328 #address-cells = <1>;
329 #size-cells = <0>;
330 #interrupt-cells = <1>;
331
332 reg = <0x80 0x40>;
333 compatible = "aspeed,ast2400-i2c-bus";
334 clocks = <&clk_apb>;
335 bus-frequency = <100000>;
336 interrupts = <1>;
337 interrupt-parent = <&i2c_ic>;
338 status = "disabled";
339 /* Does not need pinctrl properties */
340 };
341
342 i2c2: i2c-bus@c0 {
343 #address-cells = <1>;
344 #size-cells = <0>;
345 #interrupt-cells = <1>;
346
347 reg = <0xc0 0x40>;
348 compatible = "aspeed,ast2400-i2c-bus";
349 clocks = <&clk_apb>;
350 bus-frequency = <100000>;
351 interrupts = <2>;
352 interrupt-parent = <&i2c_ic>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_i2c3_default>;
355 status = "disabled";
356 };
357
358 i2c3: i2c-bus@100 {
359 #address-cells = <1>;
360 #size-cells = <0>;
361 #interrupt-cells = <1>;
362
363 reg = <0x100 0x40>;
364 compatible = "aspeed,ast2400-i2c-bus";
365 clocks = <&clk_apb>;
366 bus-frequency = <100000>;
367 interrupts = <3>;
368 interrupt-parent = <&i2c_ic>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_i2c4_default>;
371 status = "disabled";
372 };
373
374 i2c4: i2c-bus@140 {
375 #address-cells = <1>;
376 #size-cells = <0>;
377 #interrupt-cells = <1>;
378
379 reg = <0x140 0x40>;
380 compatible = "aspeed,ast2400-i2c-bus";
381 clocks = <&clk_apb>;
382 bus-frequency = <100000>;
383 interrupts = <4>;
384 interrupt-parent = <&i2c_ic>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_i2c5_default>;
387 status = "disabled";
388 };
389
390 i2c5: i2c-bus@180 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 #interrupt-cells = <1>;
394
395 reg = <0x180 0x40>;
396 compatible = "aspeed,ast2400-i2c-bus";
397 clocks = <&clk_apb>;
398 bus-frequency = <100000>;
399 interrupts = <5>;
400 interrupt-parent = <&i2c_ic>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_i2c6_default>;
403 status = "disabled";
404 };
405
406 i2c6: i2c-bus@1c0 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 #interrupt-cells = <1>;
410
411 reg = <0x1c0 0x40>;
412 compatible = "aspeed,ast2400-i2c-bus";
413 clocks = <&clk_apb>;
414 bus-frequency = <100000>;
415 interrupts = <6>;
416 interrupt-parent = <&i2c_ic>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_i2c7_default>;
419 status = "disabled";
420 };
421
422 i2c7: i2c-bus@300 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 #interrupt-cells = <1>;
426
427 reg = <0x300 0x40>;
428 compatible = "aspeed,ast2400-i2c-bus";
429 clocks = <&clk_apb>;
430 bus-frequency = <100000>;
431 interrupts = <7>;
432 interrupt-parent = <&i2c_ic>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_i2c8_default>;
435 status = "disabled";
436 };
437
438 i2c8: i2c-bus@340 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 #interrupt-cells = <1>;
442
443 reg = <0x340 0x40>;
444 compatible = "aspeed,ast2400-i2c-bus";
445 clocks = <&clk_apb>;
446 bus-frequency = <100000>;
447 interrupts = <8>;
448 interrupt-parent = <&i2c_ic>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_i2c9_default>;
451 status = "disabled";
452 };
453
454 i2c9: i2c-bus@380 {
455 #address-cells = <1>;
456 #size-cells = <0>;
457 #interrupt-cells = <1>;
458
459 reg = <0x380 0x40>;
460 compatible = "aspeed,ast2400-i2c-bus";
461 clocks = <&clk_apb>;
462 bus-frequency = <100000>;
463 interrupts = <9>;
464 interrupt-parent = <&i2c_ic>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_i2c10_default>;
467 status = "disabled";
468 };
469
470 i2c10: i2c-bus@3c0 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 #interrupt-cells = <1>;
474
475 reg = <0x3c0 0x40>;
476 compatible = "aspeed,ast2400-i2c-bus";
477 clocks = <&clk_apb>;
478 bus-frequency = <100000>;
479 interrupts = <10>;
480 interrupt-parent = <&i2c_ic>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_i2c11_default>;
483 status = "disabled";
484 };
485
486 i2c11: i2c-bus@400 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 #interrupt-cells = <1>;
490
491 reg = <0x400 0x40>;
492 compatible = "aspeed,ast2400-i2c-bus";
493 clocks = <&clk_apb>;
494 bus-frequency = <100000>;
495 interrupts = <11>;
496 interrupt-parent = <&i2c_ic>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_i2c12_default>;
499 status = "disabled";
500 };
501
502 i2c12: i2c-bus@440 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 #interrupt-cells = <1>;
506
507 reg = <0x440 0x40>;
508 compatible = "aspeed,ast2400-i2c-bus";
509 clocks = <&clk_apb>;
510 bus-frequency = <100000>;
511 interrupts = <12>;
512 interrupt-parent = <&i2c_ic>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_i2c13_default>;
515 status = "disabled";
516 };
517
518 i2c13: i2c-bus@480 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 #interrupt-cells = <1>;
522
523 reg = <0x480 0x40>;
524 compatible = "aspeed,ast2400-i2c-bus";
525 clocks = <&clk_apb>;
526 bus-frequency = <100000>;
527 interrupts = <13>;
528 interrupt-parent = <&i2c_ic>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_i2c14_default>;
531 status = "disabled";
532 };
533};
534
cd7df3f7
AJ		 535&pinctrl {
536 pinctrl_acpi_default: acpi_default {
537 function = "ACPI";
538 groups = "ACPI";
539 };
540
541 pinctrl_adc0_default: adc0_default {
542 function = "ADC0";
543 groups = "ADC0";
544 };
545
546 pinctrl_adc1_default: adc1_default {
547 function = "ADC1";
548 groups = "ADC1";
549 };
550
551 pinctrl_adc10_default: adc10_default {
552 function = "ADC10";
553 groups = "ADC10";
554 };
555
556 pinctrl_adc11_default: adc11_default {
557 function = "ADC11";
558 groups = "ADC11";
559 };
560
561 pinctrl_adc12_default: adc12_default {
562 function = "ADC12";
563 groups = "ADC12";
564 };
565
566 pinctrl_adc13_default: adc13_default {
567 function = "ADC13";
568 groups = "ADC13";
569 };
570
571 pinctrl_adc14_default: adc14_default {
572 function = "ADC14";
573 groups = "ADC14";
574 };
575
576 pinctrl_adc15_default: adc15_default {
577 function = "ADC15";
578 groups = "ADC15";
579 };
580
581 pinctrl_adc2_default: adc2_default {
582 function = "ADC2";
583 groups = "ADC2";
584 };
585
586 pinctrl_adc3_default: adc3_default {
587 function = "ADC3";
588 groups = "ADC3";
589 };
590
591 pinctrl_adc4_default: adc4_default {
592 function = "ADC4";
593 groups = "ADC4";
594 };
595
596 pinctrl_adc5_default: adc5_default {
597 function = "ADC5";
598 groups = "ADC5";
599 };
600
601 pinctrl_adc6_default: adc6_default {
602 function = "ADC6";
603 groups = "ADC6";
604 };
605
606 pinctrl_adc7_default: adc7_default {
607 function = "ADC7";
608 groups = "ADC7";
609 };
610
611 pinctrl_adc8_default: adc8_default {
612 function = "ADC8";
613 groups = "ADC8";
614 };
615
616 pinctrl_adc9_default: adc9_default {
617 function = "ADC9";
618 groups = "ADC9";
619 };
620
621 pinctrl_bmcint_default: bmcint_default {
622 function = "BMCINT";
623 groups = "BMCINT";
624 };
625
626 pinctrl_ddcclk_default: ddcclk_default {
627 function = "DDCCLK";
628 groups = "DDCCLK";
629 };
630
631 pinctrl_ddcdat_default: ddcdat_default {
632 function = "DDCDAT";
633 groups = "DDCDAT";
634 };
635
636 pinctrl_extrst_default: extrst_default {
637 function = "EXTRST";
638 groups = "EXTRST";
639 };
640
641 pinctrl_flack_default: flack_default {
642 function = "FLACK";
643 groups = "FLACK";
644 };
645
646 pinctrl_flbusy_default: flbusy_default {
647 function = "FLBUSY";
648 groups = "FLBUSY";
649 };
650
651 pinctrl_flwp_default: flwp_default {
652 function = "FLWP";
653 groups = "FLWP";
654 };
655
656 pinctrl_gpid_default: gpid_default {
657 function = "GPID";
658 groups = "GPID";
659 };
660
661 pinctrl_gpid0_default: gpid0_default {
662 function = "GPID0";
663 groups = "GPID0";
664 };
665
666 pinctrl_gpid2_default: gpid2_default {
667 function = "GPID2";
668 groups = "GPID2";
669 };
670
671 pinctrl_gpid4_default: gpid4_default {
672 function = "GPID4";
673 groups = "GPID4";
674 };
675
676 pinctrl_gpid6_default: gpid6_default {
677 function = "GPID6";
678 groups = "GPID6";
679 };
680
681 pinctrl_gpie0_default: gpie0_default {
682 function = "GPIE0";
683 groups = "GPIE0";
684 };
685
686 pinctrl_gpie2_default: gpie2_default {
687 function = "GPIE2";
688 groups = "GPIE2";
689 };
690
691 pinctrl_gpie4_default: gpie4_default {
692 function = "GPIE4";
693 groups = "GPIE4";
694 };
695
696 pinctrl_gpie6_default: gpie6_default {
697 function = "GPIE6";
698 groups = "GPIE6";
699 };
700
701 pinctrl_i2c10_default: i2c10_default {
702 function = "I2C10";
703 groups = "I2C10";
704 };
705
706 pinctrl_i2c11_default: i2c11_default {
707 function = "I2C11";
708 groups = "I2C11";
709 };
710
711 pinctrl_i2c12_default: i2c12_default {
712 function = "I2C12";
713 groups = "I2C12";
714 };
715
716 pinctrl_i2c13_default: i2c13_default {
717 function = "I2C13";
718 groups = "I2C13";
719 };
720
721 pinctrl_i2c14_default: i2c14_default {
722 function = "I2C14";
723 groups = "I2C14";
724 };
725
726 pinctrl_i2c3_default: i2c3_default {
727 function = "I2C3";
728 groups = "I2C3";
729 };
730
731 pinctrl_i2c4_default: i2c4_default {
732 function = "I2C4";
733 groups = "I2C4";
734 };
735
736 pinctrl_i2c5_default: i2c5_default {
737 function = "I2C5";
738 groups = "I2C5";
739 };
740
741 pinctrl_i2c6_default: i2c6_default {
742 function = "I2C6";
743 groups = "I2C6";
744 };
745
746 pinctrl_i2c7_default: i2c7_default {
747 function = "I2C7";
748 groups = "I2C7";
749 };
750
751 pinctrl_i2c8_default: i2c8_default {
752 function = "I2C8";
753 groups = "I2C8";
754 };
755
756 pinctrl_i2c9_default: i2c9_default {
757 function = "I2C9";
758 groups = "I2C9";
759 };
760
761 pinctrl_lpcpd_default: lpcpd_default {
762 function = "LPCPD";
763 groups = "LPCPD";
764 };
765
766 pinctrl_lpcpme_default: lpcpme_default {
767 function = "LPCPME";
768 groups = "LPCPME";
769 };
770
771 pinctrl_lpcrst_default: lpcrst_default {
772 function = "LPCRST";
773 groups = "LPCRST";
774 };
775
776 pinctrl_lpcsmi_default: lpcsmi_default {
777 function = "LPCSMI";
778 groups = "LPCSMI";
779 };
780
781 pinctrl_mac1link_default: mac1link_default {
782 function = "MAC1LINK";
783 groups = "MAC1LINK";
784 };
785
786 pinctrl_mac2link_default: mac2link_default {
787 function = "MAC2LINK";
788 groups = "MAC2LINK";
789 };
790
791 pinctrl_mdio1_default: mdio1_default {
792 function = "MDIO1";
793 groups = "MDIO1";
794 };
795
796 pinctrl_mdio2_default: mdio2_default {
797 function = "MDIO2";
798 groups = "MDIO2";
799 };
800
801 pinctrl_ncts1_default: ncts1_default {
802 function = "NCTS1";
803 groups = "NCTS1";
804 };
805
806 pinctrl_ncts2_default: ncts2_default {
807 function = "NCTS2";
808 groups = "NCTS2";
809 };
810
811 pinctrl_ncts3_default: ncts3_default {
812 function = "NCTS3";
813 groups = "NCTS3";
814 };
815
816 pinctrl_ncts4_default: ncts4_default {
817 function = "NCTS4";
818 groups = "NCTS4";
819 };
820
821 pinctrl_ndcd1_default: ndcd1_default {
822 function = "NDCD1";
823 groups = "NDCD1";
824 };
825
826 pinctrl_ndcd2_default: ndcd2_default {
827 function = "NDCD2";
828 groups = "NDCD2";
829 };
830
831 pinctrl_ndcd3_default: ndcd3_default {
832 function = "NDCD3";
833 groups = "NDCD3";
834 };
835
836 pinctrl_ndcd4_default: ndcd4_default {
837 function = "NDCD4";
838 groups = "NDCD4";
839 };
840
841 pinctrl_ndsr1_default: ndsr1_default {
842 function = "NDSR1";
843 groups = "NDSR1";
844 };
845
846 pinctrl_ndsr2_default: ndsr2_default {
847 function = "NDSR2";
848 groups = "NDSR2";
849 };
850
851 pinctrl_ndsr3_default: ndsr3_default {
852 function = "NDSR3";
853 groups = "NDSR3";
854 };
855
856 pinctrl_ndsr4_default: ndsr4_default {
857 function = "NDSR4";
858 groups = "NDSR4";
859 };
860
861 pinctrl_ndtr1_default: ndtr1_default {
862 function = "NDTR1";
863 groups = "NDTR1";
864 };
865
866 pinctrl_ndtr2_default: ndtr2_default {
867 function = "NDTR2";
868 groups = "NDTR2";
869 };
870
871 pinctrl_ndtr3_default: ndtr3_default {
872 function = "NDTR3";
873 groups = "NDTR3";
874 };
875
876 pinctrl_ndtr4_default: ndtr4_default {
877 function = "NDTR4";
878 groups = "NDTR4";
879 };
880
881 pinctrl_ndts4_default: ndts4_default {
882 function = "NDTS4";
883 groups = "NDTS4";
884 };
885
886 pinctrl_nri1_default: nri1_default {
887 function = "NRI1";
888 groups = "NRI1";
889 };
890
891 pinctrl_nri2_default: nri2_default {
892 function = "NRI2";
893 groups = "NRI2";
894 };
895
896 pinctrl_nri3_default: nri3_default {
897 function = "NRI3";
898 groups = "NRI3";
899 };
900
901 pinctrl_nri4_default: nri4_default {
902 function = "NRI4";
903 groups = "NRI4";
904 };
905
906 pinctrl_nrts1_default: nrts1_default {
907 function = "NRTS1";
908 groups = "NRTS1";
909 };
910
911 pinctrl_nrts2_default: nrts2_default {
912 function = "NRTS2";
913 groups = "NRTS2";
914 };
915
916 pinctrl_nrts3_default: nrts3_default {
917 function = "NRTS3";
918 groups = "NRTS3";
919 };
920
921 pinctrl_oscclk_default: oscclk_default {
922 function = "OSCCLK";
923 groups = "OSCCLK";
924 };
925
926 pinctrl_pwm0_default: pwm0_default {
927 function = "PWM0";
928 groups = "PWM0";
929 };
930
931 pinctrl_pwm1_default: pwm1_default {
932 function = "PWM1";
933 groups = "PWM1";
934 };
935
936 pinctrl_pwm2_default: pwm2_default {
937 function = "PWM2";
938 groups = "PWM2";
939 };
940
941 pinctrl_pwm3_default: pwm3_default {
942 function = "PWM3";
943 groups = "PWM3";
944 };
945
946 pinctrl_pwm4_default: pwm4_default {
947 function = "PWM4";
948 groups = "PWM4";
949 };
950
951 pinctrl_pwm5_default: pwm5_default {
952 function = "PWM5";
953 groups = "PWM5";
954 };
955
956 pinctrl_pwm6_default: pwm6_default {
957 function = "PWM6";
958 groups = "PWM6";
959 };
960
961 pinctrl_pwm7_default: pwm7_default {
962 function = "PWM7";
963 groups = "PWM7";
964 };
965
966 pinctrl_rgmii1_default: rgmii1_default {
967 function = "RGMII1";
968 groups = "RGMII1";
969 };
970
971 pinctrl_rgmii2_default: rgmii2_default {
972 function = "RGMII2";
973 groups = "RGMII2";
974 };
975
976 pinctrl_rmii1_default: rmii1_default {
977 function = "RMII1";
978 groups = "RMII1";
979 };
980
981 pinctrl_rmii2_default: rmii2_default {
982 function = "RMII2";
983 groups = "RMII2";
984 };
985
986 pinctrl_rom16_default: rom16_default {
987 function = "ROM16";
988 groups = "ROM16";
989 };
990
991 pinctrl_rom8_default: rom8_default {
992 function = "ROM8";
993 groups = "ROM8";
994 };
995
996 pinctrl_romcs1_default: romcs1_default {
997 function = "ROMCS1";
998 groups = "ROMCS1";
999 };
1000
1001 pinctrl_romcs2_default: romcs2_default {
1002 function = "ROMCS2";
1003 groups = "ROMCS2";
1004 };
1005
1006 pinctrl_romcs3_default: romcs3_default {
1007 function = "ROMCS3";
1008 groups = "ROMCS3";
1009 };
1010
1011 pinctrl_romcs4_default: romcs4_default {
1012 function = "ROMCS4";
1013 groups = "ROMCS4";
1014 };
1015
1016 pinctrl_rxd1_default: rxd1_default {
1017 function = "RXD1";
1018 groups = "RXD1";
1019 };
1020
1021 pinctrl_rxd2_default: rxd2_default {
1022 function = "RXD2";
1023 groups = "RXD2";
1024 };
1025
1026 pinctrl_rxd3_default: rxd3_default {
1027 function = "RXD3";
1028 groups = "RXD3";
1029 };
1030
1031 pinctrl_rxd4_default: rxd4_default {
1032 function = "RXD4";
1033 groups = "RXD4";
1034 };
1035
1036 pinctrl_salt1_default: salt1_default {
1037 function = "SALT1";
1038 groups = "SALT1";
1039 };
1040
1041 pinctrl_salt2_default: salt2_default {
1042 function = "SALT2";
1043 groups = "SALT2";
1044 };
1045
1046 pinctrl_salt3_default: salt3_default {
1047 function = "SALT3";
1048 groups = "SALT3";
1049 };
1050
1051 pinctrl_salt4_default: salt4_default {
1052 function = "SALT4";
1053 groups = "SALT4";
1054 };
1055
1056 pinctrl_sd1_default: sd1_default {
1057 function = "SD1";
1058 groups = "SD1";
1059 };
1060
1061 pinctrl_sd2_default: sd2_default {
1062 function = "SD2";
1063 groups = "SD2";
1064 };
1065
1066 pinctrl_sgpmck_default: sgpmck_default {
1067 function = "SGPMCK";
1068 groups = "SGPMCK";
1069 };
1070
1071 pinctrl_sgpmi_default: sgpmi_default {
1072 function = "SGPMI";
1073 groups = "SGPMI";
1074 };
1075
1076 pinctrl_sgpmld_default: sgpmld_default {
1077 function = "SGPMLD";
1078 groups = "SGPMLD";
1079 };
1080
1081 pinctrl_sgpmo_default: sgpmo_default {
1082 function = "SGPMO";
1083 groups = "SGPMO";
1084 };
1085
1086 pinctrl_sgpsck_default: sgpsck_default {
1087 function = "SGPSCK";
1088 groups = "SGPSCK";
1089 };
1090
1091 pinctrl_sgpsi0_default: sgpsi0_default {
1092 function = "SGPSI0";
1093 groups = "SGPSI0";
1094 };
1095
1096 pinctrl_sgpsi1_default: sgpsi1_default {
1097 function = "SGPSI1";
1098 groups = "SGPSI1";
1099 };
1100
1101 pinctrl_sgpsld_default: sgpsld_default {
1102 function = "SGPSLD";
1103 groups = "SGPSLD";
1104 };
1105
1106 pinctrl_sioonctrl_default: sioonctrl_default {
1107 function = "SIOONCTRL";
1108 groups = "SIOONCTRL";
1109 };
1110
1111 pinctrl_siopbi_default: siopbi_default {
1112 function = "SIOPBI";
1113 groups = "SIOPBI";
1114 };
1115
1116 pinctrl_siopbo_default: siopbo_default {
1117 function = "SIOPBO";
1118 groups = "SIOPBO";
1119 };
1120
1121 pinctrl_siopwreq_default: siopwreq_default {
1122 function = "SIOPWREQ";
1123 groups = "SIOPWREQ";
1124 };
1125
1126 pinctrl_siopwrgd_default: siopwrgd_default {
1127 function = "SIOPWRGD";
1128 groups = "SIOPWRGD";
1129 };
1130
1131 pinctrl_sios3_default: sios3_default {
1132 function = "SIOS3";
1133 groups = "SIOS3";
1134 };
1135
1136 pinctrl_sios5_default: sios5_default {
1137 function = "SIOS5";
1138 groups = "SIOS5";
1139 };
1140
1141 pinctrl_siosci_default: siosci_default {
1142 function = "SIOSCI";
1143 groups = "SIOSCI";
1144 };
1145
1146 pinctrl_spi1_default: spi1_default {
1147 function = "SPI1";
1148 groups = "SPI1";
1149 };
1150
1151 pinctrl_spi1debug_default: spi1debug_default {
1152 function = "SPI1DEBUG";
1153 groups = "SPI1DEBUG";
1154 };
1155
1156 pinctrl_spi1passthru_default: spi1passthru_default {
1157 function = "SPI1PASSTHRU";
1158 groups = "SPI1PASSTHRU";
1159 };
1160
1161 pinctrl_spics1_default: spics1_default {
1162 function = "SPICS1";
1163 groups = "SPICS1";
1164 };
1165
1166 pinctrl_timer3_default: timer3_default {
1167 function = "TIMER3";
1168 groups = "TIMER3";
1169 };
1170
1171 pinctrl_timer4_default: timer4_default {
1172 function = "TIMER4";
1173 groups = "TIMER4";
1174 };
1175
1176 pinctrl_timer5_default: timer5_default {
1177 function = "TIMER5";
1178 groups = "TIMER5";
1179 };
1180
1181 pinctrl_timer6_default: timer6_default {
1182 function = "TIMER6";
1183 groups = "TIMER6";
1184 };
1185
1186 pinctrl_timer7_default: timer7_default {
1187 function = "TIMER7";
1188 groups = "TIMER7";
1189 };
1190
1191 pinctrl_timer8_default: timer8_default {
1192 function = "TIMER8";
1193 groups = "TIMER8";
1194 };
1195
1196 pinctrl_txd1_default: txd1_default {
1197 function = "TXD1";
1198 groups = "TXD1";
1199 };
1200
1201 pinctrl_txd2_default: txd2_default {
1202 function = "TXD2";
1203 groups = "TXD2";
1204 };
1205
1206 pinctrl_txd3_default: txd3_default {
1207 function = "TXD3";
1208 groups = "TXD3";
1209 };
1210
1211 pinctrl_txd4_default: txd4_default {
1212 function = "TXD4";
1213 groups = "TXD4";
1214 };
1215
1216 pinctrl_uart6_default: uart6_default {
1217 function = "UART6";
1218 groups = "UART6";
1219 };
1220
1221 pinctrl_usbcki_default: usbcki_default {
1222 function = "USBCKI";
1223 groups = "USBCKI";
1224 };
1225
1226 pinctrl_vgabios_rom_default: vgabios_rom_default {
1227 function = "VGABIOS_ROM";
1228 groups = "VGABIOS_ROM";
1229 };
1230
1231 pinctrl_vgahs_default: vgahs_default {
1232 function = "VGAHS";
1233 groups = "VGAHS";
1234 };
1235
1236 pinctrl_vgavs_default: vgavs_default {
1237 function = "VGAVS";
1238 groups = "VGAVS";
1239 };
1240
1241 pinctrl_vpi18_default: vpi18_default {
1242 function = "VPI18";
1243 groups = "VPI18";
1244 };
1245
1246 pinctrl_vpi24_default: vpi24_default {
1247 function = "VPI24";
1248 groups = "VPI24";
1249 };
1250
1251 pinctrl_vpi30_default: vpi30_default {
1252 function = "VPI30";
1253 groups = "VPI30";
1254 };
1255
1256 pinctrl_vpo12_default: vpo12_default {
1257 function = "VPO12";
1258 groups = "VPO12";
1259 };
1260
1261 pinctrl_vpo24_default: vpo24_default {
1262 function = "VPO24";
1263 groups = "VPO24";
1264 };
1265
1266 pinctrl_wdtrst1_default: wdtrst1_default {
1267 function = "WDTRST1";
1268 groups = "WDTRST1";
1269 };
1270
1271 pinctrl_wdtrst2_default: wdtrst2_default {
1272 function = "WDTRST2";
1273 groups = "WDTRST2";
1274 };
1275};
Linux 6.x block layer and io_uring tree(s)