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Linux 4.18-rc2
[linux-2.6-block.git] / arch / arm / boot / dts / aspeed-g4.dtsi
CommitLineData
eb323ad0 1// SPDX-License-Identifier: GPL-2.0+
bb8155ad 2#include <dt-bindings/clock/aspeed-clock.h>
d44a1138
JS		 3
4/ {
5 model = "Aspeed BMC";
6 compatible = "aspeed,ast2400";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
10
ef856378
JS		 11 aliases {
12 i2c0 = &i2c0;
13 i2c1 = &i2c1;
14 i2c2 = &i2c2;
15 i2c3 = &i2c3;
16 i2c4 = &i2c4;
17 i2c5 = &i2c5;
18 i2c6 = &i2c6;
19 i2c7 = &i2c7;
20 i2c8 = &i2c8;
21 i2c9 = &i2c9;
22 i2c10 = &i2c10;
23 i2c11 = &i2c11;
24 i2c12 = &i2c12;
25 i2c13 = &i2c13;
0bae3904
JS		 26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 serial4 = &uart5;
a19331ca 31 serial5 = &vuart;
ef856378
JS		 32 };
33
d44a1138
JS		 34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
41 reg = <0>;
42 };
43 };
44
9bdc00a5
JS		 45 memory@40000000 {
46 device_type = "memory";
47 reg = <0x40000000 0>;
48 };
49
d44a1138
JS		 50 ahb {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55
74dc3cd3
CLG		 56 fmc: flash-controller@1e620000 {
57 reg = < 0x1e620000 0x94
bcbd328d 58 0x20000000 0x10000000 >;
74dc3cd3
CLG		 59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "aspeed,ast2400-fmc";
e1e0ec41 62 clocks = <&syscon ASPEED_CLK_AHB>;
74dc3cd3
CLG		 63 status = "disabled";
64 interrupts = <19>;
65 flash@0 {
66 reg = < 0 >;
67 compatible = "jedec,spi-nor";
68 status = "disabled";
69 };
70 };
71
72 spi: flash-controller@1e630000 {
73 reg = < 0x1e630000 0x18
bcbd328d 74 0x30000000 0x10000000 >;
74dc3cd3
CLG		 75 #address-cells = <1>;
76 #size-cells = <0>;
77 compatible = "aspeed,ast2400-spi";
e1e0ec41 78 clocks = <&syscon ASPEED_CLK_AHB>;
74dc3cd3
CLG		 79 status = "disabled";
80 flash@0 {
81 reg = < 0 >;
82 compatible = "jedec,spi-nor";
83 status = "disabled";
84 };
85 };
86
d44a1138
JS		 87 vic: interrupt-controller@1e6c0080 {
88 compatible = "aspeed,ast2400-vic";
89 interrupt-controller;
90 #interrupt-cells = <1>;
91 valid-sources = <0xffffffff 0x0007ffff>;
92 reg = <0x1e6c0080 0x80>;
93 };
94
34ea5c9d 95 mac0: ethernet@1e660000 {
78d28543 96 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
34ea5c9d
JS		 97 reg = <0x1e660000 0x180>;
98 interrupts = <2>;
deb95c59 99 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
34ea5c9d
JS		 100 status = "disabled";
101 };
102
103 mac1: ethernet@1e680000 {
78d28543 104 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
34ea5c9d
JS		 105 reg = <0x1e680000 0x180>;
106 interrupts = <3>;
deb95c59 107 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
34ea5c9d
JS		 108 status = "disabled";
109 };
110
ac6e31d3
BH		 111 ehci0: usb@1e6a1000 {
112 compatible = "aspeed,ast2400-ehci", "generic-ehci";
113 reg = <0x1e6a1000 0x100>;
114 interrupts = <5>;
115 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
116 status = "disabled";
117 };
118
119 uhci: usb@1e6b0000 {
120 compatible = "aspeed,ast2400-uhci", "generic-uhci";
121 reg = <0x1e6b0000 0x100>;
122 interrupts = <14>;
123 #ports = <3>;
124 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
125 status = "disabled";
126 };
127
d44a1138
JS		 128 apb {
129 compatible = "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 ranges;
133
d9072279 134 syscon: syscon@1e6e2000 {
bb8155ad 135 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
d9072279 136 reg = <0x1e6e2000 0x1a8>;
491bdcfa
JS		 137 #address-cells = <1>;
138 #size-cells = <0>;
bb8155ad
JS		 139 #clock-cells = <1>;
140 #reset-cells = <1>;
d9072279
AJ		 141
142 pinctrl: pinctrl {
143 compatible = "aspeed,g4-pinctrl";
d9072279 144 };
5daa8212
JS		 145
146 };
147
927c2fc2 148 rng: hwrng@1e6e2078 {
5daa8212 149 compatible = "timeriomem_rng";
927c2fc2 150 reg = <0x1e6e2078 0x4>;
5daa8212
JS		 151 period = <1>;
152 quality = <100>;
d9072279
AJ		 153 };
154
29b24640
JS		 155 adc: adc@1e6e9000 {
156 compatible = "aspeed,ast2400-adc";
157 reg = <0x1e6e9000 0xb0>;
bb8155ad
JS		 158 clocks = <&syscon ASPEED_CLK_APB>;
159 resets = <&syscon ASPEED_RESET_ADC>;
29b24640
JS		 160 #io-channel-cells = <1>;
161 status = "disabled";
162 };
163
d44a1138
JS		 164 sram@1e720000 {
165 compatible = "mmio-sram";
166 reg = <0x1e720000 0x8000>; // 32K
167 };
168
09955007
AJ		 169 gpio: gpio@1e780000 {
170 #gpio-cells = <2>;
171 gpio-controller;
172 compatible = "aspeed,ast2400-gpio";
173 reg = <0x1e780000 0x1000>;
174 interrupts = <20>;
175 gpio-ranges = <&pinctrl 0 0 220>;
2528be75 176 clocks = <&syscon ASPEED_CLK_APB>;
09955007
AJ		 177 interrupt-controller;
178 };
179
d44a1138 180 timer: timer@1e782000 {
f46b563f 181 /* This timer is a Faraday FTTMR010 derivative */
d44a1138
JS		 182 compatible = "aspeed,ast2400-timer";
183 reg = <0x1e782000 0x90>;
f46b563f 184 interrupts = <16 17 18 35 36 37 38 39>;
bb8155ad 185 clocks = <&syscon ASPEED_CLK_APB>;
f46b563f 186 clock-names = "PCLK";
d44a1138
JS		 187 };
188
d44a1138
JS		 189 uart1: serial@1e783000 {
190 compatible = "ns16550a";
a19331ca 191 reg = <0x1e783000 0x20>;
d44a1138
JS		 192 reg-shift = <2>;
193 interrupts = <9>;
bb8155ad 194 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
fd2de0a7 195 resets = <&lpc_reset 4>;
d44a1138
JS		 196 no-loopback-test;
197 status = "disabled";
198 };
199
db4d6d9d 200 uart5: serial@1e784000 {
d44a1138 201 compatible = "ns16550a";
a19331ca 202 reg = <0x1e784000 0x20>;
d44a1138 203 reg-shift = <2>;
db4d6d9d 204 interrupts = <10>;
bb8155ad 205 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
d44a1138
JS		 206 no-loopback-test;
207 status = "disabled";
208 };
209
424bd7e6 210 wdt1: watchdog@1e785000 {
23491da8 211 compatible = "aspeed,ast2400-wdt";
d44a1138 212 reg = <0x1e785000 0x1c>;
a563e192 213 clocks = <&syscon ASPEED_CLK_APB>;
d44a1138
JS		 214 };
215
424bd7e6 216 wdt2: watchdog@1e785020 {
23491da8 217 compatible = "aspeed,ast2400-wdt";
d44a1138 218 reg = <0x1e785020 0x1c>;
a563e192 219 clocks = <&syscon ASPEED_CLK_APB>;
d44a1138
JS		 220 };
221
0734089f
JS		 222 pwm_tacho: pwm-tacho-controller@1e786000 {
223 compatible = "aspeed,ast2400-pwm-tacho";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x1e786000 0x1000>;
227 clocks = <&syscon ASPEED_CLK_APB>;
228 resets = <&syscon ASPEED_RESET_PWM>;
229 status = "disabled";
230 };
231
a19331ca
JS		 232 vuart: serial@1e787000 {
233 compatible = "aspeed,ast2400-vuart";
234 reg = <0x1e787000 0x40>;
d44a1138 235 reg-shift = <2>;
bb8155ad
JS		 236 interrupts = <8>;
237 clocks = <&syscon ASPEED_CLK_APB>;
d44a1138
JS		 238 no-loopback-test;
239 status = "disabled";
240 };
241
b6436f76
AJ		 242 lpc: lpc@1e789000 {
243 compatible = "aspeed,ast2400-lpc", "simple-mfd";
244 reg = <0x1e789000 0x1000>;
245
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0x0 0x1e789000 0x1000>;
249
250 lpc_bmc: lpc-bmc@0 {
251 compatible = "aspeed,ast2400-lpc-bmc";
252 reg = <0x0 0x80>;
253 };
254
255 lpc_host: lpc-host@80 {
256 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
257 reg = <0x80 0x1e0>;
258 reg-io-width = <4>;
259
260 #address-cells = <1>;
261 #size-cells = <1>;
262 ranges = <0x0 0x80 0x1e0>;
263
264 lpc_ctrl: lpc-ctrl@0 {
265 compatible = "aspeed,ast2400-lpc-ctrl";
266 reg = <0x0 0x80>;
7674bf96 267 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
b6436f76
AJ		 268 status = "disabled";
269 };
270
d558ce0f
JS		 271 lpc_snoop: lpc-snoop@0 {
272 compatible = "aspeed,ast2400-lpc-snoop";
273 reg = <0x0 0x80>;
274 interrupts = <8>;
275 status = "disabled";
276 };
277
b6436f76
AJ		 278 lhc: lhc@20 {
279 compatible = "aspeed,ast2400-lhc";
280 reg = <0x20 0x24 0x48 0x8>;
281 };
75b310b7 282
fd2de0a7
JS		 283 lpc_reset: reset-controller@18 {
284 compatible = "aspeed,ast2400-lpc-reset";
285 reg = <0x18 0x4>;
286 #reset-cells = <1>;
287 };
288
75b310b7
JS		 289 ibt: ibt@c0 {
290 compatible = "aspeed,ast2400-ibt-bmc";
291 reg = <0xc0 0x18>;
292 interrupts = <8>;
293 status = "disabled";
294 };
b6436f76
AJ		 295 };
296 };
297
d44a1138 298 uart2: serial@1e78d000 {
d44a1138 299 compatible = "ns16550a";
a19331ca 300 reg = <0x1e78d000 0x20>;
d44a1138 301 reg-shift = <2>;
d44a1138 302 interrupts = <32>;
bb8155ad 303 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
fd2de0a7 304 resets = <&lpc_reset 5>;
d44a1138
JS		 305 no-loopback-test;
306 status = "disabled";
307 };
308
d44a1138 309 uart3: serial@1e78e000 {
d44a1138 310 compatible = "ns16550a";
a19331ca 311 reg = <0x1e78e000 0x20>;
d44a1138 312 reg-shift = <2>;
d44a1138 313 interrupts = <33>;
bb8155ad 314 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
fd2de0a7 315 resets = <&lpc_reset 6>;
d44a1138
JS		 316 no-loopback-test;
317 status = "disabled";
318 };
319
d44a1138 320 uart4: serial@1e78f000 {
d44a1138 321 compatible = "ns16550a";
a19331ca 322 reg = <0x1e78f000 0x20>;
d44a1138 323 reg-shift = <2>;
d44a1138 324 interrupts = <34>;
bb8155ad 325 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
fd2de0a7 326 resets = <&lpc_reset 7>;
d44a1138
JS		 327 no-loopback-test;
328 status = "disabled";
329 };
78a2569f 330
ef856378
JS		 331 i2c: i2c@1e78a000 {
332 compatible = "simple-bus";
333 #address-cells = <1>;
334 #size-cells = <1>;
335 ranges = <0 0x1e78a000 0x1000>;
78a2569f 336 };
d44a1138
JS		 337 };
338 };
339};
cd7df3f7 340
ef856378
JS		 341&i2c {
342 i2c_ic: interrupt-controller@0 {
343 #interrupt-cells = <1>;
344 compatible = "aspeed,ast2400-i2c-ic";
345 reg = <0x0 0x40>;
346 interrupts = <12>;
347 interrupt-controller;
348 };
349
350 i2c0: i2c-bus@40 {
351 #address-cells = <1>;
352 #size-cells = <0>;
353 #interrupt-cells = <1>;
354
355 reg = <0x40 0x40>;
356 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 357 clocks = <&syscon ASPEED_CLK_APB>;
358 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 359 bus-frequency = <100000>;
360 interrupts = <0>;
361 interrupt-parent = <&i2c_ic>;
362 status = "disabled";
363 /* Does not need pinctrl properties */
364 };
365
366 i2c1: i2c-bus@80 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 #interrupt-cells = <1>;
370
371 reg = <0x80 0x40>;
372 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 373 clocks = <&syscon ASPEED_CLK_APB>;
374 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 375 bus-frequency = <100000>;
376 interrupts = <1>;
377 interrupt-parent = <&i2c_ic>;
378 status = "disabled";
379 /* Does not need pinctrl properties */
380 };
381
382 i2c2: i2c-bus@c0 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 #interrupt-cells = <1>;
386
387 reg = <0xc0 0x40>;
388 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 389 clocks = <&syscon ASPEED_CLK_APB>;
390 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 391 bus-frequency = <100000>;
392 interrupts = <2>;
393 interrupt-parent = <&i2c_ic>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_i2c3_default>;
396 status = "disabled";
397 };
398
399 i2c3: i2c-bus@100 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 #interrupt-cells = <1>;
403
404 reg = <0x100 0x40>;
405 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 406 clocks = <&syscon ASPEED_CLK_APB>;
407 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 408 bus-frequency = <100000>;
409 interrupts = <3>;
410 interrupt-parent = <&i2c_ic>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_i2c4_default>;
413 status = "disabled";
414 };
415
416 i2c4: i2c-bus@140 {
417 #address-cells = <1>;
418 #size-cells = <0>;
419 #interrupt-cells = <1>;
420
421 reg = <0x140 0x40>;
422 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 423 clocks = <&syscon ASPEED_CLK_APB>;
424 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 425 bus-frequency = <100000>;
426 interrupts = <4>;
427 interrupt-parent = <&i2c_ic>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_i2c5_default>;
430 status = "disabled";
431 };
432
433 i2c5: i2c-bus@180 {
434 #address-cells = <1>;
435 #size-cells = <0>;
436 #interrupt-cells = <1>;
437
438 reg = <0x180 0x40>;
439 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 440 clocks = <&syscon ASPEED_CLK_APB>;
441 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 442 bus-frequency = <100000>;
443 interrupts = <5>;
444 interrupt-parent = <&i2c_ic>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_i2c6_default>;
447 status = "disabled";
448 };
449
450 i2c6: i2c-bus@1c0 {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 #interrupt-cells = <1>;
454
455 reg = <0x1c0 0x40>;
456 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 457 clocks = <&syscon ASPEED_CLK_APB>;
458 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 459 bus-frequency = <100000>;
460 interrupts = <6>;
461 interrupt-parent = <&i2c_ic>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_i2c7_default>;
464 status = "disabled";
465 };
466
467 i2c7: i2c-bus@300 {
468 #address-cells = <1>;
469 #size-cells = <0>;
470 #interrupt-cells = <1>;
471
472 reg = <0x300 0x40>;
473 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 474 clocks = <&syscon ASPEED_CLK_APB>;
475 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 476 bus-frequency = <100000>;
477 interrupts = <7>;
478 interrupt-parent = <&i2c_ic>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_i2c8_default>;
481 status = "disabled";
482 };
483
484 i2c8: i2c-bus@340 {
485 #address-cells = <1>;
486 #size-cells = <0>;
487 #interrupt-cells = <1>;
488
489 reg = <0x340 0x40>;
490 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 491 clocks = <&syscon ASPEED_CLK_APB>;
492 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 493 bus-frequency = <100000>;
494 interrupts = <8>;
495 interrupt-parent = <&i2c_ic>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_i2c9_default>;
498 status = "disabled";
499 };
500
501 i2c9: i2c-bus@380 {
502 #address-cells = <1>;
503 #size-cells = <0>;
504 #interrupt-cells = <1>;
505
506 reg = <0x380 0x40>;
507 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 508 clocks = <&syscon ASPEED_CLK_APB>;
509 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 510 bus-frequency = <100000>;
511 interrupts = <9>;
512 interrupt-parent = <&i2c_ic>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_i2c10_default>;
515 status = "disabled";
516 };
517
518 i2c10: i2c-bus@3c0 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 #interrupt-cells = <1>;
522
523 reg = <0x3c0 0x40>;
524 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 525 clocks = <&syscon ASPEED_CLK_APB>;
526 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 527 bus-frequency = <100000>;
528 interrupts = <10>;
529 interrupt-parent = <&i2c_ic>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_i2c11_default>;
532 status = "disabled";
533 };
534
535 i2c11: i2c-bus@400 {
536 #address-cells = <1>;
537 #size-cells = <0>;
538 #interrupt-cells = <1>;
539
540 reg = <0x400 0x40>;
541 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 542 clocks = <&syscon ASPEED_CLK_APB>;
543 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 544 bus-frequency = <100000>;
545 interrupts = <11>;
546 interrupt-parent = <&i2c_ic>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_i2c12_default>;
549 status = "disabled";
550 };
551
552 i2c12: i2c-bus@440 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 #interrupt-cells = <1>;
556
557 reg = <0x440 0x40>;
558 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 559 clocks = <&syscon ASPEED_CLK_APB>;
560 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 561 bus-frequency = <100000>;
562 interrupts = <12>;
563 interrupt-parent = <&i2c_ic>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&pinctrl_i2c13_default>;
566 status = "disabled";
567 };
568
569 i2c13: i2c-bus@480 {
570 #address-cells = <1>;
571 #size-cells = <0>;
572 #interrupt-cells = <1>;
573
574 reg = <0x480 0x40>;
575 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 576 clocks = <&syscon ASPEED_CLK_APB>;
577 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 578 bus-frequency = <100000>;
579 interrupts = <13>;
580 interrupt-parent = <&i2c_ic>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_i2c14_default>;
583 status = "disabled";
584 };
585};
586
cd7df3f7
AJ		 587&pinctrl {
588 pinctrl_acpi_default: acpi_default {
589 function = "ACPI";
590 groups = "ACPI";
591 };
592
593 pinctrl_adc0_default: adc0_default {
594 function = "ADC0";
595 groups = "ADC0";
596 };
597
598 pinctrl_adc1_default: adc1_default {
599 function = "ADC1";
600 groups = "ADC1";
601 };
602
603 pinctrl_adc10_default: adc10_default {
604 function = "ADC10";
605 groups = "ADC10";
606 };
607
608 pinctrl_adc11_default: adc11_default {
609 function = "ADC11";
610 groups = "ADC11";
611 };
612
613 pinctrl_adc12_default: adc12_default {
614 function = "ADC12";
615 groups = "ADC12";
616 };
617
618 pinctrl_adc13_default: adc13_default {
619 function = "ADC13";
620 groups = "ADC13";
621 };
622
623 pinctrl_adc14_default: adc14_default {
624 function = "ADC14";
625 groups = "ADC14";
626 };
627
628 pinctrl_adc15_default: adc15_default {
629 function = "ADC15";
630 groups = "ADC15";
631 };
632
633 pinctrl_adc2_default: adc2_default {
634 function = "ADC2";
635 groups = "ADC2";
636 };
637
638 pinctrl_adc3_default: adc3_default {
639 function = "ADC3";
640 groups = "ADC3";
641 };
642
643 pinctrl_adc4_default: adc4_default {
644 function = "ADC4";
645 groups = "ADC4";
646 };
647
648 pinctrl_adc5_default: adc5_default {
649 function = "ADC5";
650 groups = "ADC5";
651 };
652
653 pinctrl_adc6_default: adc6_default {
654 function = "ADC6";
655 groups = "ADC6";
656 };
657
658 pinctrl_adc7_default: adc7_default {
659 function = "ADC7";
660 groups = "ADC7";
661 };
662
663 pinctrl_adc8_default: adc8_default {
664 function = "ADC8";
665 groups = "ADC8";
666 };
667
668 pinctrl_adc9_default: adc9_default {
669 function = "ADC9";
670 groups = "ADC9";
671 };
672
673 pinctrl_bmcint_default: bmcint_default {
674 function = "BMCINT";
675 groups = "BMCINT";
676 };
677
678 pinctrl_ddcclk_default: ddcclk_default {
679 function = "DDCCLK";
680 groups = "DDCCLK";
681 };
682
683 pinctrl_ddcdat_default: ddcdat_default {
684 function = "DDCDAT";
685 groups = "DDCDAT";
686 };
687
688 pinctrl_extrst_default: extrst_default {
689 function = "EXTRST";
690 groups = "EXTRST";
691 };
692
693 pinctrl_flack_default: flack_default {
694 function = "FLACK";
695 groups = "FLACK";
696 };
697
698 pinctrl_flbusy_default: flbusy_default {
699 function = "FLBUSY";
700 groups = "FLBUSY";
701 };
702
703 pinctrl_flwp_default: flwp_default {
704 function = "FLWP";
705 groups = "FLWP";
706 };
707
708 pinctrl_gpid_default: gpid_default {
709 function = "GPID";
710 groups = "GPID";
711 };
712
713 pinctrl_gpid0_default: gpid0_default {
714 function = "GPID0";
715 groups = "GPID0";
716 };
717
718 pinctrl_gpid2_default: gpid2_default {
719 function = "GPID2";
720 groups = "GPID2";
721 };
722
723 pinctrl_gpid4_default: gpid4_default {
724 function = "GPID4";
725 groups = "GPID4";
726 };
727
728 pinctrl_gpid6_default: gpid6_default {
729 function = "GPID6";
730 groups = "GPID6";
731 };
732
733 pinctrl_gpie0_default: gpie0_default {
734 function = "GPIE0";
735 groups = "GPIE0";
736 };
737
738 pinctrl_gpie2_default: gpie2_default {
739 function = "GPIE2";
740 groups = "GPIE2";
741 };
742
743 pinctrl_gpie4_default: gpie4_default {
744 function = "GPIE4";
745 groups = "GPIE4";
746 };
747
748 pinctrl_gpie6_default: gpie6_default {
749 function = "GPIE6";
750 groups = "GPIE6";
751 };
752
753 pinctrl_i2c10_default: i2c10_default {
754 function = "I2C10";
755 groups = "I2C10";
756 };
757
758 pinctrl_i2c11_default: i2c11_default {
759 function = "I2C11";
760 groups = "I2C11";
761 };
762
763 pinctrl_i2c12_default: i2c12_default {
764 function = "I2C12";
765 groups = "I2C12";
766 };
767
768 pinctrl_i2c13_default: i2c13_default {
769 function = "I2C13";
770 groups = "I2C13";
771 };
772
773 pinctrl_i2c14_default: i2c14_default {
774 function = "I2C14";
775 groups = "I2C14";
776 };
777
778 pinctrl_i2c3_default: i2c3_default {
779 function = "I2C3";
780 groups = "I2C3";
781 };
782
783 pinctrl_i2c4_default: i2c4_default {
784 function = "I2C4";
785 groups = "I2C4";
786 };
787
788 pinctrl_i2c5_default: i2c5_default {
789 function = "I2C5";
790 groups = "I2C5";
791 };
792
793 pinctrl_i2c6_default: i2c6_default {
794 function = "I2C6";
795 groups = "I2C6";
796 };
797
798 pinctrl_i2c7_default: i2c7_default {
799 function = "I2C7";
800 groups = "I2C7";
801 };
802
803 pinctrl_i2c8_default: i2c8_default {
804 function = "I2C8";
805 groups = "I2C8";
806 };
807
808 pinctrl_i2c9_default: i2c9_default {
809 function = "I2C9";
810 groups = "I2C9";
811 };
812
813 pinctrl_lpcpd_default: lpcpd_default {
814 function = "LPCPD";
815 groups = "LPCPD";
816 };
817
818 pinctrl_lpcpme_default: lpcpme_default {
819 function = "LPCPME";
820 groups = "LPCPME";
821 };
822
823 pinctrl_lpcrst_default: lpcrst_default {
824 function = "LPCRST";
825 groups = "LPCRST";
826 };
827
828 pinctrl_lpcsmi_default: lpcsmi_default {
829 function = "LPCSMI";
830 groups = "LPCSMI";
831 };
832
833 pinctrl_mac1link_default: mac1link_default {
834 function = "MAC1LINK";
835 groups = "MAC1LINK";
836 };
837
838 pinctrl_mac2link_default: mac2link_default {
839 function = "MAC2LINK";
840 groups = "MAC2LINK";
841 };
842
843 pinctrl_mdio1_default: mdio1_default {
844 function = "MDIO1";
845 groups = "MDIO1";
846 };
847
848 pinctrl_mdio2_default: mdio2_default {
849 function = "MDIO2";
850 groups = "MDIO2";
851 };
852
853 pinctrl_ncts1_default: ncts1_default {
854 function = "NCTS1";
855 groups = "NCTS1";
856 };
857
858 pinctrl_ncts2_default: ncts2_default {
859 function = "NCTS2";
860 groups = "NCTS2";
861 };
862
863 pinctrl_ncts3_default: ncts3_default {
864 function = "NCTS3";
865 groups = "NCTS3";
866 };
867
868 pinctrl_ncts4_default: ncts4_default {
869 function = "NCTS4";
870 groups = "NCTS4";
871 };
872
873 pinctrl_ndcd1_default: ndcd1_default {
874 function = "NDCD1";
875 groups = "NDCD1";
876 };
877
878 pinctrl_ndcd2_default: ndcd2_default {
879 function = "NDCD2";
880 groups = "NDCD2";
881 };
882
883 pinctrl_ndcd3_default: ndcd3_default {
884 function = "NDCD3";
885 groups = "NDCD3";
886 };
887
888 pinctrl_ndcd4_default: ndcd4_default {
889 function = "NDCD4";
890 groups = "NDCD4";
891 };
892
893 pinctrl_ndsr1_default: ndsr1_default {
894 function = "NDSR1";
895 groups = "NDSR1";
896 };
897
898 pinctrl_ndsr2_default: ndsr2_default {
899 function = "NDSR2";
900 groups = "NDSR2";
901 };
902
903 pinctrl_ndsr3_default: ndsr3_default {
904 function = "NDSR3";
905 groups = "NDSR3";
906 };
907
908 pinctrl_ndsr4_default: ndsr4_default {
909 function = "NDSR4";
910 groups = "NDSR4";
911 };
912
913 pinctrl_ndtr1_default: ndtr1_default {
914 function = "NDTR1";
915 groups = "NDTR1";
916 };
917
918 pinctrl_ndtr2_default: ndtr2_default {
919 function = "NDTR2";
920 groups = "NDTR2";
921 };
922
923 pinctrl_ndtr3_default: ndtr3_default {
924 function = "NDTR3";
925 groups = "NDTR3";
926 };
927
928 pinctrl_ndtr4_default: ndtr4_default {
929 function = "NDTR4";
930 groups = "NDTR4";
931 };
932
933 pinctrl_ndts4_default: ndts4_default {
934 function = "NDTS4";
935 groups = "NDTS4";
936 };
937
938 pinctrl_nri1_default: nri1_default {
939 function = "NRI1";
940 groups = "NRI1";
941 };
942
943 pinctrl_nri2_default: nri2_default {
944 function = "NRI2";
945 groups = "NRI2";
946 };
947
948 pinctrl_nri3_default: nri3_default {
949 function = "NRI3";
950 groups = "NRI3";
951 };
952
953 pinctrl_nri4_default: nri4_default {
954 function = "NRI4";
955 groups = "NRI4";
956 };
957
958 pinctrl_nrts1_default: nrts1_default {
959 function = "NRTS1";
960 groups = "NRTS1";
961 };
962
963 pinctrl_nrts2_default: nrts2_default {
964 function = "NRTS2";
965 groups = "NRTS2";
966 };
967
968 pinctrl_nrts3_default: nrts3_default {
969 function = "NRTS3";
970 groups = "NRTS3";
971 };
972
973 pinctrl_oscclk_default: oscclk_default {
974 function = "OSCCLK";
975 groups = "OSCCLK";
976 };
977
978 pinctrl_pwm0_default: pwm0_default {
979 function = "PWM0";
980 groups = "PWM0";
981 };
982
983 pinctrl_pwm1_default: pwm1_default {
984 function = "PWM1";
985 groups = "PWM1";
986 };
987
988 pinctrl_pwm2_default: pwm2_default {
989 function = "PWM2";
990 groups = "PWM2";
991 };
992
993 pinctrl_pwm3_default: pwm3_default {
994 function = "PWM3";
995 groups = "PWM3";
996 };
997
998 pinctrl_pwm4_default: pwm4_default {
999 function = "PWM4";
1000 groups = "PWM4";
1001 };
1002
1003 pinctrl_pwm5_default: pwm5_default {
1004 function = "PWM5";
1005 groups = "PWM5";
1006 };
1007
1008 pinctrl_pwm6_default: pwm6_default {
1009 function = "PWM6";
1010 groups = "PWM6";
1011 };
1012
1013 pinctrl_pwm7_default: pwm7_default {
1014 function = "PWM7";
1015 groups = "PWM7";
1016 };
1017
1018 pinctrl_rgmii1_default: rgmii1_default {
1019 function = "RGMII1";
1020 groups = "RGMII1";
1021 };
1022
1023 pinctrl_rgmii2_default: rgmii2_default {
1024 function = "RGMII2";
1025 groups = "RGMII2";
1026 };
1027
1028 pinctrl_rmii1_default: rmii1_default {
1029 function = "RMII1";
1030 groups = "RMII1";
1031 };
1032
1033 pinctrl_rmii2_default: rmii2_default {
1034 function = "RMII2";
1035 groups = "RMII2";
1036 };
1037
1038 pinctrl_rom16_default: rom16_default {
1039 function = "ROM16";
1040 groups = "ROM16";
1041 };
1042
1043 pinctrl_rom8_default: rom8_default {
1044 function = "ROM8";
1045 groups = "ROM8";
1046 };
1047
1048 pinctrl_romcs1_default: romcs1_default {
1049 function = "ROMCS1";
1050 groups = "ROMCS1";
1051 };
1052
1053 pinctrl_romcs2_default: romcs2_default {
1054 function = "ROMCS2";
1055 groups = "ROMCS2";
1056 };
1057
1058 pinctrl_romcs3_default: romcs3_default {
1059 function = "ROMCS3";
1060 groups = "ROMCS3";
1061 };
1062
1063 pinctrl_romcs4_default: romcs4_default {
1064 function = "ROMCS4";
1065 groups = "ROMCS4";
1066 };
1067
1068 pinctrl_rxd1_default: rxd1_default {
1069 function = "RXD1";
1070 groups = "RXD1";
1071 };
1072
1073 pinctrl_rxd2_default: rxd2_default {
1074 function = "RXD2";
1075 groups = "RXD2";
1076 };
1077
1078 pinctrl_rxd3_default: rxd3_default {
1079 function = "RXD3";
1080 groups = "RXD3";
1081 };
1082
1083 pinctrl_rxd4_default: rxd4_default {
1084 function = "RXD4";
1085 groups = "RXD4";
1086 };
1087
1088 pinctrl_salt1_default: salt1_default {
1089 function = "SALT1";
1090 groups = "SALT1";
1091 };
1092
1093 pinctrl_salt2_default: salt2_default {
1094 function = "SALT2";
1095 groups = "SALT2";
1096 };
1097
1098 pinctrl_salt3_default: salt3_default {
1099 function = "SALT3";
1100 groups = "SALT3";
1101 };
1102
1103 pinctrl_salt4_default: salt4_default {
1104 function = "SALT4";
1105 groups = "SALT4";
1106 };
1107
1108 pinctrl_sd1_default: sd1_default {
1109 function = "SD1";
1110 groups = "SD1";
1111 };
1112
1113 pinctrl_sd2_default: sd2_default {
1114 function = "SD2";
1115 groups = "SD2";
1116 };
1117
1118 pinctrl_sgpmck_default: sgpmck_default {
1119 function = "SGPMCK";
1120 groups = "SGPMCK";
1121 };
1122
1123 pinctrl_sgpmi_default: sgpmi_default {
1124 function = "SGPMI";
1125 groups = "SGPMI";
1126 };
1127
1128 pinctrl_sgpmld_default: sgpmld_default {
1129 function = "SGPMLD";
1130 groups = "SGPMLD";
1131 };
1132
1133 pinctrl_sgpmo_default: sgpmo_default {
1134 function = "SGPMO";
1135 groups = "SGPMO";
1136 };
1137
1138 pinctrl_sgpsck_default: sgpsck_default {
1139 function = "SGPSCK";
1140 groups = "SGPSCK";
1141 };
1142
1143 pinctrl_sgpsi0_default: sgpsi0_default {
1144 function = "SGPSI0";
1145 groups = "SGPSI0";
1146 };
1147
1148 pinctrl_sgpsi1_default: sgpsi1_default {
1149 function = "SGPSI1";
1150 groups = "SGPSI1";
1151 };
1152
1153 pinctrl_sgpsld_default: sgpsld_default {
1154 function = "SGPSLD";
1155 groups = "SGPSLD";
1156 };
1157
1158 pinctrl_sioonctrl_default: sioonctrl_default {
1159 function = "SIOONCTRL";
1160 groups = "SIOONCTRL";
1161 };
1162
1163 pinctrl_siopbi_default: siopbi_default {
1164 function = "SIOPBI";
1165 groups = "SIOPBI";
1166 };
1167
1168 pinctrl_siopbo_default: siopbo_default {
1169 function = "SIOPBO";
1170 groups = "SIOPBO";
1171 };
1172
1173 pinctrl_siopwreq_default: siopwreq_default {
1174 function = "SIOPWREQ";
1175 groups = "SIOPWREQ";
1176 };
1177
1178 pinctrl_siopwrgd_default: siopwrgd_default {
1179 function = "SIOPWRGD";
1180 groups = "SIOPWRGD";
1181 };
1182
1183 pinctrl_sios3_default: sios3_default {
1184 function = "SIOS3";
1185 groups = "SIOS3";
1186 };
1187
1188 pinctrl_sios5_default: sios5_default {
1189 function = "SIOS5";
1190 groups = "SIOS5";
1191 };
1192
1193 pinctrl_siosci_default: siosci_default {
1194 function = "SIOSCI";
1195 groups = "SIOSCI";
1196 };
1197
1198 pinctrl_spi1_default: spi1_default {
1199 function = "SPI1";
1200 groups = "SPI1";
1201 };
1202
1203 pinctrl_spi1debug_default: spi1debug_default {
1204 function = "SPI1DEBUG";
1205 groups = "SPI1DEBUG";
1206 };
1207
1208 pinctrl_spi1passthru_default: spi1passthru_default {
1209 function = "SPI1PASSTHRU";
1210 groups = "SPI1PASSTHRU";
1211 };
1212
1213 pinctrl_spics1_default: spics1_default {
1214 function = "SPICS1";
1215 groups = "SPICS1";
1216 };
1217
1218 pinctrl_timer3_default: timer3_default {
1219 function = "TIMER3";
1220 groups = "TIMER3";
1221 };
1222
1223 pinctrl_timer4_default: timer4_default {
1224 function = "TIMER4";
1225 groups = "TIMER4";
1226 };
1227
1228 pinctrl_timer5_default: timer5_default {
1229 function = "TIMER5";
1230 groups = "TIMER5";
1231 };
1232
1233 pinctrl_timer6_default: timer6_default {
1234 function = "TIMER6";
1235 groups = "TIMER6";
1236 };
1237
1238 pinctrl_timer7_default: timer7_default {
1239 function = "TIMER7";
1240 groups = "TIMER7";
1241 };
1242
1243 pinctrl_timer8_default: timer8_default {
1244 function = "TIMER8";
1245 groups = "TIMER8";
1246 };
1247
1248 pinctrl_txd1_default: txd1_default {
1249 function = "TXD1";
1250 groups = "TXD1";
1251 };
1252
1253 pinctrl_txd2_default: txd2_default {
1254 function = "TXD2";
1255 groups = "TXD2";
1256 };
1257
1258 pinctrl_txd3_default: txd3_default {
1259 function = "TXD3";
1260 groups = "TXD3";
1261 };
1262
1263 pinctrl_txd4_default: txd4_default {
1264 function = "TXD4";
1265 groups = "TXD4";
1266 };
1267
1268 pinctrl_uart6_default: uart6_default {
1269 function = "UART6";
1270 groups = "UART6";
1271 };
1272
1273 pinctrl_usbcki_default: usbcki_default {
1274 function = "USBCKI";
1275 groups = "USBCKI";
1276 };
1277
ac6e31d3
BH		 1278 pinctrl_usb2h_default: usb2h_default {
1279 function = "USB2H1";
1280 groups = "USB2H1";
1281 };
1282
1283 pinctrl_usb2d_default: usb2d_default {
1284 function = "USB2D1";
1285 groups = "USB2D1";
1286 };
1287
cd7df3f7
AJ		 1288 pinctrl_vgabios_rom_default: vgabios_rom_default {
1289 function = "VGABIOS_ROM";
1290 groups = "VGABIOS_ROM";
1291 };
1292
1293 pinctrl_vgahs_default: vgahs_default {
1294 function = "VGAHS";
1295 groups = "VGAHS";
1296 };
1297
1298 pinctrl_vgavs_default: vgavs_default {
1299 function = "VGAVS";
1300 groups = "VGAVS";
1301 };
1302
1303 pinctrl_vpi18_default: vpi18_default {
1304 function = "VPI18";
1305 groups = "VPI18";
1306 };
1307
1308 pinctrl_vpi24_default: vpi24_default {
1309 function = "VPI24";
1310 groups = "VPI24";
1311 };
1312
1313 pinctrl_vpi30_default: vpi30_default {
1314 function = "VPI30";
1315 groups = "VPI30";
1316 };
1317
1318 pinctrl_vpo12_default: vpo12_default {
1319 function = "VPO12";
1320 groups = "VPO12";
1321 };
1322
1323 pinctrl_vpo24_default: vpo24_default {
1324 function = "VPO24";
1325 groups = "VPO24";
1326 };
1327
1328 pinctrl_wdtrst1_default: wdtrst1_default {
1329 function = "WDTRST1";
1330 groups = "WDTRST1";
1331 };
1332
1333 pinctrl_wdtrst2_default: wdtrst2_default {
1334 function = "WDTRST2";
1335 groups = "WDTRST2";
1336 };
1337};
Linux 6.x block layer and io_uring tree(s)