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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/livepatchin...
[linux-block.git] / arch / arm / boot / dts / aspeed-g4.dtsi
CommitLineData
eb323ad0 1// SPDX-License-Identifier: GPL-2.0+
bb8155ad 2#include <dt-bindings/clock/aspeed-clock.h>
d44a1138
JS		 3
4/ {
5 model = "Aspeed BMC";
6 compatible = "aspeed,ast2400";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
10
ef856378
JS		 11 aliases {
12 i2c0 = &i2c0;
13 i2c1 = &i2c1;
14 i2c2 = &i2c2;
15 i2c3 = &i2c3;
16 i2c4 = &i2c4;
17 i2c5 = &i2c5;
18 i2c6 = &i2c6;
19 i2c7 = &i2c7;
20 i2c8 = &i2c8;
21 i2c9 = &i2c9;
22 i2c10 = &i2c10;
23 i2c11 = &i2c11;
24 i2c12 = &i2c12;
25 i2c13 = &i2c13;
0bae3904
JS		 26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 serial4 = &uart5;
a19331ca 31 serial5 = &vuart;
ef856378
JS		 32 };
33
d44a1138
JS		 34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
41 reg = <0>;
42 };
43 };
44
9bdc00a5
JS		 45 memory@40000000 {
46 device_type = "memory";
47 reg = <0x40000000 0>;
48 };
49
d44a1138
JS		 50 ahb {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55
459a6a2f 56 fmc: spi@1e620000 {
74dc3cd3 57 reg = < 0x1e620000 0x94
bcbd328d 58 0x20000000 0x10000000 >;
74dc3cd3
CLG		 59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "aspeed,ast2400-fmc";
e1e0ec41 62 clocks = <&syscon ASPEED_CLK_AHB>;
74dc3cd3
CLG		 63 status = "disabled";
64 interrupts = <19>;
65 flash@0 {
66 reg = < 0 >;
67 compatible = "jedec,spi-nor";
876c5d89 68 spi-max-frequency = <50000000>;
74dc3cd3
CLG		 69 status = "disabled";
70 };
901d5143
JS		 71 flash@1 {
72 reg = < 1 >;
73 compatible = "jedec,spi-nor";
74 status = "disabled";
75 };
76 flash@2 {
77 reg = < 2 >;
78 compatible = "jedec,spi-nor";
79 status = "disabled";
80 };
81 flash@3 {
82 reg = < 3 >;
83 compatible = "jedec,spi-nor";
84 status = "disabled";
85 };
86 flash@4 {
87 reg = < 4 >;
88 compatible = "jedec,spi-nor";
89 status = "disabled";
90 };
74dc3cd3
CLG		 91 };
92
459a6a2f 93 spi: spi@1e630000 {
74dc3cd3 94 reg = < 0x1e630000 0x18
bcbd328d 95 0x30000000 0x10000000 >;
74dc3cd3
CLG		 96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "aspeed,ast2400-spi";
e1e0ec41 99 clocks = <&syscon ASPEED_CLK_AHB>;
74dc3cd3
CLG		 100 status = "disabled";
101 flash@0 {
102 reg = < 0 >;
103 compatible = "jedec,spi-nor";
876c5d89 104 spi-max-frequency = <50000000>;
74dc3cd3
CLG		 105 status = "disabled";
106 };
107 };
108
d44a1138
JS		 109 vic: interrupt-controller@1e6c0080 {
110 compatible = "aspeed,ast2400-vic";
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 valid-sources = <0xffffffff 0x0007ffff>;
114 reg = <0x1e6c0080 0x80>;
115 };
116
2450ceaf
BH		 117 cvic: copro-interrupt-controller@1e6c2000 {
118 compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
119 valid-sources = <0x7fffffff>;
120 reg = <0x1e6c2000 0x80>;
121 };
122
34ea5c9d 123 mac0: ethernet@1e660000 {
78d28543 124 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
34ea5c9d
JS		 125 reg = <0x1e660000 0x180>;
126 interrupts = <2>;
deb95c59 127 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
34ea5c9d
JS		 128 status = "disabled";
129 };
130
131 mac1: ethernet@1e680000 {
78d28543 132 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
34ea5c9d
JS		 133 reg = <0x1e680000 0x180>;
134 interrupts = <3>;
deb95c59 135 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
34ea5c9d
JS		 136 status = "disabled";
137 };
138
ac6e31d3
BH		 139 ehci0: usb@1e6a1000 {
140 compatible = "aspeed,ast2400-ehci", "generic-ehci";
141 reg = <0x1e6a1000 0x100>;
142 interrupts = <5>;
143 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
c282ea74
BH		 144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_usb2h_default>;
ac6e31d3
BH		 146 status = "disabled";
147 };
148
149 uhci: usb@1e6b0000 {
150 compatible = "aspeed,ast2400-uhci", "generic-uhci";
151 reg = <0x1e6b0000 0x100>;
152 interrupts = <14>;
153 #ports = <3>;
154 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
155 status = "disabled";
c282ea74
BH		 156 /*
157 * No default pinmux, it will follow EHCI, use an explicit pinmux
158 * override if you don't enable EHCI
159 */
ac6e31d3
BH		 160 };
161
608d05c6
BH		 162 vhub: usb-vhub@1e6a0000 {
163 compatible = "aspeed,ast2400-usb-vhub";
164 reg = <0x1e6a0000 0x300>;
165 interrupts = <5>;
166 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_usb2d_default>;
169 status = "disabled";
170 };
171
d44a1138
JS		 172 apb {
173 compatible = "simple-bus";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 ranges;
177
d9072279 178 syscon: syscon@1e6e2000 {
bb8155ad 179 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
d9072279 180 reg = <0x1e6e2000 0x1a8>;
491bdcfa
JS		 181 #address-cells = <1>;
182 #size-cells = <0>;
bb8155ad
JS		 183 #clock-cells = <1>;
184 #reset-cells = <1>;
d9072279
AJ		 185
186 pinctrl: pinctrl {
b46aaf8a 187 compatible = "aspeed,ast2400-pinctrl";
d9072279 188 };
5daa8212 189
0215e2a5
PV		 190 p2a: p2a-control {
191 compatible = "aspeed,ast2400-p2a-ctrl";
192 status = "disabled";
193 };
5daa8212
JS		 194 };
195
927c2fc2 196 rng: hwrng@1e6e2078 {
5daa8212 197 compatible = "timeriomem_rng";
927c2fc2 198 reg = <0x1e6e2078 0x4>;
5daa8212
JS		 199 period = <1>;
200 quality = <100>;
d9072279
AJ		 201 };
202
29b24640
JS		 203 adc: adc@1e6e9000 {
204 compatible = "aspeed,ast2400-adc";
205 reg = <0x1e6e9000 0xb0>;
bb8155ad
JS		 206 clocks = <&syscon ASPEED_CLK_APB>;
207 resets = <&syscon ASPEED_RESET_ADC>;
29b24640
JS		 208 #io-channel-cells = <1>;
209 status = "disabled";
210 };
211
2450ceaf 212 sram: sram@1e720000 {
d44a1138
JS		 213 compatible = "mmio-sram";
214 reg = <0x1e720000 0x8000>; // 32K
215 };
216
c3522795
AJ		 217 sdmmc: sd-controller@1e740000 {
218 compatible = "aspeed,ast2400-sd-controller";
219 reg = <0x1e740000 0x100>;
220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges = <0 0x1e740000 0x10000>;
223 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
224 status = "disabled";
225
226 sdhci0: sdhci@100 {
227 compatible = "aspeed,ast2400-sdhci";
228 reg = <0x100 0x100>;
229 interrupts = <26>;
230 sdhci,auto-cmd12;
231 clocks = <&syscon ASPEED_CLK_SDIO>;
232 status = "disabled";
233 };
234
235 sdhci1: sdhci@200 {
236 compatible = "aspeed,ast2400-sdhci";
237 reg = <0x200 0x100>;
238 interrupts = <26>;
239 sdhci,auto-cmd12;
240 clocks = <&syscon ASPEED_CLK_SDIO>;
241 status = "disabled";
242 };
243 };
244
09955007
AJ		 245 gpio: gpio@1e780000 {
246 #gpio-cells = <2>;
247 gpio-controller;
248 compatible = "aspeed,ast2400-gpio";
249 reg = <0x1e780000 0x1000>;
250 interrupts = <20>;
251 gpio-ranges = <&pinctrl 0 0 220>;
2528be75 252 clocks = <&syscon ASPEED_CLK_APB>;
09955007 253 interrupt-controller;
8b880293 254 #interrupt-cells = <2>;
09955007
AJ		 255 };
256
d44a1138 257 timer: timer@1e782000 {
f46b563f 258 /* This timer is a Faraday FTTMR010 derivative */
d44a1138
JS		 259 compatible = "aspeed,ast2400-timer";
260 reg = <0x1e782000 0x90>;
f46b563f 261 interrupts = <16 17 18 35 36 37 38 39>;
bb8155ad 262 clocks = <&syscon ASPEED_CLK_APB>;
f46b563f 263 clock-names = "PCLK";
d44a1138 264 };
6d00c6f8
JS		 265
266 rtc: rtc@1e781000 {
267 compatible = "aspeed,ast2400-rtc";
268 reg = <0x1e781000 0x18>;
269 status = "disabled";
270 };
d44a1138 271
d44a1138
JS		 272 uart1: serial@1e783000 {
273 compatible = "ns16550a";
a19331ca 274 reg = <0x1e783000 0x20>;
d44a1138
JS		 275 reg-shift = <2>;
276 interrupts = <9>;
bb8155ad 277 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
fd2de0a7 278 resets = <&lpc_reset 4>;
d44a1138
JS		 279 no-loopback-test;
280 status = "disabled";
281 };
282
db4d6d9d 283 uart5: serial@1e784000 {
d44a1138 284 compatible = "ns16550a";
a19331ca 285 reg = <0x1e784000 0x20>;
d44a1138 286 reg-shift = <2>;
db4d6d9d 287 interrupts = <10>;
bb8155ad 288 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
d44a1138
JS		 289 no-loopback-test;
290 status = "disabled";
291 };
292
424bd7e6 293 wdt1: watchdog@1e785000 {
23491da8 294 compatible = "aspeed,ast2400-wdt";
d44a1138 295 reg = <0x1e785000 0x1c>;
a563e192 296 clocks = <&syscon ASPEED_CLK_APB>;
d44a1138
JS		 297 };
298
424bd7e6 299 wdt2: watchdog@1e785020 {
23491da8 300 compatible = "aspeed,ast2400-wdt";
d44a1138 301 reg = <0x1e785020 0x1c>;
a563e192 302 clocks = <&syscon ASPEED_CLK_APB>;
d44a1138
JS		 303 };
304
0734089f
JS		 305 pwm_tacho: pwm-tacho-controller@1e786000 {
306 compatible = "aspeed,ast2400-pwm-tacho";
307 #address-cells = <1>;
308 #size-cells = <0>;
309 reg = <0x1e786000 0x1000>;
a2df75ab 310 clocks = <&syscon ASPEED_CLK_24M>;
0734089f
JS		 311 resets = <&syscon ASPEED_RESET_PWM>;
312 status = "disabled";
313 };
314
a19331ca
JS		 315 vuart: serial@1e787000 {
316 compatible = "aspeed,ast2400-vuart";
317 reg = <0x1e787000 0x40>;
d44a1138 318 reg-shift = <2>;
bb8155ad
JS		 319 interrupts = <8>;
320 clocks = <&syscon ASPEED_CLK_APB>;
d44a1138
JS		 321 no-loopback-test;
322 status = "disabled";
323 };
324
b6436f76
AJ		 325 lpc: lpc@1e789000 {
326 compatible = "aspeed,ast2400-lpc", "simple-mfd";
327 reg = <0x1e789000 0x1000>;
328
329 #address-cells = <1>;
330 #size-cells = <1>;
331 ranges = <0x0 0x1e789000 0x1000>;
332
333 lpc_bmc: lpc-bmc@0 {
334 compatible = "aspeed,ast2400-lpc-bmc";
335 reg = <0x0 0x80>;
336 };
337
338 lpc_host: lpc-host@80 {
339 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
340 reg = <0x80 0x1e0>;
341 reg-io-width = <4>;
342
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges = <0x0 0x80 0x1e0>;
346
347 lpc_ctrl: lpc-ctrl@0 {
348 compatible = "aspeed,ast2400-lpc-ctrl";
349 reg = <0x0 0x80>;
7674bf96 350 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
b6436f76
AJ		 351 status = "disabled";
352 };
353
d558ce0f
JS		 354 lpc_snoop: lpc-snoop@0 {
355 compatible = "aspeed,ast2400-lpc-snoop";
356 reg = <0x0 0x80>;
357 interrupts = <8>;
358 status = "disabled";
359 };
360
b6436f76
AJ		 361 lhc: lhc@20 {
362 compatible = "aspeed,ast2400-lhc";
363 reg = <0x20 0x24 0x48 0x8>;
364 };
75b310b7 365
fd2de0a7
JS		 366 lpc_reset: reset-controller@18 {
367 compatible = "aspeed,ast2400-lpc-reset";
368 reg = <0x18 0x4>;
369 #reset-cells = <1>;
370 };
371
75b310b7
JS		 372 ibt: ibt@c0 {
373 compatible = "aspeed,ast2400-ibt-bmc";
374 reg = <0xc0 0x18>;
375 interrupts = <8>;
376 status = "disabled";
377 };
b6436f76
AJ		 378 };
379 };
380
d44a1138 381 uart2: serial@1e78d000 {
d44a1138 382 compatible = "ns16550a";
a19331ca 383 reg = <0x1e78d000 0x20>;
d44a1138 384 reg-shift = <2>;
d44a1138 385 interrupts = <32>;
bb8155ad 386 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
fd2de0a7 387 resets = <&lpc_reset 5>;
d44a1138
JS		 388 no-loopback-test;
389 status = "disabled";
390 };
391
d44a1138 392 uart3: serial@1e78e000 {
d44a1138 393 compatible = "ns16550a";
a19331ca 394 reg = <0x1e78e000 0x20>;
d44a1138 395 reg-shift = <2>;
d44a1138 396 interrupts = <33>;
bb8155ad 397 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
fd2de0a7 398 resets = <&lpc_reset 6>;
d44a1138
JS		 399 no-loopback-test;
400 status = "disabled";
401 };
402
d44a1138 403 uart4: serial@1e78f000 {
d44a1138 404 compatible = "ns16550a";
a19331ca 405 reg = <0x1e78f000 0x20>;
d44a1138 406 reg-shift = <2>;
d44a1138 407 interrupts = <34>;
bb8155ad 408 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
fd2de0a7 409 resets = <&lpc_reset 7>;
d44a1138
JS		 410 no-loopback-test;
411 status = "disabled";
412 };
78a2569f 413
1426d40e 414 i2c: bus@1e78a000 {
ef856378
JS		 415 compatible = "simple-bus";
416 #address-cells = <1>;
417 #size-cells = <1>;
418 ranges = <0 0x1e78a000 0x1000>;
78a2569f 419 };
d44a1138
JS		 420 };
421 };
422};
cd7df3f7 423
ef856378
JS		 424&i2c {
425 i2c_ic: interrupt-controller@0 {
426 #interrupt-cells = <1>;
427 compatible = "aspeed,ast2400-i2c-ic";
428 reg = <0x0 0x40>;
429 interrupts = <12>;
430 interrupt-controller;
431 };
432
433 i2c0: i2c-bus@40 {
434 #address-cells = <1>;
435 #size-cells = <0>;
436 #interrupt-cells = <1>;
437
438 reg = <0x40 0x40>;
439 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 440 clocks = <&syscon ASPEED_CLK_APB>;
441 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 442 bus-frequency = <100000>;
443 interrupts = <0>;
444 interrupt-parent = <&i2c_ic>;
445 status = "disabled";
446 /* Does not need pinctrl properties */
447 };
448
449 i2c1: i2c-bus@80 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 #interrupt-cells = <1>;
453
454 reg = <0x80 0x40>;
455 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 456 clocks = <&syscon ASPEED_CLK_APB>;
457 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 458 bus-frequency = <100000>;
459 interrupts = <1>;
460 interrupt-parent = <&i2c_ic>;
461 status = "disabled";
462 /* Does not need pinctrl properties */
463 };
464
465 i2c2: i2c-bus@c0 {
466 #address-cells = <1>;
467 #size-cells = <0>;
468 #interrupt-cells = <1>;
469
470 reg = <0xc0 0x40>;
471 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 472 clocks = <&syscon ASPEED_CLK_APB>;
473 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 474 bus-frequency = <100000>;
475 interrupts = <2>;
476 interrupt-parent = <&i2c_ic>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_i2c3_default>;
479 status = "disabled";
480 };
481
482 i2c3: i2c-bus@100 {
483 #address-cells = <1>;
484 #size-cells = <0>;
485 #interrupt-cells = <1>;
486
487 reg = <0x100 0x40>;
488 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 489 clocks = <&syscon ASPEED_CLK_APB>;
490 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 491 bus-frequency = <100000>;
492 interrupts = <3>;
493 interrupt-parent = <&i2c_ic>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&pinctrl_i2c4_default>;
496 status = "disabled";
497 };
498
499 i2c4: i2c-bus@140 {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 #interrupt-cells = <1>;
503
504 reg = <0x140 0x40>;
505 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 506 clocks = <&syscon ASPEED_CLK_APB>;
507 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 508 bus-frequency = <100000>;
509 interrupts = <4>;
510 interrupt-parent = <&i2c_ic>;
511 pinctrl-names = "default";
512 pinctrl-0 = <&pinctrl_i2c5_default>;
513 status = "disabled";
514 };
515
516 i2c5: i2c-bus@180 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 #interrupt-cells = <1>;
520
521 reg = <0x180 0x40>;
522 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 523 clocks = <&syscon ASPEED_CLK_APB>;
524 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 525 bus-frequency = <100000>;
526 interrupts = <5>;
527 interrupt-parent = <&i2c_ic>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_i2c6_default>;
530 status = "disabled";
531 };
532
533 i2c6: i2c-bus@1c0 {
534 #address-cells = <1>;
535 #size-cells = <0>;
536 #interrupt-cells = <1>;
537
538 reg = <0x1c0 0x40>;
539 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 540 clocks = <&syscon ASPEED_CLK_APB>;
541 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 542 bus-frequency = <100000>;
543 interrupts = <6>;
544 interrupt-parent = <&i2c_ic>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_i2c7_default>;
547 status = "disabled";
548 };
549
550 i2c7: i2c-bus@300 {
551 #address-cells = <1>;
552 #size-cells = <0>;
553 #interrupt-cells = <1>;
554
555 reg = <0x300 0x40>;
556 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 557 clocks = <&syscon ASPEED_CLK_APB>;
558 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 559 bus-frequency = <100000>;
560 interrupts = <7>;
561 interrupt-parent = <&i2c_ic>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_i2c8_default>;
564 status = "disabled";
565 };
566
567 i2c8: i2c-bus@340 {
568 #address-cells = <1>;
569 #size-cells = <0>;
570 #interrupt-cells = <1>;
571
572 reg = <0x340 0x40>;
573 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 574 clocks = <&syscon ASPEED_CLK_APB>;
575 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 576 bus-frequency = <100000>;
577 interrupts = <8>;
578 interrupt-parent = <&i2c_ic>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&pinctrl_i2c9_default>;
581 status = "disabled";
582 };
583
584 i2c9: i2c-bus@380 {
585 #address-cells = <1>;
586 #size-cells = <0>;
587 #interrupt-cells = <1>;
588
589 reg = <0x380 0x40>;
590 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 591 clocks = <&syscon ASPEED_CLK_APB>;
592 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 593 bus-frequency = <100000>;
594 interrupts = <9>;
595 interrupt-parent = <&i2c_ic>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&pinctrl_i2c10_default>;
598 status = "disabled";
599 };
600
601 i2c10: i2c-bus@3c0 {
602 #address-cells = <1>;
603 #size-cells = <0>;
604 #interrupt-cells = <1>;
605
606 reg = <0x3c0 0x40>;
607 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 608 clocks = <&syscon ASPEED_CLK_APB>;
609 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 610 bus-frequency = <100000>;
611 interrupts = <10>;
612 interrupt-parent = <&i2c_ic>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&pinctrl_i2c11_default>;
615 status = "disabled";
616 };
617
618 i2c11: i2c-bus@400 {
619 #address-cells = <1>;
620 #size-cells = <0>;
621 #interrupt-cells = <1>;
622
623 reg = <0x400 0x40>;
624 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 625 clocks = <&syscon ASPEED_CLK_APB>;
626 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 627 bus-frequency = <100000>;
628 interrupts = <11>;
629 interrupt-parent = <&i2c_ic>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_i2c12_default>;
632 status = "disabled";
633 };
634
635 i2c12: i2c-bus@440 {
636 #address-cells = <1>;
637 #size-cells = <0>;
638 #interrupt-cells = <1>;
639
640 reg = <0x440 0x40>;
641 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 642 clocks = <&syscon ASPEED_CLK_APB>;
643 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 644 bus-frequency = <100000>;
645 interrupts = <12>;
646 interrupt-parent = <&i2c_ic>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&pinctrl_i2c13_default>;
649 status = "disabled";
650 };
651
652 i2c13: i2c-bus@480 {
653 #address-cells = <1>;
654 #size-cells = <0>;
655 #interrupt-cells = <1>;
656
657 reg = <0x480 0x40>;
658 compatible = "aspeed,ast2400-i2c-bus";
bb8155ad
JS		 659 clocks = <&syscon ASPEED_CLK_APB>;
660 resets = <&syscon ASPEED_RESET_I2C>;
ef856378
JS		 661 bus-frequency = <100000>;
662 interrupts = <13>;
663 interrupt-parent = <&i2c_ic>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&pinctrl_i2c14_default>;
666 status = "disabled";
667 };
668};
669
cd7df3f7
AJ		 670&pinctrl {
671 pinctrl_acpi_default: acpi_default {
672 function = "ACPI";
673 groups = "ACPI";
674 };
675
676 pinctrl_adc0_default: adc0_default {
677 function = "ADC0";
678 groups = "ADC0";
679 };
680
681 pinctrl_adc1_default: adc1_default {
682 function = "ADC1";
683 groups = "ADC1";
684 };
685
686 pinctrl_adc10_default: adc10_default {
687 function = "ADC10";
688 groups = "ADC10";
689 };
690
691 pinctrl_adc11_default: adc11_default {
692 function = "ADC11";
693 groups = "ADC11";
694 };
695
696 pinctrl_adc12_default: adc12_default {
697 function = "ADC12";
698 groups = "ADC12";
699 };
700
701 pinctrl_adc13_default: adc13_default {
702 function = "ADC13";
703 groups = "ADC13";
704 };
705
706 pinctrl_adc14_default: adc14_default {
707 function = "ADC14";
708 groups = "ADC14";
709 };
710
711 pinctrl_adc15_default: adc15_default {
712 function = "ADC15";
713 groups = "ADC15";
714 };
715
716 pinctrl_adc2_default: adc2_default {
717 function = "ADC2";
718 groups = "ADC2";
719 };
720
721 pinctrl_adc3_default: adc3_default {
722 function = "ADC3";
723 groups = "ADC3";
724 };
725
726 pinctrl_adc4_default: adc4_default {
727 function = "ADC4";
728 groups = "ADC4";
729 };
730
731 pinctrl_adc5_default: adc5_default {
732 function = "ADC5";
733 groups = "ADC5";
734 };
735
736 pinctrl_adc6_default: adc6_default {
737 function = "ADC6";
738 groups = "ADC6";
739 };
740
741 pinctrl_adc7_default: adc7_default {
742 function = "ADC7";
743 groups = "ADC7";
744 };
745
746 pinctrl_adc8_default: adc8_default {
747 function = "ADC8";
748 groups = "ADC8";
749 };
750
751 pinctrl_adc9_default: adc9_default {
752 function = "ADC9";
753 groups = "ADC9";
754 };
755
756 pinctrl_bmcint_default: bmcint_default {
757 function = "BMCINT";
758 groups = "BMCINT";
759 };
760
761 pinctrl_ddcclk_default: ddcclk_default {
762 function = "DDCCLK";
763 groups = "DDCCLK";
764 };
765
766 pinctrl_ddcdat_default: ddcdat_default {
767 function = "DDCDAT";
768 groups = "DDCDAT";
769 };
770
771 pinctrl_extrst_default: extrst_default {
772 function = "EXTRST";
773 groups = "EXTRST";
774 };
775
776 pinctrl_flack_default: flack_default {
777 function = "FLACK";
778 groups = "FLACK";
779 };
780
781 pinctrl_flbusy_default: flbusy_default {
782 function = "FLBUSY";
783 groups = "FLBUSY";
784 };
785
786 pinctrl_flwp_default: flwp_default {
787 function = "FLWP";
788 groups = "FLWP";
789 };
790
791 pinctrl_gpid_default: gpid_default {
792 function = "GPID";
793 groups = "GPID";
794 };
795
796 pinctrl_gpid0_default: gpid0_default {
797 function = "GPID0";
798 groups = "GPID0";
799 };
800
801 pinctrl_gpid2_default: gpid2_default {
802 function = "GPID2";
803 groups = "GPID2";
804 };
805
806 pinctrl_gpid4_default: gpid4_default {
807 function = "GPID4";
808 groups = "GPID4";
809 };
810
811 pinctrl_gpid6_default: gpid6_default {
812 function = "GPID6";
813 groups = "GPID6";
814 };
815
816 pinctrl_gpie0_default: gpie0_default {
817 function = "GPIE0";
818 groups = "GPIE0";
819 };
820
821 pinctrl_gpie2_default: gpie2_default {
822 function = "GPIE2";
823 groups = "GPIE2";
824 };
825
826 pinctrl_gpie4_default: gpie4_default {
827 function = "GPIE4";
828 groups = "GPIE4";
829 };
830
831 pinctrl_gpie6_default: gpie6_default {
832 function = "GPIE6";
833 groups = "GPIE6";
834 };
835
836 pinctrl_i2c10_default: i2c10_default {
837 function = "I2C10";
838 groups = "I2C10";
839 };
840
841 pinctrl_i2c11_default: i2c11_default {
842 function = "I2C11";
843 groups = "I2C11";
844 };
845
846 pinctrl_i2c12_default: i2c12_default {
847 function = "I2C12";
848 groups = "I2C12";
849 };
850
851 pinctrl_i2c13_default: i2c13_default {
852 function = "I2C13";
853 groups = "I2C13";
854 };
855
856 pinctrl_i2c14_default: i2c14_default {
857 function = "I2C14";
858 groups = "I2C14";
859 };
860
861 pinctrl_i2c3_default: i2c3_default {
862 function = "I2C3";
863 groups = "I2C3";
864 };
865
866 pinctrl_i2c4_default: i2c4_default {
867 function = "I2C4";
868 groups = "I2C4";
869 };
870
871 pinctrl_i2c5_default: i2c5_default {
872 function = "I2C5";
873 groups = "I2C5";
874 };
875
876 pinctrl_i2c6_default: i2c6_default {
877 function = "I2C6";
878 groups = "I2C6";
879 };
880
881 pinctrl_i2c7_default: i2c7_default {
882 function = "I2C7";
883 groups = "I2C7";
884 };
885
886 pinctrl_i2c8_default: i2c8_default {
887 function = "I2C8";
888 groups = "I2C8";
889 };
890
891 pinctrl_i2c9_default: i2c9_default {
892 function = "I2C9";
893 groups = "I2C9";
894 };
895
896 pinctrl_lpcpd_default: lpcpd_default {
897 function = "LPCPD";
898 groups = "LPCPD";
899 };
900
901 pinctrl_lpcpme_default: lpcpme_default {
902 function = "LPCPME";
903 groups = "LPCPME";
904 };
905
906 pinctrl_lpcrst_default: lpcrst_default {
907 function = "LPCRST";
908 groups = "LPCRST";
909 };
910
911 pinctrl_lpcsmi_default: lpcsmi_default {
912 function = "LPCSMI";
913 groups = "LPCSMI";
914 };
915
916 pinctrl_mac1link_default: mac1link_default {
917 function = "MAC1LINK";
918 groups = "MAC1LINK";
919 };
920
921 pinctrl_mac2link_default: mac2link_default {
922 function = "MAC2LINK";
923 groups = "MAC2LINK";
924 };
925
926 pinctrl_mdio1_default: mdio1_default {
927 function = "MDIO1";
928 groups = "MDIO1";
929 };
930
931 pinctrl_mdio2_default: mdio2_default {
932 function = "MDIO2";
933 groups = "MDIO2";
934 };
935
936 pinctrl_ncts1_default: ncts1_default {
937 function = "NCTS1";
938 groups = "NCTS1";
939 };
940
941 pinctrl_ncts2_default: ncts2_default {
942 function = "NCTS2";
943 groups = "NCTS2";
944 };
945
946 pinctrl_ncts3_default: ncts3_default {
947 function = "NCTS3";
948 groups = "NCTS3";
949 };
950
951 pinctrl_ncts4_default: ncts4_default {
952 function = "NCTS4";
953 groups = "NCTS4";
954 };
955
956 pinctrl_ndcd1_default: ndcd1_default {
957 function = "NDCD1";
958 groups = "NDCD1";
959 };
960
961 pinctrl_ndcd2_default: ndcd2_default {
962 function = "NDCD2";
963 groups = "NDCD2";
964 };
965
966 pinctrl_ndcd3_default: ndcd3_default {
967 function = "NDCD3";
968 groups = "NDCD3";
969 };
970
971 pinctrl_ndcd4_default: ndcd4_default {
972 function = "NDCD4";
973 groups = "NDCD4";
974 };
975
976 pinctrl_ndsr1_default: ndsr1_default {
977 function = "NDSR1";
978 groups = "NDSR1";
979 };
980
981 pinctrl_ndsr2_default: ndsr2_default {
982 function = "NDSR2";
983 groups = "NDSR2";
984 };
985
986 pinctrl_ndsr3_default: ndsr3_default {
987 function = "NDSR3";
988 groups = "NDSR3";
989 };
990
991 pinctrl_ndsr4_default: ndsr4_default {
992 function = "NDSR4";
993 groups = "NDSR4";
994 };
995
996 pinctrl_ndtr1_default: ndtr1_default {
997 function = "NDTR1";
998 groups = "NDTR1";
999 };
1000
1001 pinctrl_ndtr2_default: ndtr2_default {
1002 function = "NDTR2";
1003 groups = "NDTR2";
1004 };
1005
1006 pinctrl_ndtr3_default: ndtr3_default {
1007 function = "NDTR3";
1008 groups = "NDTR3";
1009 };
1010
1011 pinctrl_ndtr4_default: ndtr4_default {
1012 function = "NDTR4";
1013 groups = "NDTR4";
1014 };
1015
1016 pinctrl_ndts4_default: ndts4_default {
1017 function = "NDTS4";
1018 groups = "NDTS4";
1019 };
1020
1021 pinctrl_nri1_default: nri1_default {
1022 function = "NRI1";
1023 groups = "NRI1";
1024 };
1025
1026 pinctrl_nri2_default: nri2_default {
1027 function = "NRI2";
1028 groups = "NRI2";
1029 };
1030
1031 pinctrl_nri3_default: nri3_default {
1032 function = "NRI3";
1033 groups = "NRI3";
1034 };
1035
1036 pinctrl_nri4_default: nri4_default {
1037 function = "NRI4";
1038 groups = "NRI4";
1039 };
1040
1041 pinctrl_nrts1_default: nrts1_default {
1042 function = "NRTS1";
1043 groups = "NRTS1";
1044 };
1045
1046 pinctrl_nrts2_default: nrts2_default {
1047 function = "NRTS2";
1048 groups = "NRTS2";
1049 };
1050
1051 pinctrl_nrts3_default: nrts3_default {
1052 function = "NRTS3";
1053 groups = "NRTS3";
1054 };
1055
1056 pinctrl_oscclk_default: oscclk_default {
1057 function = "OSCCLK";
1058 groups = "OSCCLK";
1059 };
1060
1061 pinctrl_pwm0_default: pwm0_default {
1062 function = "PWM0";
1063 groups = "PWM0";
1064 };
1065
1066 pinctrl_pwm1_default: pwm1_default {
1067 function = "PWM1";
1068 groups = "PWM1";
1069 };
1070
1071 pinctrl_pwm2_default: pwm2_default {
1072 function = "PWM2";
1073 groups = "PWM2";
1074 };
1075
1076 pinctrl_pwm3_default: pwm3_default {
1077 function = "PWM3";
1078 groups = "PWM3";
1079 };
1080
1081 pinctrl_pwm4_default: pwm4_default {
1082 function = "PWM4";
1083 groups = "PWM4";
1084 };
1085
1086 pinctrl_pwm5_default: pwm5_default {
1087 function = "PWM5";
1088 groups = "PWM5";
1089 };
1090
1091 pinctrl_pwm6_default: pwm6_default {
1092 function = "PWM6";
1093 groups = "PWM6";
1094 };
1095
1096 pinctrl_pwm7_default: pwm7_default {
1097 function = "PWM7";
1098 groups = "PWM7";
1099 };
1100
1101 pinctrl_rgmii1_default: rgmii1_default {
1102 function = "RGMII1";
1103 groups = "RGMII1";
1104 };
1105
1106 pinctrl_rgmii2_default: rgmii2_default {
1107 function = "RGMII2";
1108 groups = "RGMII2";
1109 };
1110
1111 pinctrl_rmii1_default: rmii1_default {
1112 function = "RMII1";
1113 groups = "RMII1";
1114 };
1115
1116 pinctrl_rmii2_default: rmii2_default {
1117 function = "RMII2";
1118 groups = "RMII2";
1119 };
1120
1121 pinctrl_rom16_default: rom16_default {
1122 function = "ROM16";
1123 groups = "ROM16";
1124 };
1125
1126 pinctrl_rom8_default: rom8_default {
1127 function = "ROM8";
1128 groups = "ROM8";
1129 };
1130
1131 pinctrl_romcs1_default: romcs1_default {
1132 function = "ROMCS1";
1133 groups = "ROMCS1";
1134 };
1135
1136 pinctrl_romcs2_default: romcs2_default {
1137 function = "ROMCS2";
1138 groups = "ROMCS2";
1139 };
1140
1141 pinctrl_romcs3_default: romcs3_default {
1142 function = "ROMCS3";
1143 groups = "ROMCS3";
1144 };
1145
1146 pinctrl_romcs4_default: romcs4_default {
1147 function = "ROMCS4";
1148 groups = "ROMCS4";
1149 };
1150
1151 pinctrl_rxd1_default: rxd1_default {
1152 function = "RXD1";
1153 groups = "RXD1";
1154 };
1155
1156 pinctrl_rxd2_default: rxd2_default {
1157 function = "RXD2";
1158 groups = "RXD2";
1159 };
1160
1161 pinctrl_rxd3_default: rxd3_default {
1162 function = "RXD3";
1163 groups = "RXD3";
1164 };
1165
1166 pinctrl_rxd4_default: rxd4_default {
1167 function = "RXD4";
1168 groups = "RXD4";
1169 };
1170
1171 pinctrl_salt1_default: salt1_default {
1172 function = "SALT1";
1173 groups = "SALT1";
1174 };
1175
1176 pinctrl_salt2_default: salt2_default {
1177 function = "SALT2";
1178 groups = "SALT2";
1179 };
1180
1181 pinctrl_salt3_default: salt3_default {
1182 function = "SALT3";
1183 groups = "SALT3";
1184 };
1185
1186 pinctrl_salt4_default: salt4_default {
1187 function = "SALT4";
1188 groups = "SALT4";
1189 };
1190
1191 pinctrl_sd1_default: sd1_default {
1192 function = "SD1";
1193 groups = "SD1";
1194 };
1195
1196 pinctrl_sd2_default: sd2_default {
1197 function = "SD2";
1198 groups = "SD2";
1199 };
1200
1201 pinctrl_sgpmck_default: sgpmck_default {
1202 function = "SGPMCK";
1203 groups = "SGPMCK";
1204 };
1205
1206 pinctrl_sgpmi_default: sgpmi_default {
1207 function = "SGPMI";
1208 groups = "SGPMI";
1209 };
1210
1211 pinctrl_sgpmld_default: sgpmld_default {
1212 function = "SGPMLD";
1213 groups = "SGPMLD";
1214 };
1215
1216 pinctrl_sgpmo_default: sgpmo_default {
1217 function = "SGPMO";
1218 groups = "SGPMO";
1219 };
1220
1221 pinctrl_sgpsck_default: sgpsck_default {
1222 function = "SGPSCK";
1223 groups = "SGPSCK";
1224 };
1225
1226 pinctrl_sgpsi0_default: sgpsi0_default {
1227 function = "SGPSI0";
1228 groups = "SGPSI0";
1229 };
1230
1231 pinctrl_sgpsi1_default: sgpsi1_default {
1232 function = "SGPSI1";
1233 groups = "SGPSI1";
1234 };
1235
1236 pinctrl_sgpsld_default: sgpsld_default {
1237 function = "SGPSLD";
1238 groups = "SGPSLD";
1239 };
1240
1241 pinctrl_sioonctrl_default: sioonctrl_default {
1242 function = "SIOONCTRL";
1243 groups = "SIOONCTRL";
1244 };
1245
1246 pinctrl_siopbi_default: siopbi_default {
1247 function = "SIOPBI";
1248 groups = "SIOPBI";
1249 };
1250
1251 pinctrl_siopbo_default: siopbo_default {
1252 function = "SIOPBO";
1253 groups = "SIOPBO";
1254 };
1255
1256 pinctrl_siopwreq_default: siopwreq_default {
1257 function = "SIOPWREQ";
1258 groups = "SIOPWREQ";
1259 };
1260
1261 pinctrl_siopwrgd_default: siopwrgd_default {
1262 function = "SIOPWRGD";
1263 groups = "SIOPWRGD";
1264 };
1265
1266 pinctrl_sios3_default: sios3_default {
1267 function = "SIOS3";
1268 groups = "SIOS3";
1269 };
1270
1271 pinctrl_sios5_default: sios5_default {
1272 function = "SIOS5";
1273 groups = "SIOS5";
1274 };
1275
1276 pinctrl_siosci_default: siosci_default {
1277 function = "SIOSCI";
1278 groups = "SIOSCI";
1279 };
1280
1281 pinctrl_spi1_default: spi1_default {
1282 function = "SPI1";
1283 groups = "SPI1";
1284 };
1285
1286 pinctrl_spi1debug_default: spi1debug_default {
1287 function = "SPI1DEBUG";
1288 groups = "SPI1DEBUG";
1289 };
1290
1291 pinctrl_spi1passthru_default: spi1passthru_default {
1292 function = "SPI1PASSTHRU";
1293 groups = "SPI1PASSTHRU";
1294 };
1295
1296 pinctrl_spics1_default: spics1_default {
1297 function = "SPICS1";
1298 groups = "SPICS1";
1299 };
1300
1301 pinctrl_timer3_default: timer3_default {
1302 function = "TIMER3";
1303 groups = "TIMER3";
1304 };
1305
1306 pinctrl_timer4_default: timer4_default {
1307 function = "TIMER4";
1308 groups = "TIMER4";
1309 };
1310
1311 pinctrl_timer5_default: timer5_default {
1312 function = "TIMER5";
1313 groups = "TIMER5";
1314 };
1315
1316 pinctrl_timer6_default: timer6_default {
1317 function = "TIMER6";
1318 groups = "TIMER6";
1319 };
1320
1321 pinctrl_timer7_default: timer7_default {
1322 function = "TIMER7";
1323 groups = "TIMER7";
1324 };
1325
1326 pinctrl_timer8_default: timer8_default {
1327 function = "TIMER8";
1328 groups = "TIMER8";
1329 };
1330
1331 pinctrl_txd1_default: txd1_default {
1332 function = "TXD1";
1333 groups = "TXD1";
1334 };
1335
1336 pinctrl_txd2_default: txd2_default {
1337 function = "TXD2";
1338 groups = "TXD2";
1339 };
1340
1341 pinctrl_txd3_default: txd3_default {
1342 function = "TXD3";
1343 groups = "TXD3";
1344 };
1345
1346 pinctrl_txd4_default: txd4_default {
1347 function = "TXD4";
1348 groups = "TXD4";
1349 };
1350
1351 pinctrl_uart6_default: uart6_default {
1352 function = "UART6";
1353 groups = "UART6";
1354 };
1355
1356 pinctrl_usbcki_default: usbcki_default {
1357 function = "USBCKI";
1358 groups = "USBCKI";
1359 };
1360
ac6e31d3
BH		 1361 pinctrl_usb2h_default: usb2h_default {
1362 function = "USB2H1";
1363 groups = "USB2H1";
1364 };
1365
1366 pinctrl_usb2d_default: usb2d_default {
1367 function = "USB2D1";
1368 groups = "USB2D1";
1369 };
1370
cd7df3f7
AJ		 1371 pinctrl_vgabios_rom_default: vgabios_rom_default {
1372 function = "VGABIOS_ROM";
1373 groups = "VGABIOS_ROM";
1374 };
1375
1376 pinctrl_vgahs_default: vgahs_default {
1377 function = "VGAHS";
1378 groups = "VGAHS";
1379 };
1380
1381 pinctrl_vgavs_default: vgavs_default {
1382 function = "VGAVS";
1383 groups = "VGAVS";
1384 };
1385
1386 pinctrl_vpi18_default: vpi18_default {
1387 function = "VPI18";
1388 groups = "VPI18";
1389 };
1390
1391 pinctrl_vpi24_default: vpi24_default {
1392 function = "VPI24";
1393 groups = "VPI24";
1394 };
1395
1396 pinctrl_vpi30_default: vpi30_default {
1397 function = "VPI30";
1398 groups = "VPI30";
1399 };
1400
1401 pinctrl_vpo12_default: vpo12_default {
1402 function = "VPO12";
1403 groups = "VPO12";
1404 };
1405
1406 pinctrl_vpo24_default: vpo24_default {
1407 function = "VPO24";
1408 groups = "VPO24";
1409 };
1410
1411 pinctrl_wdtrst1_default: wdtrst1_default {
1412 function = "WDTRST1";
1413 groups = "WDTRST1";
1414 };
1415
1416 pinctrl_wdtrst2_default: wdtrst2_default {
1417 function = "WDTRST2";
1418 groups = "WDTRST2";
1419 };
1420};
Linux 6.x block layer and io_uring tree(s)