Linux v4.13-rc1
[linux-2.6-block.git] / arch / arm / boot / dts / aspeed-g4.dtsi
CommitLineData
d44a1138
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1#include "skeleton.dtsi"
2
3/ {
4 model = "Aspeed BMC";
5 compatible = "aspeed,ast2400";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&vic>;
9
10 cpus {
11 #address-cells = <1>;
12 #size-cells = <0>;
13
14 cpu@0 {
15 compatible = "arm,arm926ej-s";
16 device_type = "cpu";
17 reg = <0>;
18 };
19 };
20
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21 ahb {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
74dc3cd3
CLG
27 fmc: flash-controller@1e620000 {
28 reg = < 0x1e620000 0x94
29 0x20000000 0x02000000 >;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 compatible = "aspeed,ast2400-fmc";
33 status = "disabled";
34 interrupts = <19>;
35 flash@0 {
36 reg = < 0 >;
37 compatible = "jedec,spi-nor";
38 status = "disabled";
39 };
40 };
41
42 spi: flash-controller@1e630000 {
43 reg = < 0x1e630000 0x18
44 0x30000000 0x02000000 >;
45 #address-cells = <1>;
46 #size-cells = <0>;
47 compatible = "aspeed,ast2400-spi";
48 status = "disabled";
49 flash@0 {
50 reg = < 0 >;
51 compatible = "jedec,spi-nor";
52 status = "disabled";
53 };
54 };
55
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56 vic: interrupt-controller@1e6c0080 {
57 compatible = "aspeed,ast2400-vic";
58 interrupt-controller;
59 #interrupt-cells = <1>;
60 valid-sources = <0xffffffff 0x0007ffff>;
61 reg = <0x1e6c0080 0x80>;
62 };
63
34ea5c9d 64 mac0: ethernet@1e660000 {
78d28543 65 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
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66 reg = <0x1e660000 0x180>;
67 interrupts = <2>;
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68 status = "disabled";
69 };
70
71 mac1: ethernet@1e680000 {
78d28543 72 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
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73 reg = <0x1e680000 0x180>;
74 interrupts = <3>;
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75 status = "disabled";
76 };
77
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78 apb {
79 compatible = "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges;
83
d9072279
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84 syscon: syscon@1e6e2000 {
85 compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
86 reg = <0x1e6e2000 0x1a8>;
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87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 clk_clkin: clk_clkin {
91 #clock-cells = <0>;
92 compatible = "fixed-clock";
93 clock-frequency = <48000000>;
94 };
95
96 clk_hpll: clk_hpll@70 {
97 #clock-cells = <0>;
98 compatible = "aspeed,g4-hpll-clock", "fixed-clock";
99 reg = <0x70>;
100 clocks = <&clk_clkin>;
101 clock-frequency = <384000000>;
102 };
103
104 clk_ahb: clk_ahb@70 {
105 #clock-cells = <0>;
106 compatible = "aspeed,g4-ahb-clock", "fixed-clock";
107 reg = <0x70>;
108 clocks = <&clk_hpll>;
109 clock-frequency = <192000000>;
110 };
111
112 clk_apb: clk_apb@08 {
113 #clock-cells = <0>;
114 compatible = "aspeed,g4-apb-clock", "fixed-clock";
115 reg = <0x08>;
116 clocks = <&clk_hpll>;
117 clock-frequency = <48000000>;
118 };
119
120 clk_uart: clk_uart@2c{
121 #clock-cells = <0>;
122 compatible = "aspeed,g4-uart-clock", "fixed-clock";
123 reg = <0x2c>;
124 clock-frequency = <24000000>;
125 };
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126
127 pinctrl: pinctrl {
128 compatible = "aspeed,g4-pinctrl";
129
130 pinctrl_acpi_default: acpi_default {
131 function = "ACPI";
132 groups = "ACPI";
133 };
134
135 pinctrl_adc0_default: adc0_default {
136 function = "ADC0";
137 groups = "ADC0";
138 };
139
140 pinctrl_adc1_default: adc1_default {
141 function = "ADC1";
142 groups = "ADC1";
143 };
144
145 pinctrl_adc10_default: adc10_default {
146 function = "ADC10";
147 groups = "ADC10";
148 };
149
150 pinctrl_adc11_default: adc11_default {
151 function = "ADC11";
152 groups = "ADC11";
153 };
154
155 pinctrl_adc12_default: adc12_default {
156 function = "ADC12";
157 groups = "ADC12";
158 };
159
160 pinctrl_adc13_default: adc13_default {
161 function = "ADC13";
162 groups = "ADC13";
163 };
164
165 pinctrl_adc14_default: adc14_default {
166 function = "ADC14";
167 groups = "ADC14";
168 };
169
170 pinctrl_adc15_default: adc15_default {
171 function = "ADC15";
172 groups = "ADC15";
173 };
174
175 pinctrl_adc2_default: adc2_default {
176 function = "ADC2";
177 groups = "ADC2";
178 };
179
180 pinctrl_adc3_default: adc3_default {
181 function = "ADC3";
182 groups = "ADC3";
183 };
184
185 pinctrl_adc4_default: adc4_default {
186 function = "ADC4";
187 groups = "ADC4";
188 };
189
190 pinctrl_adc5_default: adc5_default {
191 function = "ADC5";
192 groups = "ADC5";
193 };
194
195 pinctrl_adc6_default: adc6_default {
196 function = "ADC6";
197 groups = "ADC6";
198 };
199
200 pinctrl_adc7_default: adc7_default {
201 function = "ADC7";
202 groups = "ADC7";
203 };
204
205 pinctrl_adc8_default: adc8_default {
206 function = "ADC8";
207 groups = "ADC8";
208 };
209
210 pinctrl_adc9_default: adc9_default {
211 function = "ADC9";
212 groups = "ADC9";
213 };
214
215 pinctrl_bmcint_default: bmcint_default {
216 function = "BMCINT";
217 groups = "BMCINT";
218 };
219
220 pinctrl_ddcclk_default: ddcclk_default {
221 function = "DDCCLK";
222 groups = "DDCCLK";
223 };
224
225 pinctrl_ddcdat_default: ddcdat_default {
226 function = "DDCDAT";
227 groups = "DDCDAT";
228 };
229
230 pinctrl_extrst_default: extrst_default {
231 function = "EXTRST";
232 groups = "EXTRST";
233 };
234
235 pinctrl_flack_default: flack_default {
236 function = "FLACK";
237 groups = "FLACK";
238 };
239
240 pinctrl_flbusy_default: flbusy_default {
241 function = "FLBUSY";
242 groups = "FLBUSY";
243 };
244
245 pinctrl_flwp_default: flwp_default {
246 function = "FLWP";
247 groups = "FLWP";
248 };
249
250 pinctrl_gpid_default: gpid_default {
251 function = "GPID";
252 groups = "GPID";
253 };
254
255 pinctrl_gpid0_default: gpid0_default {
256 function = "GPID0";
257 groups = "GPID0";
258 };
259
260 pinctrl_gpid2_default: gpid2_default {
261 function = "GPID2";
262 groups = "GPID2";
263 };
264
265 pinctrl_gpid4_default: gpid4_default {
266 function = "GPID4";
267 groups = "GPID4";
268 };
269
270 pinctrl_gpid6_default: gpid6_default {
271 function = "GPID6";
272 groups = "GPID6";
273 };
274
275 pinctrl_gpie0_default: gpie0_default {
276 function = "GPIE0";
277 groups = "GPIE0";
278 };
279
280 pinctrl_gpie2_default: gpie2_default {
281 function = "GPIE2";
282 groups = "GPIE2";
283 };
284
285 pinctrl_gpie4_default: gpie4_default {
286 function = "GPIE4";
287 groups = "GPIE4";
288 };
289
290 pinctrl_gpie6_default: gpie6_default {
291 function = "GPIE6";
292 groups = "GPIE6";
293 };
294
295 pinctrl_i2c10_default: i2c10_default {
296 function = "I2C10";
297 groups = "I2C10";
298 };
299
300 pinctrl_i2c11_default: i2c11_default {
301 function = "I2C11";
302 groups = "I2C11";
303 };
304
305 pinctrl_i2c12_default: i2c12_default {
306 function = "I2C12";
307 groups = "I2C12";
308 };
309
310 pinctrl_i2c13_default: i2c13_default {
311 function = "I2C13";
312 groups = "I2C13";
313 };
314
315 pinctrl_i2c14_default: i2c14_default {
316 function = "I2C14";
317 groups = "I2C14";
318 };
319
320 pinctrl_i2c3_default: i2c3_default {
321 function = "I2C3";
322 groups = "I2C3";
323 };
324
325 pinctrl_i2c4_default: i2c4_default {
326 function = "I2C4";
327 groups = "I2C4";
328 };
329
330 pinctrl_i2c5_default: i2c5_default {
331 function = "I2C5";
332 groups = "I2C5";
333 };
334
335 pinctrl_i2c6_default: i2c6_default {
336 function = "I2C6";
337 groups = "I2C6";
338 };
339
340 pinctrl_i2c7_default: i2c7_default {
341 function = "I2C7";
342 groups = "I2C7";
343 };
344
345 pinctrl_i2c8_default: i2c8_default {
346 function = "I2C8";
347 groups = "I2C8";
348 };
349
350 pinctrl_i2c9_default: i2c9_default {
351 function = "I2C9";
352 groups = "I2C9";
353 };
354
355 pinctrl_lpcpd_default: lpcpd_default {
356 function = "LPCPD";
357 groups = "LPCPD";
358 };
359
360 pinctrl_lpcpme_default: lpcpme_default {
361 function = "LPCPME";
362 groups = "LPCPME";
363 };
364
365 pinctrl_lpcrst_default: lpcrst_default {
366 function = "LPCRST";
367 groups = "LPCRST";
368 };
369
370 pinctrl_lpcsmi_default: lpcsmi_default {
371 function = "LPCSMI";
372 groups = "LPCSMI";
373 };
374
375 pinctrl_mac1link_default: mac1link_default {
376 function = "MAC1LINK";
377 groups = "MAC1LINK";
378 };
379
380 pinctrl_mac2link_default: mac2link_default {
381 function = "MAC2LINK";
382 groups = "MAC2LINK";
383 };
384
385 pinctrl_mdio1_default: mdio1_default {
386 function = "MDIO1";
387 groups = "MDIO1";
388 };
389
390 pinctrl_mdio2_default: mdio2_default {
391 function = "MDIO2";
392 groups = "MDIO2";
393 };
394
395 pinctrl_ncts1_default: ncts1_default {
396 function = "NCTS1";
397 groups = "NCTS1";
398 };
399
400 pinctrl_ncts2_default: ncts2_default {
401 function = "NCTS2";
402 groups = "NCTS2";
403 };
404
405 pinctrl_ncts3_default: ncts3_default {
406 function = "NCTS3";
407 groups = "NCTS3";
408 };
409
410 pinctrl_ncts4_default: ncts4_default {
411 function = "NCTS4";
412 groups = "NCTS4";
413 };
414
415 pinctrl_ndcd1_default: ndcd1_default {
416 function = "NDCD1";
417 groups = "NDCD1";
418 };
419
420 pinctrl_ndcd2_default: ndcd2_default {
421 function = "NDCD2";
422 groups = "NDCD2";
423 };
424
425 pinctrl_ndcd3_default: ndcd3_default {
426 function = "NDCD3";
427 groups = "NDCD3";
428 };
429
430 pinctrl_ndcd4_default: ndcd4_default {
431 function = "NDCD4";
432 groups = "NDCD4";
433 };
434
435 pinctrl_ndsr1_default: ndsr1_default {
436 function = "NDSR1";
437 groups = "NDSR1";
438 };
439
440 pinctrl_ndsr2_default: ndsr2_default {
441 function = "NDSR2";
442 groups = "NDSR2";
443 };
444
445 pinctrl_ndsr3_default: ndsr3_default {
446 function = "NDSR3";
447 groups = "NDSR3";
448 };
449
450 pinctrl_ndsr4_default: ndsr4_default {
451 function = "NDSR4";
452 groups = "NDSR4";
453 };
454
455 pinctrl_ndtr1_default: ndtr1_default {
456 function = "NDTR1";
457 groups = "NDTR1";
458 };
459
460 pinctrl_ndtr2_default: ndtr2_default {
461 function = "NDTR2";
462 groups = "NDTR2";
463 };
464
465 pinctrl_ndtr3_default: ndtr3_default {
466 function = "NDTR3";
467 groups = "NDTR3";
468 };
469
470 pinctrl_ndtr4_default: ndtr4_default {
471 function = "NDTR4";
472 groups = "NDTR4";
473 };
474
475 pinctrl_ndts4_default: ndts4_default {
476 function = "NDTS4";
477 groups = "NDTS4";
478 };
479
480 pinctrl_nri1_default: nri1_default {
481 function = "NRI1";
482 groups = "NRI1";
483 };
484
485 pinctrl_nri2_default: nri2_default {
486 function = "NRI2";
487 groups = "NRI2";
488 };
489
490 pinctrl_nri3_default: nri3_default {
491 function = "NRI3";
492 groups = "NRI3";
493 };
494
495 pinctrl_nri4_default: nri4_default {
496 function = "NRI4";
497 groups = "NRI4";
498 };
499
500 pinctrl_nrts1_default: nrts1_default {
501 function = "NRTS1";
502 groups = "NRTS1";
503 };
504
505 pinctrl_nrts2_default: nrts2_default {
506 function = "NRTS2";
507 groups = "NRTS2";
508 };
509
510 pinctrl_nrts3_default: nrts3_default {
511 function = "NRTS3";
512 groups = "NRTS3";
513 };
514
515 pinctrl_oscclk_default: oscclk_default {
516 function = "OSCCLK";
517 groups = "OSCCLK";
518 };
519
520 pinctrl_pwm0_default: pwm0_default {
521 function = "PWM0";
522 groups = "PWM0";
523 };
524
525 pinctrl_pwm1_default: pwm1_default {
526 function = "PWM1";
527 groups = "PWM1";
528 };
529
530 pinctrl_pwm2_default: pwm2_default {
531 function = "PWM2";
532 groups = "PWM2";
533 };
534
535 pinctrl_pwm3_default: pwm3_default {
536 function = "PWM3";
537 groups = "PWM3";
538 };
539
540 pinctrl_pwm4_default: pwm4_default {
541 function = "PWM4";
542 groups = "PWM4";
543 };
544
545 pinctrl_pwm5_default: pwm5_default {
546 function = "PWM5";
547 groups = "PWM5";
548 };
549
550 pinctrl_pwm6_default: pwm6_default {
551 function = "PWM6";
552 groups = "PWM6";
553 };
554
555 pinctrl_pwm7_default: pwm7_default {
556 function = "PWM7";
557 groups = "PWM7";
558 };
559
560 pinctrl_rgmii1_default: rgmii1_default {
561 function = "RGMII1";
562 groups = "RGMII1";
563 };
564
565 pinctrl_rgmii2_default: rgmii2_default {
566 function = "RGMII2";
567 groups = "RGMII2";
568 };
569
570 pinctrl_rmii1_default: rmii1_default {
571 function = "RMII1";
572 groups = "RMII1";
573 };
574
575 pinctrl_rmii2_default: rmii2_default {
576 function = "RMII2";
577 groups = "RMII2";
578 };
579
580 pinctrl_rom16_default: rom16_default {
581 function = "ROM16";
582 groups = "ROM16";
583 };
584
585 pinctrl_rom8_default: rom8_default {
586 function = "ROM8";
587 groups = "ROM8";
588 };
589
590 pinctrl_romcs1_default: romcs1_default {
591 function = "ROMCS1";
592 groups = "ROMCS1";
593 };
594
595 pinctrl_romcs2_default: romcs2_default {
596 function = "ROMCS2";
597 groups = "ROMCS2";
598 };
599
600 pinctrl_romcs3_default: romcs3_default {
601 function = "ROMCS3";
602 groups = "ROMCS3";
603 };
604
605 pinctrl_romcs4_default: romcs4_default {
606 function = "ROMCS4";
607 groups = "ROMCS4";
608 };
609
610 pinctrl_rxd1_default: rxd1_default {
611 function = "RXD1";
612 groups = "RXD1";
613 };
614
615 pinctrl_rxd2_default: rxd2_default {
616 function = "RXD2";
617 groups = "RXD2";
618 };
619
620 pinctrl_rxd3_default: rxd3_default {
621 function = "RXD3";
622 groups = "RXD3";
623 };
624
625 pinctrl_rxd4_default: rxd4_default {
626 function = "RXD4";
627 groups = "RXD4";
628 };
629
630 pinctrl_salt1_default: salt1_default {
631 function = "SALT1";
632 groups = "SALT1";
633 };
634
635 pinctrl_salt2_default: salt2_default {
636 function = "SALT2";
637 groups = "SALT2";
638 };
639
640 pinctrl_salt3_default: salt3_default {
641 function = "SALT3";
642 groups = "SALT3";
643 };
644
645 pinctrl_salt4_default: salt4_default {
646 function = "SALT4";
647 groups = "SALT4";
648 };
649
650 pinctrl_sd1_default: sd1_default {
651 function = "SD1";
652 groups = "SD1";
653 };
654
655 pinctrl_sd2_default: sd2_default {
656 function = "SD2";
657 groups = "SD2";
658 };
659
660 pinctrl_sgpmck_default: sgpmck_default {
661 function = "SGPMCK";
662 groups = "SGPMCK";
663 };
664
665 pinctrl_sgpmi_default: sgpmi_default {
666 function = "SGPMI";
667 groups = "SGPMI";
668 };
669
670 pinctrl_sgpmld_default: sgpmld_default {
671 function = "SGPMLD";
672 groups = "SGPMLD";
673 };
674
675 pinctrl_sgpmo_default: sgpmo_default {
676 function = "SGPMO";
677 groups = "SGPMO";
678 };
679
680 pinctrl_sgpsck_default: sgpsck_default {
681 function = "SGPSCK";
682 groups = "SGPSCK";
683 };
684
685 pinctrl_sgpsi0_default: sgpsi0_default {
686 function = "SGPSI0";
687 groups = "SGPSI0";
688 };
689
690 pinctrl_sgpsi1_default: sgpsi1_default {
691 function = "SGPSI1";
692 groups = "SGPSI1";
693 };
694
695 pinctrl_sgpsld_default: sgpsld_default {
696 function = "SGPSLD";
697 groups = "SGPSLD";
698 };
699
700 pinctrl_sioonctrl_default: sioonctrl_default {
701 function = "SIOONCTRL";
702 groups = "SIOONCTRL";
703 };
704
705 pinctrl_siopbi_default: siopbi_default {
706 function = "SIOPBI";
707 groups = "SIOPBI";
708 };
709
710 pinctrl_siopbo_default: siopbo_default {
711 function = "SIOPBO";
712 groups = "SIOPBO";
713 };
714
715 pinctrl_siopwreq_default: siopwreq_default {
716 function = "SIOPWREQ";
717 groups = "SIOPWREQ";
718 };
719
720 pinctrl_siopwrgd_default: siopwrgd_default {
721 function = "SIOPWRGD";
722 groups = "SIOPWRGD";
723 };
724
725 pinctrl_sios3_default: sios3_default {
726 function = "SIOS3";
727 groups = "SIOS3";
728 };
729
730 pinctrl_sios5_default: sios5_default {
731 function = "SIOS5";
732 groups = "SIOS5";
733 };
734
735 pinctrl_siosci_default: siosci_default {
736 function = "SIOSCI";
737 groups = "SIOSCI";
738 };
739
740 pinctrl_spi1_default: spi1_default {
741 function = "SPI1";
742 groups = "SPI1";
743 };
744
745 pinctrl_spi1debug_default: spi1debug_default {
746 function = "SPI1DEBUG";
747 groups = "SPI1DEBUG";
748 };
749
750 pinctrl_spi1passthru_default: spi1passthru_default {
751 function = "SPI1PASSTHRU";
752 groups = "SPI1PASSTHRU";
753 };
754
755 pinctrl_spics1_default: spics1_default {
756 function = "SPICS1";
757 groups = "SPICS1";
758 };
759
760 pinctrl_timer3_default: timer3_default {
761 function = "TIMER3";
762 groups = "TIMER3";
763 };
764
765 pinctrl_timer4_default: timer4_default {
766 function = "TIMER4";
767 groups = "TIMER4";
768 };
769
770 pinctrl_timer5_default: timer5_default {
771 function = "TIMER5";
772 groups = "TIMER5";
773 };
774
775 pinctrl_timer6_default: timer6_default {
776 function = "TIMER6";
777 groups = "TIMER6";
778 };
779
780 pinctrl_timer7_default: timer7_default {
781 function = "TIMER7";
782 groups = "TIMER7";
783 };
784
785 pinctrl_timer8_default: timer8_default {
786 function = "TIMER8";
787 groups = "TIMER8";
788 };
789
790 pinctrl_txd1_default: txd1_default {
791 function = "TXD1";
792 groups = "TXD1";
793 };
794
795 pinctrl_txd2_default: txd2_default {
796 function = "TXD2";
797 groups = "TXD2";
798 };
799
800 pinctrl_txd3_default: txd3_default {
801 function = "TXD3";
802 groups = "TXD3";
803 };
804
805 pinctrl_txd4_default: txd4_default {
806 function = "TXD4";
807 groups = "TXD4";
808 };
809
810 pinctrl_uart6_default: uart6_default {
811 function = "UART6";
812 groups = "UART6";
813 };
814
815 pinctrl_usbcki_default: usbcki_default {
816 function = "USBCKI";
817 groups = "USBCKI";
818 };
819
820 pinctrl_vgabios_rom_default: vgabios_rom_default {
821 function = "VGABIOS_ROM";
822 groups = "VGABIOS_ROM";
823 };
824
825 pinctrl_vgahs_default: vgahs_default {
826 function = "VGAHS";
827 groups = "VGAHS";
828 };
829
830 pinctrl_vgavs_default: vgavs_default {
831 function = "VGAVS";
832 groups = "VGAVS";
833 };
834
835 pinctrl_vpi18_default: vpi18_default {
836 function = "VPI18";
837 groups = "VPI18";
838 };
839
840 pinctrl_vpi24_default: vpi24_default {
841 function = "VPI24";
842 groups = "VPI24";
843 };
844
845 pinctrl_vpi30_default: vpi30_default {
846 function = "VPI30";
847 groups = "VPI30";
848 };
849
850 pinctrl_vpo12_default: vpo12_default {
851 function = "VPO12";
852 groups = "VPO12";
853 };
854
855 pinctrl_vpo24_default: vpo24_default {
856 function = "VPO24";
857 groups = "VPO24";
858 };
859
860 pinctrl_wdtrst1_default: wdtrst1_default {
861 function = "WDTRST1";
862 groups = "WDTRST1";
863 };
864
865 pinctrl_wdtrst2_default: wdtrst2_default {
866 function = "WDTRST2";
867 groups = "WDTRST2";
868 };
869
870 };
871 };
872
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873 sram@1e720000 {
874 compatible = "mmio-sram";
875 reg = <0x1e720000 0x8000>; // 32K
876 };
877
09955007
AJ
878 gpio: gpio@1e780000 {
879 #gpio-cells = <2>;
880 gpio-controller;
881 compatible = "aspeed,ast2400-gpio";
882 reg = <0x1e780000 0x1000>;
883 interrupts = <20>;
884 gpio-ranges = <&pinctrl 0 0 220>;
885 interrupt-controller;
886 };
887
d44a1138 888 timer: timer@1e782000 {
f46b563f 889 /* This timer is a Faraday FTTMR010 derivative */
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JS
890 compatible = "aspeed,ast2400-timer";
891 reg = <0x1e782000 0x90>;
f46b563f 892 interrupts = <16 17 18 35 36 37 38 39>;
d44a1138 893 clocks = <&clk_apb>;
f46b563f 894 clock-names = "PCLK";
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JS
895 };
896
897 wdt1: wdt@1e785000 {
23491da8 898 compatible = "aspeed,ast2400-wdt";
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JS
899 reg = <0x1e785000 0x1c>;
900 interrupts = <27>;
901 };
902
903 wdt2: wdt@1e785020 {
23491da8 904 compatible = "aspeed,ast2400-wdt";
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905 reg = <0x1e785020 0x1c>;
906 interrupts = <27>;
907 clocks = <&clk_apb>;
908 status = "disabled";
909 };
910
911 uart1: serial@1e783000 {
912 compatible = "ns16550a";
913 reg = <0x1e783000 0x1000>;
914 reg-shift = <2>;
915 interrupts = <9>;
916 clocks = <&clk_uart>;
917 no-loopback-test;
918 status = "disabled";
919 };
920
921 uart2: serial@1e78d000 {
922 compatible = "ns16550a";
923 reg = <0x1e78d000 0x1000>;
924 reg-shift = <2>;
925 interrupts = <32>;
926 clocks = <&clk_uart>;
927 no-loopback-test;
928 status = "disabled";
929 };
930
931 uart3: serial@1e78e000 {
932 compatible = "ns16550a";
933 reg = <0x1e78e000 0x1000>;
934 reg-shift = <2>;
935 interrupts = <33>;
936 clocks = <&clk_uart>;
937 no-loopback-test;
938 status = "disabled";
939 };
940
941 uart4: serial@1e78f000 {
942 compatible = "ns16550a";
943 reg = <0x1e78f000 0x1000>;
944 reg-shift = <2>;
945 interrupts = <34>;
946 clocks = <&clk_uart>;
947 no-loopback-test;
948 status = "disabled";
949 };
950
951 uart5: serial@1e784000 {
952 compatible = "ns16550a";
953 reg = <0x1e784000 0x1000>;
954 reg-shift = <2>;
955 interrupts = <10>;
956 clocks = <&clk_uart>;
957 current-speed = <38400>;
958 no-loopback-test;
959 status = "disabled";
960 };
961
962 uart6: serial@1e787000 {
963 compatible = "ns16550a";
964 reg = <0x1e787000 0x1000>;
965 reg-shift = <2>;
966 interrupts = <10>;
967 clocks = <&clk_uart>;
968 no-loopback-test;
969 status = "disabled";
970 };
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RA
971
972 adc: adc@1e6e9000 {
973 compatible = "aspeed,ast2400-adc";
974 reg = <0x1e6e9000 0xb0>;
975 clocks = <&clk_apb>;
976 #io-channel-cells = <1>;
977 status = "disabled";
978 };
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979 };
980 };
981};