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Merge tag 'kvm-x86-misc-6.9' of https://github.com/kvm-x86/linux into HEAD
[linux-2.6-block.git] / arch / arm / boot / dts / aspeed / aspeed-g6.dtsi
CommitLineData
2ca5646b
JS		 1// SPDX-License-Identifier: GPL-2.0-or-later
2// Copyright 2019 IBM Corp.
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
645afe73 5#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
2ca5646b
JS		 6#include <dt-bindings/clock/ast2600-clock.h>
7
8/ {
9 model = "Aspeed BMC";
10 compatible = "aspeed,ast2600";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
14
15 aliases {
9ee6d17b
JS		 16 i2c0 = &i2c0;
17 i2c1 = &i2c1;
18 i2c2 = &i2c2;
19 i2c3 = &i2c3;
20 i2c4 = &i2c4;
21 i2c5 = &i2c5;
22 i2c6 = &i2c6;
23 i2c7 = &i2c7;
24 i2c8 = &i2c8;
25 i2c9 = &i2c9;
26 i2c10 = &i2c10;
27 i2c11 = &i2c11;
28 i2c12 = &i2c12;
29 i2c13 = &i2c13;
30 i2c14 = &i2c14;
31 i2c15 = &i2c15;
c0d3e181
JS		 32 serial0 = &uart1;
33 serial1 = &uart2;
34 serial2 = &uart3;
35 serial3 = &uart4;
2ca5646b 36 serial4 = &uart5;
2aed40ee
JS		 37 serial5 = &vuart1;
38 serial6 = &vuart2;
2fb4955a
PL		 39 mdio0 = &mdio0;
40 mdio1 = &mdio1;
41 mdio2 = &mdio2;
42 mdio3 = &mdio3;
2ca5646b
JS		 43 };
44
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "aspeed,ast2600-smp";
50
51 cpu@f00 {
52 compatible = "arm,cortex-a7";
53 device_type = "cpu";
54 reg = <0xf00>;
55 };
56
57 cpu@f01 {
58 compatible = "arm,cortex-a7";
59 device_type = "cpu";
60 reg = <0xf01>;
61 };
62 };
63
64 timer {
65 compatible = "arm,armv7-timer";
66 interrupt-parent = <&gic>;
67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
71 clocks = <&syscon ASPEED_CLK_HPLL>;
72 arm,cpu-registers-not-fw-configured;
c998f40f 73 always-on;
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JS		 74 };
75
aac82707
TL		 76 edac: sdram@1e6e0000 {
77 compatible = "aspeed,ast2600-sdram-edac", "syscon";
78 reg = <0x1e6e0000 0x174>;
79 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
80 };
81
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JS		 82 ahb {
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 device_type = "soc";
87 ranges;
88
89 gic: interrupt-controller@40461000 {
90 compatible = "arm,cortex-a7-gic";
91 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
92 #interrupt-cells = <3>;
93 interrupt-controller;
94 interrupt-parent = <&gic>;
95 reg = <0x40461000 0x1000>,
96 <0x40462000 0x1000>,
97 <0x40464000 0x2000>,
98 <0x40466000 0x2000>;
99 };
100
62462a52
NL		 101 ahbc: bus@1e600000 {
102 compatible = "aspeed,ast2600-ahbc", "syscon";
103 reg = <0x1e600000 0x100>;
104 };
105
51d5d1bf 106 fmc: spi@1e620000 {
651b79e8 107 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
51d5d1bf
CLG		 108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "aspeed,ast2600-fmc";
111 clocks = <&syscon ASPEED_CLK_AHB>;
112 status = "disabled";
113 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
114 flash@0 {
115 reg = < 0 >;
116 compatible = "jedec,spi-nor";
117 spi-max-frequency = <50000000>;
4a92d02f 118 spi-rx-bus-width = <2>;
51d5d1bf
CLG		 119 status = "disabled";
120 };
121 flash@1 {
122 reg = < 1 >;
123 compatible = "jedec,spi-nor";
124 spi-max-frequency = <50000000>;
4a92d02f 125 spi-rx-bus-width = <2>;
51d5d1bf
CLG		 126 status = "disabled";
127 };
128 flash@2 {
129 reg = < 2 >;
130 compatible = "jedec,spi-nor";
131 spi-max-frequency = <50000000>;
4a92d02f 132 spi-rx-bus-width = <2>;
51d5d1bf
CLG		 133 status = "disabled";
134 };
135 };
136
137 spi1: spi@1e630000 {
651b79e8 138 reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
51d5d1bf
CLG		 139 #address-cells = <1>;
140 #size-cells = <0>;
141 compatible = "aspeed,ast2600-spi";
142 clocks = <&syscon ASPEED_CLK_AHB>;
143 status = "disabled";
144 flash@0 {
145 reg = < 0 >;
146 compatible = "jedec,spi-nor";
147 spi-max-frequency = <50000000>;
4a92d02f 148 spi-rx-bus-width = <2>;
51d5d1bf
CLG		 149 status = "disabled";
150 };
151 flash@1 {
152 reg = < 1 >;
153 compatible = "jedec,spi-nor";
154 spi-max-frequency = <50000000>;
4a92d02f 155 spi-rx-bus-width = <2>;
51d5d1bf
CLG		 156 status = "disabled";
157 };
158 };
159
160 spi2: spi@1e631000 {
651b79e8 161 reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
51d5d1bf
CLG		 162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "aspeed,ast2600-spi";
165 clocks = <&syscon ASPEED_CLK_AHB>;
166 status = "disabled";
167 flash@0 {
168 reg = < 0 >;
169 compatible = "jedec,spi-nor";
170 spi-max-frequency = <50000000>;
4a92d02f 171 spi-rx-bus-width = <2>;
51d5d1bf
CLG		 172 status = "disabled";
173 };
174 flash@1 {
175 reg = < 1 >;
176 compatible = "jedec,spi-nor";
177 spi-max-frequency = <50000000>;
4a92d02f 178 spi-rx-bus-width = <2>;
51d5d1bf
CLG		 179 status = "disabled";
180 };
181 flash@2 {
182 reg = < 2 >;
183 compatible = "jedec,spi-nor";
184 spi-max-frequency = <50000000>;
4a92d02f 185 spi-rx-bus-width = <2>;
51d5d1bf
CLG		 186 status = "disabled";
187 };
188 };
189
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JS		 190 mdio0: mdio@1e650000 {
191 compatible = "aspeed,ast2600-mdio";
192 reg = <0x1e650000 0x8>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 status = "disabled";
d29f8a6e
AJ		 196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_mdio1_default>;
a8db203d 198 resets = <&syscon ASPEED_RESET_MII>;
2ca5646b
JS		 199 };
200
201 mdio1: mdio@1e650008 {
202 compatible = "aspeed,ast2600-mdio";
203 reg = <0x1e650008 0x8>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 status = "disabled";
d29f8a6e
AJ		 207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_mdio2_default>;
a8db203d 209 resets = <&syscon ASPEED_RESET_MII>;
2ca5646b
JS		 210 };
211
212 mdio2: mdio@1e650010 {
213 compatible = "aspeed,ast2600-mdio";
214 reg = <0x1e650010 0x8>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 status = "disabled";
d29f8a6e
AJ		 218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_mdio3_default>;
a8db203d 220 resets = <&syscon ASPEED_RESET_MII>;
2ca5646b
JS		 221 };
222
223 mdio3: mdio@1e650018 {
224 compatible = "aspeed,ast2600-mdio";
225 reg = <0x1e650018 0x8>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 status = "disabled";
d29f8a6e
AJ		 229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_mdio4_default>;
a8db203d 231 resets = <&syscon ASPEED_RESET_MII>;
2ca5646b
JS		 232 };
233
234 mac0: ftgmac@1e660000 {
235 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
236 reg = <0x1e660000 0x180>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
241 status = "disabled";
242 };
243
244 mac1: ftgmac@1e680000 {
245 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
246 reg = <0x1e680000 0x180>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
251 status = "disabled";
252 };
253
254 mac2: ftgmac@1e670000 {
255 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
256 reg = <0x1e670000 0x180>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
261 status = "disabled";
262 };
263
264 mac3: ftgmac@1e690000 {
265 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
266 reg = <0x1e690000 0x180>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
271 status = "disabled";
272 };
273
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TR		 274 ehci0: usb@1e6a1000 {
275 compatible = "aspeed,ast2600-ehci", "generic-ehci";
276 reg = <0x1e6a1000 0x100>;
277 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_usb2ah_default>;
281 status = "disabled";
282 };
283
284 ehci1: usb@1e6a3000 {
285 compatible = "aspeed,ast2600-ehci", "generic-ehci";
286 reg = <0x1e6a3000 0x100>;
287 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_usb2bh_default>;
291 status = "disabled";
292 };
293
294 uhci: usb@1e6b0000 {
295 compatible = "aspeed,ast2600-uhci", "generic-uhci";
296 reg = <0x1e6b0000 0x100>;
297 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
298 #ports = <2>;
299 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
300 status = "disabled";
301 /*
302 * No default pinmux, it will follow EHCI, use an
303 * explicit pinmux override if EHCI is not enabled.
304 */
305 };
306
307 vhub: usb-vhub@1e6a0000 {
308 compatible = "aspeed,ast2600-usb-vhub";
309 reg = <0x1e6a0000 0x350>;
310 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
312 aspeed,vhub-downstream-ports = <7>;
313 aspeed,vhub-generic-endpoints = <21>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usb2ad_default>;
316 status = "disabled";
317 };
318
c9cb67c3
NL		 319 udc: usb@1e6a2000 {
320 compatible = "aspeed,ast2600-udc";
321 reg = <0x1e6a2000 0x300>;
322 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_usb2bd_default>;
326 status = "disabled";
327 };
328
2ca5646b
JS		 329 apb {
330 compatible = "simple-bus";
331 #address-cells = <1>;
332 #size-cells = <1>;
333 ranges;
334
a1a2990e
NL		 335 hace: crypto@1e6d0000 {
336 compatible = "aspeed,ast2600-hace";
337 reg = <0x1e6d0000 0x200>;
338 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
340 resets = <&syscon ASPEED_RESET_HACE>;
341 };
342
2ca5646b
JS		 343 syscon: syscon@1e6e2000 {
344 compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
345 reg = <0x1e6e2000 0x1000>;
346 ranges = <0 0x1e6e2000 0x1000>;
347 #address-cells = <1>;
348 #size-cells = <1>;
349 #clock-cells = <1>;
350 #reset-cells = <1>;
351
352 pinctrl: pinctrl {
353 compatible = "aspeed,ast2600-pinctrl";
354 };
355
fe100b38
JS		 356 silicon-id@14 {
357 compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id";
358 reg = <0x14 0x4 0x5b0 0x8>;
359 };
360
2ca5646b
JS		 361 smp-memram@180 {
362 compatible = "aspeed,ast2600-smpmem";
363 reg = <0x180 0x40>;
364 };
f9950ad2
EJ		 365
366 scu_ic0: interrupt-controller@560 {
367 #interrupt-cells = <1>;
368 compatible = "aspeed,ast2600-scu-ic0";
369 reg = <0x560 0x4>;
370 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 };
373
374 scu_ic1: interrupt-controller@570 {
375 #interrupt-cells = <1>;
376 compatible = "aspeed,ast2600-scu-ic1";
377 reg = <0x570 0x4>;
378 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-controller;
380 };
2ca5646b
JS		 381 };
382
383 rng: hwrng@1e6e2524 {
384 compatible = "timeriomem_rng";
385 reg = <0x1e6e2524 0x4>;
386 period = <1>;
387 quality = <100>;
388 };
389
4fa40bfa
JS		 390 gfx: display@1e6e6000 {
391 compatible = "aspeed,ast2600-gfx", "syscon";
392 reg = <0x1e6e6000 0x1000>;
393 reg-io-width = <4>;
394 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
395 resets = <&syscon ASPEED_RESET_GRAPHICS>;
396 syscon = <&syscon>;
397 status = "disabled";
398 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
399 };
400
e7d1ed84
EJ		 401 xdma: xdma@1e6e7000 {
402 compatible = "aspeed,ast2600-xdma";
403 reg = <0x1e6e7000 0x100>;
404 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
f90fe8d3
EJ		 405 resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>;
406 reset-names = "device", "root-complex";
e7d1ed84 407 interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
645afe73
EJ		 408 <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>;
409 aspeed,pcie-device = "bmc";
e7d1ed84
EJ		 410 aspeed,scu = <&syscon>;
411 status = "disabled";
412 };
413
eaad4046
EJ		 414 adc0: adc@1e6e9000 {
415 compatible = "aspeed,ast2600-adc0";
416 reg = <0x1e6e9000 0x100>;
417 clocks = <&syscon ASPEED_CLK_APB2>;
418 resets = <&syscon ASPEED_RESET_ADC>;
419 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
420 #io-channel-cells = <1>;
421 status = "disabled";
422 };
423
424 adc1: adc@1e6e9100 {
425 compatible = "aspeed,ast2600-adc1";
426 reg = <0x1e6e9100 0x100>;
427 clocks = <&syscon ASPEED_CLK_APB2>;
428 resets = <&syscon ASPEED_RESET_ADC>;
429 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
430 #io-channel-cells = <1>;
431 status = "disabled";
432 };
433
fea28946
JS		 434 sbc: secure-boot-controller@1e6f2000 {
435 compatible = "aspeed,ast2600-sbc";
436 reg = <0x1e6f2000 0x1000>;
437 };
438
62462a52
NL		 439 acry: crypto@1e6fa000 {
440 compatible = "aspeed,ast2600-acry";
441 reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;
442 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;
444 aspeed,ahbc = <&ahbc>;
445 };
446
32e62d1b
HC		 447 video: video@1e700000 {
448 compatible = "aspeed,ast2600-video-engine";
449 reg = <0x1e700000 0x1000>;
450 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
451 <&syscon ASPEED_CLK_GATE_ECLK>;
452 clock-names = "vclk", "eclk";
453 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
454 status = "disabled";
455 };
456
8dbcb5b7
RG		 457 gpio0: gpio@1e780000 {
458 #gpio-cells = <2>;
459 gpio-controller;
460 compatible = "aspeed,ast2600-gpio";
886f82ce 461 reg = <0x1e780000 0x400>;
8dbcb5b7
RG		 462 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
463 gpio-ranges = <&pinctrl 0 0 208>;
464 ngpios = <208>;
465 clocks = <&syscon ASPEED_CLK_APB2>;
466 interrupt-controller;
467 #interrupt-cells = <2>;
468 };
469
09eccdc9
SL		 470 sgpiom0: sgpiom@1e780500 {
471 #gpio-cells = <2>;
472 gpio-controller;
473 compatible = "aspeed,ast2600-sgpiom";
474 reg = <0x1e780500 0x100>;
475 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&syscon ASPEED_CLK_APB2>;
96fd598e 477 #interrupt-cells = <2>;
09eccdc9
SL		 478 interrupt-controller;
479 bus-frequency = <12000000>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_sgpm1_default>;
482 status = "disabled";
483 };
484
485 sgpiom1: sgpiom@1e780600 {
486 #gpio-cells = <2>;
487 gpio-controller;
488 compatible = "aspeed,ast2600-sgpiom";
489 reg = <0x1e780600 0x100>;
490 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&syscon ASPEED_CLK_APB2>;
96fd598e 492 #interrupt-cells = <2>;
09eccdc9
SL		 493 interrupt-controller;
494 bus-frequency = <12000000>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_sgpm2_default>;
497 status = "disabled";
498 };
499
8dbcb5b7
RG		 500 gpio1: gpio@1e780800 {
501 #gpio-cells = <2>;
502 gpio-controller;
503 compatible = "aspeed,ast2600-gpio";
504 reg = <0x1e780800 0x800>;
505 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
506 gpio-ranges = <&pinctrl 0 208 36>;
507 ngpios = <36>;
508 clocks = <&syscon ASPEED_CLK_APB1>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 };
512
2ca5646b
JS		 513 rtc: rtc@1e781000 {
514 compatible = "aspeed,ast2600-rtc";
515 reg = <0x1e781000 0x18>;
516 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
517 status = "disabled";
518 };
519
3eca037f
JS		 520 timer: timer@1e782000 {
521 compatible = "aspeed,ast2600-timer";
522 reg = <0x1e782000 0x90>;
523 interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
524 <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
525 <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
526 <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
527 <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
528 <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
529 <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
530 <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&syscon ASPEED_CLK_APB1>;
532 clock-names = "PCLK";
c998f40f 533 status = "disabled";
3eca037f
JS		 534 };
535
c0d3e181
JS		 536 uart1: serial@1e783000 {
537 compatible = "ns16550a";
538 reg = <0x1e783000 0x20>;
539 reg-shift = <2>;
540 reg-io-width = <4>;
541 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
543 resets = <&lpc_reset 4>;
544 no-loopback-test;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>;
547 status = "disabled";
548 };
549
2ca5646b
JS		 550 uart5: serial@1e784000 {
551 compatible = "ns16550a";
552 reg = <0x1e784000 0x1000>;
553 reg-shift = <2>;
554 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
556 no-loopback-test;
557 };
558
559 wdt1: watchdog@1e785000 {
560 compatible = "aspeed,ast2600-wdt";
561 reg = <0x1e785000 0x40>;
562 };
563
564 wdt2: watchdog@1e785040 {
565 compatible = "aspeed,ast2600-wdt";
566 reg = <0x1e785040 0x40>;
567 status = "disabled";
568 };
569
570 wdt3: watchdog@1e785080 {
571 compatible = "aspeed,ast2600-wdt";
572 reg = <0x1e785080 0x40>;
573 status = "disabled";
574 };
575
56d71b55 576 wdt4: watchdog@1e7850c0 {
2ca5646b
JS		 577 compatible = "aspeed,ast2600-wdt";
578 reg = <0x1e7850C0 0x40>;
579 status = "disabled";
580 };
581
ac2743a7
IW		 582 peci0: peci-controller@1e78b000 {
583 compatible = "aspeed,ast2600-peci";
584 reg = <0x1e78b000 0x100>;
585 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;
587 resets = <&syscon ASPEED_RESET_PECI>;
588 cmd-timeout-ms = <1000>;
589 clock-frequency = <1000000>;
590 status = "disabled";
591 };
592
12ce8bd3 593 lpc: lpc@1e789000 {
311bf0f1 594 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
12ce8bd3 595 reg = <0x1e789000 0x1000>;
311bf0f1 596 reg-io-width = <4>;
12ce8bd3
BB		 597
598 #address-cells = <1>;
599 #size-cells = <1>;
600 ranges = <0x0 0x1e789000 0x1000>;
601
311bf0f1
CWW		 602 kcs1: kcs@24 {
603 compatible = "aspeed,ast2500-kcs-bmc-v2";
604 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
605 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
45cd8bba 606 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
311bf0f1
CWW		 607 kcs_chan = <1>;
608 status = "disabled";
609 };
610
611 kcs2: kcs@28 {
612 compatible = "aspeed,ast2500-kcs-bmc-v2";
613 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
614 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
45cd8bba 615 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
311bf0f1
CWW		 616 status = "disabled";
617 };
618
619 kcs3: kcs@2c {
620 compatible = "aspeed,ast2500-kcs-bmc-v2";
621 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
622 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
45cd8bba 623 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
311bf0f1
CWW		 624 status = "disabled";
625 };
626
627 kcs4: kcs@114 {
628 compatible = "aspeed,ast2500-kcs-bmc-v2";
629 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
630 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
45cd8bba 631 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
311bf0f1
CWW		 632 status = "disabled";
633 };
634
635 lpc_ctrl: lpc-ctrl@80 {
636 compatible = "aspeed,ast2600-lpc-ctrl";
637 reg = <0x80 0x80>;
638 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
639 status = "disabled";
640 };
641
642 lpc_snoop: lpc-snoop@80 {
643 compatible = "aspeed,ast2600-lpc-snoop";
644 reg = <0x80 0x80>;
645 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
647 status = "disabled";
648 };
649
650 lhc: lhc@a0 {
651 compatible = "aspeed,ast2600-lhc";
652 reg = <0xa0 0x24 0xc8 0x8>;
653 };
654
655 lpc_reset: reset-controller@98 {
656 compatible = "aspeed,ast2600-lpc-reset";
657 reg = <0x98 0x4>;
658 #reset-cells = <1>;
12ce8bd3
BB		 659 };
660
f9241fe8
CWW		 661 uart_routing: uart-routing@98 {
662 compatible = "aspeed,ast2600-uart-routing";
663 reg = <0x98 0x8>;
664 status = "disabled";
665 };
666
311bf0f1
CWW		 667 ibt: ibt@140 {
668 compatible = "aspeed,ast2600-ibt-bmc";
669 reg = <0x140 0x18>;
670 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
a350dc62 671 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
311bf0f1 672 status = "disabled";
12ce8bd3
BB		 673 };
674 };
675
2ca5646b
JS		 676 sdc: sdc@1e740000 {
677 compatible = "aspeed,ast2600-sd-controller";
678 reg = <0x1e740000 0x100>;
679 #address-cells = <1>;
680 #size-cells = <1>;
681 ranges = <0 0x1e740000 0x10000>;
682 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
683 status = "disabled";
684
685 sdhci0: sdhci@1e740100 {
686 compatible = "aspeed,ast2600-sdhci", "sdhci";
687 reg = <0x100 0x100>;
688 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
689 sdhci,auto-cmd12;
690 clocks = <&syscon ASPEED_CLK_SDIO>;
691 status = "disabled";
692 };
693
694 sdhci1: sdhci@1e740200 {
695 compatible = "aspeed,ast2600-sdhci", "sdhci";
696 reg = <0x200 0x100>;
697 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
698 sdhci,auto-cmd12;
699 clocks = <&syscon ASPEED_CLK_SDIO>;
700 status = "disabled";
701 };
702 };
703
311b57f0 704 emmc_controller: sdc@1e750000 {
2ca5646b
JS		 705 compatible = "aspeed,ast2600-sd-controller";
706 reg = <0x1e750000 0x100>;
707 #address-cells = <1>;
708 #size-cells = <1>;
709 ranges = <0 0x1e750000 0x10000>;
710 clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
711 status = "disabled";
712
311b57f0 713 emmc: sdhci@1e750100 {
2ca5646b
JS		 714 compatible = "aspeed,ast2600-sdhci";
715 reg = <0x100 0x100>;
716 sdhci,auto-cmd12;
717 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&syscon ASPEED_CLK_EMMC>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&pinctrl_emmc_default>;
721 };
722 };
9ee6d17b 723
2aed40ee
JS		 724 vuart1: serial@1e787000 {
725 compatible = "aspeed,ast2500-vuart";
726 reg = <0x1e787000 0x40>;
727 reg-shift = <2>;
728 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&syscon ASPEED_CLK_APB1>;
730 no-loopback-test;
731 status = "disabled";
732 };
733
dda28c09
JS		 734 vuart3: serial@1e787800 {
735 compatible = "aspeed,ast2500-vuart";
736 reg = <0x1e787800 0x40>;
737 reg-shift = <2>;
738 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&syscon ASPEED_CLK_APB2>;
740 no-loopback-test;
741 status = "disabled";
742 };
743
2aed40ee
JS		 744 vuart2: serial@1e788000 {
745 compatible = "aspeed,ast2500-vuart";
746 reg = <0x1e788000 0x40>;
747 reg-shift = <2>;
748 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&syscon ASPEED_CLK_APB1>;
750 no-loopback-test;
751 status = "disabled";
752 };
753
dda28c09
JS		 754 vuart4: serial@1e788800 {
755 compatible = "aspeed,ast2500-vuart";
756 reg = <0x1e788800 0x40>;
757 reg-shift = <2>;
758 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&syscon ASPEED_CLK_APB2>;
760 no-loopback-test;
761 status = "disabled";
762 };
763
c0d3e181
JS		 764 uart2: serial@1e78d000 {
765 compatible = "ns16550a";
766 reg = <0x1e78d000 0x20>;
767 reg-shift = <2>;
768 reg-io-width = <4>;
769 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
771 resets = <&lpc_reset 5>;
772 no-loopback-test;
773 pinctrl-names = "default";
774 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
775 status = "disabled";
776 };
777
778 uart3: serial@1e78e000 {
779 compatible = "ns16550a";
780 reg = <0x1e78e000 0x20>;
781 reg-shift = <2>;
782 reg-io-width = <4>;
783 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
785 resets = <&lpc_reset 6>;
786 no-loopback-test;
787 pinctrl-names = "default";
788 pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
789 status = "disabled";
790 };
791
792 uart4: serial@1e78f000 {
793 compatible = "ns16550a";
794 reg = <0x1e78f000 0x20>;
795 reg-shift = <2>;
796 reg-io-width = <4>;
797 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
799 resets = <&lpc_reset 7>;
800 no-loopback-test;
801 pinctrl-names = "default";
802 pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>;
803 status = "disabled";
804 };
805
e360b84c
KC		 806 uart6: serial@1e790000 {
807 compatible = "ns16550a";
808 reg = <0x1e790000 0x20>;
809 reg-shift = <2>;
810 reg-io-width = <4>;
811 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>;
813 no-loopback-test;
814 pinctrl-names = "default";
815 pinctrl-0 = <&pinctrl_uart6_default>;
816
817 status = "disabled";
818 };
819
820 uart7: serial@1e790100 {
821 compatible = "ns16550a";
822 reg = <0x1e790100 0x20>;
823 reg-shift = <2>;
824 reg-io-width = <4>;
825 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>;
827 no-loopback-test;
828 pinctrl-names = "default";
829 pinctrl-0 = <&pinctrl_uart7_default>;
830
831 status = "disabled";
832 };
833
834 uart8: serial@1e790200 {
835 compatible = "ns16550a";
836 reg = <0x1e790200 0x20>;
837 reg-shift = <2>;
838 reg-io-width = <4>;
839 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>;
841 no-loopback-test;
842 pinctrl-names = "default";
843 pinctrl-0 = <&pinctrl_uart8_default>;
844
845 status = "disabled";
846 };
847
848 uart9: serial@1e790300 {
849 compatible = "ns16550a";
850 reg = <0x1e790300 0x20>;
851 reg-shift = <2>;
852 reg-io-width = <4>;
853 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>;
855 no-loopback-test;
856 pinctrl-names = "default";
857 pinctrl-0 = <&pinctrl_uart9_default>;
858
859 status = "disabled";
860 };
861
9ee6d17b
JS		 862 i2c: bus@1e78a000 {
863 compatible = "simple-bus";
864 #address-cells = <1>;
865 #size-cells = <1>;
866 ranges = <0 0x1e78a000 0x1000>;
867 };
868
41320001
JS		 869 fsim0: fsi@1e79b000 {
870 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
871 reg = <0x1e79b000 0x94>;
872 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names = "default";
874 pinctrl-0 = <&pinctrl_fsi1_default>;
875 clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
876 status = "disabled";
877 };
878
879 fsim1: fsi@1e79b100 {
880 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
881 reg = <0x1e79b100 0x94>;
882 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&pinctrl_fsi2_default>;
885 clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
886 status = "disabled";
887 };
7d4f0b0d
CWW		 888
889 udma: dma-controller@1e79e000 {
890 compatible = "aspeed,ast2600-udma";
891 reg = <0x1e79e000 0x1000>;
892 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
893 dma-channels = <28>;
894 #dma-cells = <1>;
895 status = "disabled";
896 };
2ca5646b
JS		 897 };
898 };
899};
900
f510f04c 901#include "aspeed-g6-pinctrl.dtsi"
9ee6d17b
JS		 902
903&i2c {
8bba55f7 904 i2c0: i2c-bus@80 {
9ee6d17b
JS		 905 #address-cells = <1>;
906 #size-cells = <0>;
9ee6d17b
JS		 907 reg = <0x80 0x80>;
908 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 909 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 910 resets = <&syscon ASPEED_RESET_I2C>;
911 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
912 bus-frequency = <100000>;
913 pinctrl-names = "default";
914 pinctrl-0 = <&pinctrl_i2c1_default>;
915 status = "disabled";
916 };
917
918 i2c1: i2c-bus@100 {
919 #address-cells = <1>;
920 #size-cells = <0>;
9ee6d17b
JS		 921 reg = <0x100 0x80>;
922 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 923 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 924 resets = <&syscon ASPEED_RESET_I2C>;
925 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
926 bus-frequency = <100000>;
927 pinctrl-names = "default";
928 pinctrl-0 = <&pinctrl_i2c2_default>;
929 status = "disabled";
930 };
931
932 i2c2: i2c-bus@180 {
933 #address-cells = <1>;
934 #size-cells = <0>;
9ee6d17b
JS		 935 reg = <0x180 0x80>;
936 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 937 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 938 resets = <&syscon ASPEED_RESET_I2C>;
939 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
940 bus-frequency = <100000>;
941 pinctrl-names = "default";
942 pinctrl-0 = <&pinctrl_i2c3_default>;
943 status = "disabled";
944 };
945
946 i2c3: i2c-bus@200 {
947 #address-cells = <1>;
948 #size-cells = <0>;
9ee6d17b
JS		 949 reg = <0x200 0x80>;
950 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 951 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 952 resets = <&syscon ASPEED_RESET_I2C>;
953 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
954 bus-frequency = <100000>;
955 pinctrl-names = "default";
956 pinctrl-0 = <&pinctrl_i2c4_default>;
957 status = "disabled";
958 };
959
960 i2c4: i2c-bus@280 {
961 #address-cells = <1>;
962 #size-cells = <0>;
9ee6d17b
JS		 963 reg = <0x280 0x80>;
964 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 965 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 966 resets = <&syscon ASPEED_RESET_I2C>;
967 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
968 bus-frequency = <100000>;
969 pinctrl-names = "default";
970 pinctrl-0 = <&pinctrl_i2c5_default>;
971 status = "disabled";
972 };
973
974 i2c5: i2c-bus@300 {
975 #address-cells = <1>;
976 #size-cells = <0>;
9ee6d17b
JS		 977 reg = <0x300 0x80>;
978 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 979 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 980 resets = <&syscon ASPEED_RESET_I2C>;
981 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
982 bus-frequency = <100000>;
983 pinctrl-names = "default";
984 pinctrl-0 = <&pinctrl_i2c6_default>;
985 status = "disabled";
986 };
987
988 i2c6: i2c-bus@380 {
989 #address-cells = <1>;
990 #size-cells = <0>;
9ee6d17b
JS		 991 reg = <0x380 0x80>;
992 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 993 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 994 resets = <&syscon ASPEED_RESET_I2C>;
995 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
996 bus-frequency = <100000>;
997 pinctrl-names = "default";
998 pinctrl-0 = <&pinctrl_i2c7_default>;
999 status = "disabled";
1000 };
1001
1002 i2c7: i2c-bus@400 {
1003 #address-cells = <1>;
1004 #size-cells = <0>;
9ee6d17b
JS		 1005 reg = <0x400 0x80>;
1006 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1007 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1008 resets = <&syscon ASPEED_RESET_I2C>;
1009 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1010 bus-frequency = <100000>;
1011 pinctrl-names = "default";
1012 pinctrl-0 = <&pinctrl_i2c8_default>;
1013 status = "disabled";
1014 };
1015
1016 i2c8: i2c-bus@480 {
1017 #address-cells = <1>;
1018 #size-cells = <0>;
9ee6d17b
JS		 1019 reg = <0x480 0x80>;
1020 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1021 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1022 resets = <&syscon ASPEED_RESET_I2C>;
1023 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1024 bus-frequency = <100000>;
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&pinctrl_i2c9_default>;
1027 status = "disabled";
1028 };
1029
1030 i2c9: i2c-bus@500 {
1031 #address-cells = <1>;
1032 #size-cells = <0>;
9ee6d17b
JS		 1033 reg = <0x500 0x80>;
1034 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1035 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1036 resets = <&syscon ASPEED_RESET_I2C>;
1037 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1038 bus-frequency = <100000>;
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&pinctrl_i2c10_default>;
1041 status = "disabled";
1042 };
1043
1044 i2c10: i2c-bus@580 {
1045 #address-cells = <1>;
1046 #size-cells = <0>;
9ee6d17b
JS		 1047 reg = <0x580 0x80>;
1048 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1049 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1050 resets = <&syscon ASPEED_RESET_I2C>;
1051 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1052 bus-frequency = <100000>;
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&pinctrl_i2c11_default>;
1055 status = "disabled";
1056 };
1057
1058 i2c11: i2c-bus@600 {
1059 #address-cells = <1>;
1060 #size-cells = <0>;
9ee6d17b
JS		 1061 reg = <0x600 0x80>;
1062 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1063 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1064 resets = <&syscon ASPEED_RESET_I2C>;
1065 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1066 bus-frequency = <100000>;
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&pinctrl_i2c12_default>;
1069 status = "disabled";
1070 };
1071
1072 i2c12: i2c-bus@680 {
1073 #address-cells = <1>;
1074 #size-cells = <0>;
9ee6d17b
JS		 1075 reg = <0x680 0x80>;
1076 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1077 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1078 resets = <&syscon ASPEED_RESET_I2C>;
1079 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1080 bus-frequency = <100000>;
1081 pinctrl-names = "default";
1082 pinctrl-0 = <&pinctrl_i2c13_default>;
1083 status = "disabled";
1084 };
1085
1086 i2c13: i2c-bus@700 {
1087 #address-cells = <1>;
1088 #size-cells = <0>;
9ee6d17b
JS		 1089 reg = <0x700 0x80>;
1090 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1091 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1092 resets = <&syscon ASPEED_RESET_I2C>;
1093 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1094 bus-frequency = <100000>;
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&pinctrl_i2c14_default>;
1097 status = "disabled";
1098 };
1099
1100 i2c14: i2c-bus@780 {
1101 #address-cells = <1>;
1102 #size-cells = <0>;
9ee6d17b
JS		 1103 reg = <0x780 0x80>;
1104 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1105 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1106 resets = <&syscon ASPEED_RESET_I2C>;
1107 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1108 bus-frequency = <100000>;
1109 pinctrl-names = "default";
1110 pinctrl-0 = <&pinctrl_i2c15_default>;
1111 status = "disabled";
1112 };
1113
1114 i2c15: i2c-bus@800 {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
9ee6d17b
JS		 1117 reg = <0x800 0x80>;
1118 compatible = "aspeed,ast2600-i2c-bus";
8bba55f7 1119 clocks = <&syscon ASPEED_CLK_APB2>;
9ee6d17b
JS		 1120 resets = <&syscon ASPEED_RESET_I2C>;
1121 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1122 bus-frequency = <100000>;
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&pinctrl_i2c16_default>;
1125 status = "disabled";
1126 };
1127};
Linux 6.x block layer and io_uring tree(s)